STMicroelectronics ST10 Series Owner's manual

This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Ref: ST10FPM
ST10
FAMILY PROGRAMMING MANUAL

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1 INTRODUCTION......................................................................................................... 3
2 STANDARD INSTRUCTION SET............................................................................... 4
2.1 ADDRESSING MODES............................................................................................... 4
2.1.1 Short adressing modes................................................................................................ 4
2.1.2 Long addressing mode................................................................................................ 5
2.1.3 DPP override mechanism............................................................................................ 6
2.1.4 Indirect addressing modes .......................................................................................... 6
2.1.5 Constants .................................................................................................................... 7
2.1.6 Branch target addressing modes................................................................................. 7
2.2 INSTRUCTION EXECUTION TIMES.......................................................................... 8
2.2.1 Definition of measurement units.................................................................................. 9
2.2.2 Minimum state times.................................................................................................... 10
2.2.3 Additional state times .................................................................................................. 10
2.3 INSTRUCTION SET SUMMARY................................................................................. 13
2.4 INSTRUCTION SET ORDERED BY FUNCTIONAL GROUP..................................... 15
2.5 INSTRUCTION SET ORDERED BY OPCODES........................................................ 26
2.6 INSTRUCTION CONVENTIONS................................................................................. 34
2.6.1 Instruction name.......................................................................................................... 34
2.6.2 Syntax.......................................................................................................................... 34
2.6.3 Operation..................................................................................................................... 34
2.6.4 Data types ................................................................................................................... 35
2.6.5 Description................................................................................................................... 35
2.6.6 Condition code.............................................................................................................35
2.6.7 Flags............................................................................................................................ 36
2.6.8 Addressing modes....................................................................................................... 37
2.7 ATOMIC AND EXTENDED INSTRUCTIONS ............................................................. 38
2.8 INSTRUCTION DESCRIPTIONS................................................................................ 39
3 MAC INSTRUCTION SET........................................................................................... 123
3.1 ADDRESSING MODES............................................................................................... 123
3.2 MAC INSTRUCTION EXECUTION TIME ................................................................... 124
3.3 MAC INSTRUCTION SET SUMMARY........................................................................ 124
3.4 MAC INSTRUCTION CONVENTIONS........................................................................ 126
3.4.1 Operands..................................................................................................................... 126
3.4.2 Operations................................................................................................................... 126
3.4.3 Abbreviations............................................................................................................... 126
3.4.4 Data addressing Modes............................................................................................... 126
3.4.5 Instruction format.........................................................................................................127
3.4.6 Flag states................................................................................................................... 127
3.4.7 Repeated instruction syntax........................................................................................ 127
3.4.8 Shift value.................................................................................................................... 127
3.5 MAC INSTRUCTION DESCRIPTIONS....................................................................... 127
4 REVISION HISTORY .................................................................................................. 170
TABLE OF CONTENTS Page

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September 2013
1 - INTRODUCTION
This programming manual details the instruction
set for the ST10 family of products. The manual is
arranged in two sections. Section 1 details the
standard instruction set and includes all of the
basic instructions.
Section 2 details the extension to the instruction
set provided by the MAC. The MAC instructions
are only available to devices containing the MAC,
refer to the datasheet for device-specific
information.
In the standard instruction set, addressing modes,
instruction execution times, minimum state times
and the causes of additional state times are
defined. Cross reference tables of instruction
mnemonics, hexadecimal opcode, address
modes and number of bytes, are provided for the
optimization of instruction sequences.
Instruction set tables ordered by functional group,
can be used to identify the best instruction for a
given application. Instruction set tables ordered
by hexadecimal opcode can be used to identify
specific instructions when reading executable
code i.e. during the de-bugging phase. Finally,
each instruction is described individually on a
page of standard format, using the conventions
defined in this manual. For ease of use, the
instructions are listed alphabetically.
The MAC instruction set is divided into its 5
functional groups: Multiply and Multiply-
Accumulate, 32-Bit Arithmetic, Shift, Compare
and Transfer Instructions. Two new addressing
modes supply the MAC with up to 2 new operands
per instruction.
Cross reference tables of MAC instruction
mnemonics by address mode, and MAC
instruction mnemonic by functional code can be
used for quick reference.
As for the standard instruction set, each
instruction has been described individually in a
standard format according to defined conventions.
For convenience, the instructions are described in
alphabetical order.
ST10
ST10 FAMILY PROGRAMMING MANUAL
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2 - STANDARD INSTRUCTION SET
2.1 - Addressing Modes
2.1.1 - Short adressing modes
The ST10 family of devices use several powerful
addressing modes for access to word, byte and bit
data. This section describes short, long and indi-
rect address modes, constants and branch target
addressing modes. Short addressing modes use
an implicit base offset address to specify the
24-bit physical address. Short addressing modes
give access to the GPR, SFR or bit-addressable
memory spacePhysicalAddress = BaseAddress +
∆x ShortAddress.
Note: ∆= 1 for byte GPRs, ∆= 2 for word GPRs
(see Table 1).
Rw, Rb
Specifies direct access to any GPR in the cur-
rently active context (register bank). Both ’Rw’and
’Rb’ require four bits in the instruction format. The
base address of the current register bank is deter-
mined by the content of register CP. ’Rw’ specifies
a 4-bit word GPR address relative to the base
address (CP), while ’Rb’ specifies a 4 bit byte
GPR address relative to the base address (CP).
reg
Specifies direct access to any (E)SFR or GPR in
the currently active context (register bank). ’reg’
requires eight bits in the instruction format. Short
’reg’ addresses from 00h to EFh always specify
(E)SFRs. In this case, the factor ’∆’ equals 2 and
the base address is 00’F000h for the standard
SFR area, or 00’FE00h for the extended ESFR
area. ‘reg’ accesses to the ESFR area require a
preceding EXT*R instruction to switch the base
address. Depending on the opcode of an instruc-
tion, either the total word (for word operations), or
the low byte (for byte operations) of an SFR can
be addressed via 'reg'. Note that the high byte of
an SFR cannot be accessed by the 'reg' address-
ing mode. Short 'reg' addresses from F0h to FFh
always specify GPRs. In this case, only the lower
four bits of 'reg' are significant for physical
address generation, therefore it can be regarded
as identical to the address generation described
for the 'Rb' and 'Rw' addressing modes.
bitoff
Specifies direct access to any word in the
bit-addressable memory space. 'bitoff' requires
eight bits in the instruction format. Depending on
the specified 'bitoff' range, different base
addresses are used to generate physical
addresses: Short 'bitoff' addresses from 00h to
7Fh use 00’FD00h as a base address, therefore
they specify the 128 highest internal RAM word
locations (00’FD00h to 00’FDFEh).Short 'bitoff'
addresses from 80h to EFh use 00’FF00h as a
base address to specify the highest internal SFR
word locations (00’FF00h to 00’FFDEh) or use
00’F100h as a base address to specify the highest
internal ESFR word locations (00’F100h to
00’F1DEh). ‘bitoff’ accesses to the ESFR area
require a preceding EXT*R instruction to switch
the base address. For short 'bitoff' addresses from
F0h to FFh, only the lowest four bits and the
contents of the CP register are used to generate
the physical address of the selected word GPR.
bitaddr
Any bit address is specified by a word address
within the bit-addressable memory space (see
'bitoff'), and by a bit position ('bitpos') within that
word. Thus, 'bitaddr' requires twelve bits in the
instruction format.
Table 1 : Short addressing mode summary
Mnemo Physical Address Short Address Range Scope of Access
Rw (CP) + 2*Rw Rw = 0...15 GPRs (Word) 16 values
Rb (CP) + 1*Rb Rb = 0...15 GPRs (Byte) 16 values
reg 00’FE00h
00’F000h
(CP)
(CP)
+ 2*reg
+ 2*reg
+ 2*(reg^0Fh)
+ 1*(reg^0Fh)
reg
reg
reg
reg
= 00h...EFh
= 00h...EFh
= F0h...FFh
= F0h...FFh
SFRs
ESFRs
GPRs
GPRs
(Word, Low byte)
(Word, Low byte)
(Word) 16 values
(Bytes) 16 values
bitoff 00’FD00h
00’FF00h
(CP)
+ 2*bitoff
+ 2*(bitoff^FFh)
+ 2*(bitoff^0Fh)
bitoff
bitoff
bitoff
= 00h...7Fh
= 80h...EFh
= F0h...FFh
RAM
SFR
GPR
Bit word offset 128 values
Bit word offset 128 values
Bit word offset 16 values
bitaddr Word offset as with bitoff
Immediate bit position bitoff bitpos = 00h...FFh = 0...15 Any single bit

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2.1.2 - Long addressing mode
Long addressing mode uses one of the four DPP
registers to specify a physical 18-bit or 24-bit
address. Any word or byte data within the entire
address space can be accessed in this mode. All
devices support an override mechanism for the
DPP addressing scheme (see section 2.1.3 - DPP
override mechanism).
Long addresses (16-bit) are treated in two parts.
Bits 13...0 specify a 14-bit data page offset, and
bits 15...14 specify the Data Page Pointer (1 of 4).
The DPP is used to generate the physical 24-bit
address (see Figure 1).
All ST10 devices support an address space of up
to 16MByte, so only the lower ten bits of the
selected DPP register content are concatenated
with the 14-bit data page offset to build the physi-
cal address.
Note: Word accesses on odd byte addresses
are not executed, but rather trigger a
hardware trap. After reset, the DPP regis-
ters are initialized so that all long
addresses are directly mapped onto the
identical physical addresses, within seg-
ment 0.
The long addressing mode is referred to by the mnemonic “mem”.
Figure 1 : Interpretation of a 16-bit long address
Table 2 : Summary of long address modes
Mnemo Physical Address Long Address Range Scope of Access
mem (DPP0) || mem^3FFFh 0000h...3FFFh Any Word or Byte
(DPP1) || mem^3FFFh 4000h...7FFFh
(DPP2) || mem^3FFFh 8000h...BFFFh
(DPP3) || mem^3FFFh C000h...FFFFh
mem pag || mem^3FFFh 0000h...FFFFh (14-bit) Any Word or Byte
mem seg || mem 0000h...FFFFh (16-bit) Any Word or Byte
0
15 14 13
16-bit Long Address
DPP0
DPP1
DPP2
DPP3
14-bit page offset
24-bit Physical Address
selects Data Page Pointer
0
9
023 1314

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2.1.3 - DPP override mechanism
The DPP override mechanism temporarily
bypasses the DPP addressing scheme. The
EXTP(R) and EXTS(R) instructions override this
addressing mechanism. Instruction EXTP(R)
replaces the content of the respective DPP
register, while instruction EXTS(R) concatenates
the complete 16-bit long address with the
specified segment base address. The overriding
page or segment may be specified directly as a
constant (#pag, #seg) or by a word GPR (Rw)
(see Figure 2).
2.1.4 - Indirect addressing modes
Indirect addressing modes can be considered as a
combination of short and long addressing modes.
In this mode, long 16-bit addresses are specified
indirectly by the contents of a word GPR, which is
specified directly by a short 4-bit address (’Rw’=0
to 15). Some indirect addressing modes add a
constant value to the GPR contents before the
long 16-bit address is calculated. Other indirect
addressing modes allow decrementing or incre-
menting of the indirect address pointers(GPR con-
tent) by 2 or 1 (referring to words or bytes).
In each case, one of the four DPP registers is
used to specify the physical 18-bit or 24-bit
addresses. Any word or byte data within the entire
memory space can be addressed indirectly. Note
that EXTP(R) and EXTS(R) instructions override
the DPP mechanism.
Instructions using the lowest four word GPRs
(R3...R0) as indirect address pointers are speci-
fied by short 2-bit addresses.
Word accesses on odd byte addresses are not
executed, but rather trigger a hardware trap.
After reset, the DPP registers are initialized in a
way that all indirect long addresses are directly
mapped onto the identical physical addresses.
Physical addresses are generated from indirect
address pointers by the following algorithm:
1. Calculate the physical address of the word
GPR which is used as indirect address pointer, by
using the specified short address (’Rw’) and the
current register bank base address (CP).
GPRAddress = (CP) + 2 x ShortAddress
2. Pre-decremented indirect address pointers
(‘-Rw’) are decremented by a data-type-depen-
dent value (∆ = 1 for byte operations, ∆ = 2 for
word operations), before the long 16-bit address
is generated:
(GPRAddress) = (GPRAddress) - ∆ [optional step!]
3. Calculate the long 16-bit (Rw + #data16 if
selected) address by adding a constant value (if
selected) to the content of the indirect address
pointer:
Long Address = (GPR Address) + Constant
4. Calculate the physical 18-bit or 24-bit address
using the resulting long address and the corre-
sponding DPP register content (see long 'mem'
addressing modes).
Physical Address = (DPPi) + Long Address ^ 3FFFh
5. Post-Incremented indirect address pointers
(‘Rw+’) are incremented by a data-type-depen-
dent value (∆ = 1 for byte operations, ∆ = 2 for
word operations):
(GPR Address) = (GPR Address) + ∆ [optional step!]
Figure 2 : Overriding the DPP mechanism
0
15 14 13
16-bit Long Address
#pag 14-bit page offset
24-bit Physical Address
0
15
16-bit Long Address
#seg 16-bit segment offset
24-bit Physical Address
EXTP(R):
EXTS(R):

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The following indirect addressing modes are pro-
vided:
2.1.5 - Constants
The ST10 Family instruction set supports the use
of wordwide or bytewide immediate constants.
For optimum utilization of the available code stor-
age, these constants are represented in the
instruction formats by either 3, 4, 8 or 16 bits.
Therefore, short constants are always
zero-extended, while long constants can be trun-
cated to match the data format required for the
operation:
Note: Immediate constants are always signified
by a leading number sign “#”.
2.1.6 - Branch target addressing modes
Jump and Call instructions use different address-
ing modes to specify the target address and seg-
ment.
Relative, absolute and indirect modes can be
used to update the Instruction Pointer register
(IP), while the Code Segment Pointer register
(CSP) can only be updated with an absolute
value.
A special mode is provided to address the
interrupt and trap jump vector table situated in the
lowest portion of code segment 0.
Table 3 : Table of indirect address modes
Mnemonic Notes
[Rw] Most instructions accept any GPR
(R15...R0) as indirect address pointer.
Some instructions, however, only
accept the lower four GPRs (R3...R0).
[Rw+] The specified indirect address pointer
is automatically incremented by 2 or 1
(for word or byte data operations) after
the access.
[-Rw] The specified indirect address pointer
is automatically decremented by 2 or 1
(for word or byte data operations)
before the access.
[Rw+#data16] A 16-bit constant and the contents of
the indirect address pointer are added
before the long 16-bit address is calcu-
lated.
Table 4 : Table of constants
Mnemonic Word operation Byte operation
#data30000h+ data300h+ data3
#data40000h+ data400h+ data4
#data80000h+ data8data8
#data16 data16 data16 ^ FFh
#mask 0000h+ mask mask
Table 5 : Branch target address summary
Mnemonic Target Address Target Segment Valid Address Range
caddr (IP) = caddr - caddr = 0000h...FFFEh
rel (IP) = (IP) + 2*rel - rel = 00h...7Fh
(IP) = (IP) + 2*(~rel+1) - rel = 80h...FFh
[Rw] (IP) = ((CP) + 2*Rw) - Rw = 0...15
seg - (CSP) = seg seg = 0...255
#trap7(IP) = 0000h + 4*trap7(CSP) = 0000h trap7= 00h...7Fh

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caddr
Specifies an absolute 16-bit code address within
the current segment. Branches MAY NOT be
taken to odd code addresses.
Therefore, the least significant bit of ’caddr’ must
always contain a ’0’, otherwise a hardware trap
would occur.
rel
Represents an 8-bit signed word offset address
relative to the current Instruction Pointer contents
which points to the instruction after the branch
instruction.
Depending on the offset address range, either for-
ward (’rel’= 00h to 7Fh) or backward (’rel’= 80h to
FFh) branches are possible.
The branch instruction itself is repeatedly exe-
cuted, when ’rel’ = ’-1’ (FFh) for a word-sized
branch instruction, or ’rel’ = ’-2’ (FEh) for a dou-
ble-word-sized branch instruction.
[Rw]
The 16-bit branch target instruction address is
determined indirectly by the content of a word
GPR. In contrast to indirect data addresses, indi-
rectly specified code addresses are NOT calcu-
lated by additional pointer registers (e.g. DPP
registers).
Branches MAY NOT be taken to odd code
addresses. Therefore, to prevent a hardware trap,
the least significant bit of the address pointer GPR
must always contain a ’0.
seg
Specifies an absolute code segment number. All
devices support 256 different code segments, so
only the eight lower bits of the ’seg’ operand value
are used for updating the CSP register.
#trap7
Specifies a particular interrupt or trap number for
branching to the corresponding interrupt or trap
service routine by a jump vector table.
Trap numbers from 00h to 7Fh can be specified,
which allows access to any double word code
location within the address range
00’0000h...00’01FCh in code segment 0 (i.e. the
interrupt jump vector table).
For further information on the relation between
trap numbers and interrupt or trap sources, refer
to the device user manual section on “Interrupt
and Trap Functions”.
2.2 - Instruction execution times
The instruction execution time depends on where
the instruction is fetched from, and where the
operands are read from or written to.
The fastest processing mode is to execute a pro-
gram fetched from the internal ROM. In this case
most of the instructions can be processed in just
one machine cycle.
All external memory accesses are performed by
the on-chip External Bus Controller (EBC) which
works in parallel with the CPU.
Instructions from external memory cannot be pro-
cessed as fast as instructions from the internal
ROM, because it is necessary to perform data
transfers sequentially via the external interface.
In contrast to internal ROM program execution,
the time required to process an external program
additionally depends on the length of the instruc-
tions and operands, on the selected bus mode,
and on the duration of an external memory cycle.
Processing a program from the internal RAM
space is not as fast as execution from the internal
ROM area, but it is flexible (i.e. for loading tempo-
rary programs into the internal RAM via the chip's
serial interface, or end-of-line programming via
the bootstrap loader).
The following description evaluates the minimum
and maximum program execution times. which is
sufficient for most requirements. For an exact
determination of the instructions' state times, the
facilities provided by simulators or emulators
should be used.
This section defines measurement units, summa-
rizes the minimum (standard) state times of the
16-bit microcontroller instructions, and describes
the exceptions from the standard timing.

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2.2.1 - Definition of measurement units
The following measurement units are used to define instruction processing times:
[fCPU]: CPU operating frequency (may vary from 1MHz to 80MHz).
[State]: One state time is specified by one CPU clock period. Therefore, one State is used as the basic
time unit, because it represents the shortest period of time which has to be considered for
instruction timing evaluations.
1 [State] = 1/
f
CPU[s] ; for
f
CPU = variable
= 50[ns] ; for
f
CPU = 20MHz
[ACT]: ALE (Address Latch Enable) Cycle Time specifies the time required to perform one external
memory access. One ALE Cycle Time consists of either two (for demultiplexed external bus
modes) or three (for multiplexed external bus modes) state times plus a number of state times,
which is determined by the number of waitstates programmed in the MCTC (Memory Cycle
Time Control) and MTTC (Memory Tristate Time Control) bit fields of the SYSCON/BUSCONx
registers.
For demultiplexed external bus modes:
1*ACT = (2 + (15 – MCTC) + (1 – MTTC)) * States
= 100 n... 900 ns ; for
f
CPU = 20MHz
For multiplexed external bus modes:
1*ACT = (3 + (15 – MCTC) + (1 – MTTC)) * States
= 150ns ... 950ns ; for
f
CPU = 20MHz
Ttot The total time (
T
tot) taken to process a particular part of a program can be calculated by the
sum of the single instruction processing times (
T
In) of the considered instructions plus an offset
value of 6 state times which takes into account the solitary filling of the pipeline:
Ttot =TI1 + TI2 + ... + TIn + 6 * States
TIn The time (
T
In) taken to process a single instruction, consists of a minimum number (
T
Imin)
plus an additional number (
T
Iadd) of instruction state times and/or ALE Cycle Times:
TIn =TImin + TIadd

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2.2.2 - Minimum state times
The table below shows the minimum number of
state times required to process an instruction
fetched from the internal ROM (
T
Imin (ROM)).
This table can also be used to calculate the mini-
mum number of state times for instructions
fetched from the internal RAM (
T
Imin (RAM)), or
ALE Cycle Times for instructions fetched from the
external memory (
T
Imin (ext)).
Most of the 16-bit microcontroller instructions
(except some branch, multiplication, division and
a special move instructions) require a minimum of
two state times. For internal ROM program execu-
tion, execution time has no dependence on
instruction length, except for some special branch
situations.
To evaluate the execution time for the injected tar-
get instruction of a cache jump instruction, it can
be considered as if it was executed from the inter-
nal ROM, regardless of which memory area the
rest of the current program is really fetched from.
For some of the branch instructions the table
below represents both the standard number of
state times (i.e. the corresponding branch is
taken) and an additional
T
Imin value in parenthe-
ses, which refers to the case where, either the
branch condition is not met, or a cache jump is
taken.
Instructions executed from the internal RAM
require the same minimum time as they would if
they were fetched from the internal ROM, plus an
instruction-length dependent number of state
times, as follows:
– For 2-byte instructions:
T
Imin(RAM) =
T
Imin(ROM) + 4 * States
– For 4-byte instructions:
T
Imin(RAM) =
T
Imin(ROM) + 6 * States
Unlike internal ROM program execution, the mini-
mum time
T
Imin(ext) to process an external
instruction also depends on instruction length.
T
Imin(ext) is either 1 ALE Cycle Time for most of
the 2-byte instructions, or 2 ALE Cycle Times for
most of the 4-byte instructions.
The following formula represents the minimum
execution time of instructions fetched from an
external memory via a 16-bit wide data bus:
– For 2-byte instructions:
T
Imin(ext) = 1*ACT + (
T
Imin(ROM) - 2) * States
– For 4-byte instructions:
T
Imin(ext) = 2*ACTs + (
T
Imin(ROM) - 2) * States
Note: For instructions fetched from an external
memory via an 8-bit wide data bus, the
minimum number of required ALE Cycle
Times is twice the number for those of a
16-bit wide bus.
2.2.3 - Additional state times
Some operand accesses can extend the execu-
tion time of an instruction
T
In. Since the additional
time
T
Iadd is generally caused by internal instruc-
tion pipelining, it may be possible to minimize the
effect by rearranging the instruction sequences.
Simulators and emulators offer a high level of pro-
grammer support for program optimization.
The following operands require additional state
times:
Internal ROM operand reads:
T
Iadd = 2 * States
Both byte and word operand reads always require
2 additional state times.
Table 6 : Minimum instruction state times [Unit = ns]
Instruction
T
Imin
(ROM)
[States]
T
Imin (ROM)
(20MHz
CPU clk)
CALLI, CALLA
CALLS, CALLR, PCALL
JB, JBC, JNB, JNBS
JMPS
JMPA, JMPI, JMPR
MUL, MULU
DIV, DIVL, DIVU, DIVLU
MOV[B] Rn, [Rm + #data16]
RET, RETI, RETP, RETS
TRAP
All other instructions
4
4
4
4
4
10
20
4
4
4
2
(2)
(2)
(2)
200
200
200
200
200
500
1000
200
200
200
100
(100)
(100)
(100)

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Internal RAM operand reads via indirect addressing modes: T
Iadd = 0 or 1 * State
Reading a GPR or any other directly addressed operand within the internal RAM space does NOT cause
additional state time. However, reading an indirectly addressed internal RAM operand will extend the pro-
cessing time by 1 state time, if the preceding instruction auto-increments or auto-decrements a GPR, as
shown in the following example:
In this case, the additional time can be avoided by putting another suitable instruction before the instruc-
tion
I
n+1 indirectly reading the internal RAM.
Internal SFR operand reads:
T
Iadd = 0, 1 * State or 2 * States
SFR read accesses do NOT usually require additional processing time. In some rare cases, however,
either one or two additional state times will be caused by particular SFR operations:
– Reading an SFR immediately after an instruction, which writes to the internal SFR space, as shown in
the following example:
– Reading the PSW register immediately after an instruction which implicitly updates the flags as shown
in the following example:
– Implicitly incrementing or decrementing the SP register immediately after an instruction which explicitly
writes to the SP register, as shown in the following example:
In each of these above cases, the extra state times can be avoided by putting other suitable instructions
before the instruction
I
n+1 reading the SFR.
External operand reads:
T
Iadd = 1 * ACT
Any external operand reading via a 16-bit wide data bus requires one additional ALE Cycle Time. Read-
ing word operands via an 8-bit wide data bus takes twice as much time (2 ALE Cycle Times) as the read-
ing of byte operands.
External operand writes:
T
Iadd = 0 * State ... 1 * ACT
Writing an external operand via a 16-bit wide data bus takes one additional ALE Cycle Time. For timing
calculation of the external program parts, this extra time must always be considered. The value of
T
Iadd
which must be considered for timing evaluations of internal program parts, may fluctuate between 0 state
times and 1 ALE Cycle Time. This is because external writes are normally performed in parallel to other
CPU operations. Thus,
T
Iadd could already have been considered in the standard processing time of
another instruction. Writing a word operand via an 8-bit wide data bus requires twice as much time (2 ALE
Cycle Times) as the writing of a byte operand.
In: MOV R1, [R0+] ; auto-increment R0
In+1 : MOV [R3], [R2] ; if R2 points into the internal RAM space:
; TIadd = 1 * State
In: MOV T0, #1000h ; write to Timer 0
In+1 : ADD R3, T1 ; read from Timer 1: TIadd = 1 * State
In: ADD R0, #1000h ; implicit modification of PSW flags
In+1 : BAND C, Z ; read from PSW: TIadd = 2 * States
In: MOV SP, #0FB00h ; explicit update of the stack pointer
In+1 : SCXT R1, #1000h ; implicit decrement of the stack pointer:
; TIadd = 2 * States

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Jumps into the internal ROM space: T
Iadd = 0 or 2 * States
The minimum time of 4 state times for standard jumps into the internal ROM space will be extended by 2
additional state times, if the branch target instruction is a double word instruction at a non-aligned double
word location (xxx2h, xxx6h, xxxAh, xxxEh), as shown in the following example:
A cache jump, which normally requires just 2 state times, will be extended by 2 additional state times, if
both the cached jump target instruction and the following instruction are non-aligned double word instruc-
tions, as shown in the following example:
If necessary, these extra state times can be avoided by allocating double word jump target instructions to
aligned double word addresses (xxx0h, xxx4h, xxx8h, xxxCh).
Testing Branch Conditions:
T
Iadd = 0 or 1 * States
NO extra time is usually required for a conditional branch instructions to decide whether a branch condi-
tion is met or not. However, an additional state time is required if the preceding instruction writes to the
PSW register, as shown in the following example:
In this case, the extra state time can be intercepted by putting another suitable instruction before the con-
ditional branch instruction.
label : .... ; any non-aligned double word instruction
; (e.g. at location 0FFEh)
.... : ....
In+1 : JMPA cc_UC, label ; if a standard branch is taken:
; TIadd = 2 *States (TIn = 6 *States)
label : .... ; any non-aligned double word instruction
; (e.g. at location 12FAh)
In+1 :.... ; any non-aligned double word instruction
; (e.g. at location 12FEh)
In+2 : JMPR cc_UC, label ; provided that a cache jump is taken:
; TIadd = 2 * States (TIn = 4 * States)
In: BSET USR0 ; implicit modification of PSW flags
In+1 : JMPR cc_Z, label ; test condition flag in PSW: TIadd= 1 * State

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Highi
Low xF xE xD xC xB xA x9 x8 x7 x6 x5 x4 x3 x2 x1 x0
0x
BSET BITaddrQ.q
BCLR BITaddrQ.q
JMPR cc, rel
ROL MUL BFLDL ADDB ADD ADDB ADD ADDB ADD ADDB ADD ADDB ADD
Rw
n
, Rw
m
Rw
n
, Rw
m
BITOFF, MASK,
#data
3
Rw
n
, [Rw
i
]
Rw
n
, [Rw
i
+]
Rw
n
, #data
3
REG, #data
16
MEM, REG REG, MEM Rw
n
, Rw
m
1x ROL
Rw
n
, #d
4
MULU BFLDH ADDCB ADDC ADDCB ADDC ADDCB ADDC ADDCB ADDC ADDCB ADDC
2x ROR PRIOR BCMP SUBB SUB SUBB SUB SUBB SUB SUBB SUB SUBB SUB
Rw
n
, Rw
m
Rw
n
, Rw
m
BITadd, BITadd Rw
n
, [Rw
i
]
Rw
n
, [Rw
i
+]
Rw
n
, #data
3
REG, #data
16
MEM, REG REG, MEM Rw
n
, Rw
m
3x ROR _BMOVN
Rw
n
, #d
4
BITadd, BITadd SUBCB SUBC SUBCB SUBC SUBCB SUBC SUBCB SUBC SUBCB SUBC
4x SHL DIV BMOV CMPB CMP CMPB CMP _ _ CMPB CMP CMPB CMP
Rw
n
, Rw
m
Rw
n
BITadd, BITadd Rw
n
, [Rw
i
]
Rw
n
, [Rw
i
+]
Rw
n
, #data
3
REG, #data
16
MEM, REG REG, MEM Rw
n
, Rw
m
5x SHL DIVU BOR
Rw
n
, #d
4
Rw
n
BITadd, BITadd XORB XOR XORB XOR XORB XOR XORB XOR XORB XOR
6x SHR DIVL BAND ANDB AND ANDB AND ANDB AND ANDB AND ANDB AND
Rw
n
, Rw
m
Rw
n
BITadd, BITadd Rw
n
, [Rw
i
]
Rw
n
, [Rw
i
+]
Rw
n
, #data
3
REG, #data
16
MEM, REG REG, MEM Rw
n
, Rw
m
7x SHR DIVLU BXOR
Rw
n
, #d
4
Rw
n
BITadd, BITadd ORB OR ORB OR ORB OR ORB OR ORB OR
8x _ _ JB MOVB MOV IDLE CMPI1 _MOV CoXXX CMPI NEG CMPI1
BITadd, REL [-Rw
m
], Rw
n
Rw
n
, #d
16
[Rw
n
], MEM Rw
n
, [Rw
m
⊗]Rw
n
, MEM Rw
n
Rw
n
, #d
4
9x JMPI TRAP MOVB MOV PWRDN _MOV CoXXX
cc, [Rw
n
]#trap JNB Rw
n
, [Rw
m
+] CMPI2 MEM, [Rw
n
] [IDXI⊗], [Rw
m
⊗]CMPD2 CPLB CMPD2
Ax ASHR CALLI JBC MOVB MOV SRVWDT CMPD1 DISWDT MOVB CoXXX CMPD1 NEGB CMPD1
Rw
n
, Rw
m
cc, [Rw
n
]BITadd, BITadd [Rw
n
], Rw
m
Rw
n
, #d
16
[Rw
n
], MEM Rw
n
, Rw
m
Rw
n
, MEM Rw
n
Rw
n
, #d
4
Bx ASHR CALLR MOVB MOV SRST EINIT MOVB CoSTORE
Rw
n
, #d
4
REL JNBS [Rw
m
], Rw
n
CMPD2 [Rw
m
+ #d
16
], Rw
n
Rw
n
, CoREG CMPD2 CPLB CMPD2
Cx NOP RET CALLA MOVB MOV _ SCXT MOVBZ MOV CoSTORE MOVBZ _ MOVBZ
CC, CADDR [Rw
n
], [Rw
m
] REG, #d
16
MEM, REG Rw
n
, [Rw
m
+ #d
16
][Rw
n
⊗], CoREG REG, MEM Rw
n
, Rw
m
Dx
EXTP(R)/ RETS CALLS MOVB MOV EXTP(R)/ SCXT MOV CoMOV ATOMIC/EXTR
EXTS(R) EXTS(R) REG, MEM [Rw
m
+ #d
16
], Rw
n
[IDXI⊗], [Rw
m
⊗]#data
2
Rw
m
, #d
2
SEG, CADDDR [Rw
n+
], [Rw
m
]#pag, #data2 MOVBS MOVBS MOVBS
Ex PUSH RETP JMPA MOVB MOV MOVB MOV _ MOVB _ PCALL MOVB MOV
REG REG CC, CADDR [Rw
n
], [Rw
m
+] REG, Data#
16
Rw
n
, [Rw
m
+ #d
16
]REG, CADDR Rw
n
, #data
4
Fx JMPS _ _ MOVB MOV _ MOVB MOVB MOV MOVB MOV
POP RETI SEG, CADDR MEM, REG [Rw
m
+ #d
16
], Rw
n
REG, MEM Rw
n
, #data
4
2.3 - Instruction set summary
The following table lists the instruction mnemonic by hex-code with operand.
Table 7 : Instruction mnemonic by hex-code with operand

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Table 8 lists the instructions by their mnemonic and identifies the addressing modes that may be used with
a specific instruction and the instruction length, depending on the selected addressing mode (in bytes).
Table 8 : Mnemonic vs address mode & number of bytes
Mnemonic Addressing Modes Bytes Mnemonic Addressing Modes Bytes
ADD[B] Rwn1, Rwm12 CPL[B] Rwn12
ADDC[B] Rwn1, [Rwi] 2 NEG[B]
AND[B] Rwn1, [Rwi+] 2 DIV Rwn2
OR[B] Rwn1, #data32 DIVL
SUB[B] reg, #data16 4 DIVLU
SUBC[B] reg, mem 4 DIVU
XOR[B] mem, reg 4 MUL Rwn, Rwm2
MULU
ASHR Rwn, Rwm2 CMPD1/2 Rwn, #data42
ROL / ROR Rwn, #data42 CMPI1/2 Rwn, #data16 4
SHL / SHR Rwn, mem 4
BAND bitaddrZ.z, bitaddrQ.q 4 CMP[B] Rwn, Rwm1
BCMP Rwn, [Rwi] 12
BMOV Rwn, [Rwi+]12
BMOVN Rwn, #data312
BOR / BXOR reg, #data16 4
reg, mem 4
BCLR bitaddrQ.q, 2 CALLA cc, caddr 4
BSET JMPA
BFLDH bitoffQ,#mask8,#data84 CALLI cc, [Rwn]2
BFLDL JMPI
MOV[B] Rwn1, Rwm12CALLS seg, caddr 4
Rwn1, #data42JMPS
Rwn1, [Rwm]2CALLR rel 2
Rwn1, [Rwm+] 2JMPR cc, rel 2
[Rwm], Rwn12JB bitaddrQ.q,rel 4
[-Rwm], Rwn12JBC
[Rwn], [Rwm]2JNB
[Rwn+], [Rwm]2JNBS
[Rwn], [Rwm+] 2PCALL reg, caddr 4
reg, #data16 4POP reg 2
Rwn, [Rwm+#data16]14PUSH
[Rwm+#data16], Rwn14RETP
[Rwn], mem 4SCXT reg, #data16 4
mem, [Rwn]4reg, mem 4
reg, mem 4PRIOR Rwn, Rwm2
mem, reg 4

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Note 1. Byte oriented instructions (suffix ‘B’) use Rb instead of Rw (not with [Rw
i
]!).
2.4 - Instruction set ordered by functional
group
The minimum number of state times required for
instruction execution are given for the following
configurations: internal ROM, internal RAM, exter-
nal memory with a 16-bit demultiplexed and multi-
plexed bus or an 8-bit demultiplexed and
multiplexed bus. These state time figures do not
take into account possible wait states on external
busses or possible additional state times induced
by operand fetches. The following notes apply to
this summary:
Data addressing modes
Rw: Word GPR (R0, R1, … , R15).
Rb: Byte GPR (RL0, RH0, …, RL7, RH7).
reg: SFR or GPR (in case of a byte operation
on an SFR, only the low byte can be
accessed via ‘reg’).
mem: Direct word or byte memory location.
[…]: Indirect word or byte memory location.
(Any word GPR can be used as indirect
address pointer, except for the arithmetic,
logical and compare instructions, where
only R0 to R3 are allowed).
bitaddr: Direct bit in the bit-addressable memory
area.
bitoff: Direct word in the bit-addressable mem-
ory area.
#datax: Immediate constant (the number of signif-
icant bits that can be user-specified is
given by the appendix “x”).
#mask8:Immediate 8-bit mask used for bit-field
modifications.
Multiply and divide operations
The MDL and MDH registers are implicit source
and/or destination operands of the multiply and
divide instructions.
Branch target addressing modes
caddr: Direct 16-bit jump target address
(Updates the Instruction Pointer).
seg: Direct 8-bit segment address (Updates
the Code Segment Pointer).
rel: Signed 8-bit jump target word offset
address relative to the Instruction
Pointer of the following instruction.
#trap7: Immediate 7-bit trap or interrupt number.
Extension operations
The EXT* instructions override the standard DPP
addressing scheme:
#pag: Immediate 10-bit page address.
#seg: Immediate 8-bit segment address.
MOVBS Rwn, Rbm2TRAP #trap7 2
MOVBZ reg, mem 4ATOMIC #data2 2
mem, reg 4EXTR
EXTS Rwm, #data2 2EXTP Rwm,#data22
EXTSR #seg, #data24EXTPR #pag, #data24
NOP - 2SRST/IDLE - 4
RET PWRDN
RETI SRVWDT
RETS = DISWDT
EINIT
Table 8 : Mnemonic vs address mode & number of bytes (continued)
Mnemonic Addressing Modes Bytes Mnemonic Addressing Modes Bytes

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Branch condition codes
cc: Symbolically specifiable condition codes
cc_UC Unconditional
cc_Z Zero
cc_NZ Not Zero
cc_V Overflow
cc_NV No Overflow
cc_N Negative
cc_NN Not Negative
cc_C Carry
cc_NC No Carry
cc_EQ Equal
cc_NE Not Equal
cc_ULT Unsigned Less Than
cc_ULE Unsigned Less Than or Equal
cc_UGE Unsigned Greater Than or Equal
cc_UGT Unsigned Greater Than
cc_SLE Signed Less Than or Equal
cc_SLT Signed Less Than
cc_SGE Signed Greater Than or Equal
cc_SGT Signed Greater Than
cc_NET NotEqualandNotEnd-of-Table
Table 9 : Arithmetic instructions
Mnemonic Description
Int.ROM
Int.RAM
16-bit N-Mux
16-bit Mux
8-bit N-Mux
8-bit Mux
Bytes
ADD Rw, Rw Add direct word GPR to direct GPR 2 6 2 3 4 6 2
ADD Rw, [Rw] Add indirect word memory to direct GPR 2 6 2 3 4 6 2
ADD Rw, [Rw+] Add indirect word memory to direct GPR and post-
increment source pointer by 2 262346 2
ADD Rw, #data3Add immediate word data to direct GPR 2 6 2 3 4 6 2
ADD reg, #data16 Add immediate word data to direct register 2 8 4 6 8 12 4
ADD reg, mem Add direct word memory to direct register 2 8 4 6 8 12 4
ADD mem, reg Add direct word register to direct memory 2 8 4 6 8 12 4
ADDB Rb, Rb Add direct byte GPR to direct GPR 2 6 2 3 4 6 2
ADDB Rb, [Rw] Add indirect byte memory to direct GPR 2 6 2 3 4 6 2
ADDB Rb, [Rw+] Add indirect byte memory to direct GPR and post-increment
source pointer by 1 262346 2
ADDB Rb, #data3Add immediate byte data to direct GPR 2 6 2 3 4 6 2
ADDB reg, #data16 Add immediate byte data to direct register 2 8 4 6 8 12 4
ADDB reg, mem Add direct byte memory to direct register 2 8 4 6 8 12 4
ADDB mem, reg Add direct byte register to direct memory 2 8 4 6 8 12 4
ADDC Rw, Rw Add direct word GPR to direct GPR with Carry 2 6 2 3 4 6 2
ADDC Rw, [Rw] Add indirect word memory to direct GPR with Carry 2 6 2 3 4 6 2
ADDC Rw, [Rw+] Add indirect word memory to direct GPR with Carry and
post-increment source pointer by 2 262346 2
ADDC Rw, #data3Add immediate word data to direct GPR with Carry 2 6 2 3 4 6 2
ADDC reg, #data16 Add immediate word data to direct register with Carry 2 8 4 6 8 12 4
ADDC reg, mem Add direct word memory to direct register with Carry 2 8 4 6 8 12 4
ADDC mem, reg Add direct word register to direct memory with Carry 2 8 4 6 8 12 4

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ADDCB Rb, Rb Add direct byte GPR to direct GPR with Carry 2 6 2 3 4 6 2
ADDCB Rb, [Rw] Add indirect byte memory to direct GPR with Carry 2 6 2 3 4 6 2
ADDCB Rb, [Rw+] Add indirect byte memory to direct GPR with Carry and
post-increment source pointer by 1 262346 2
ADDCB Rb, #data3Add immediate byte data to direct GPR with Carry 2 6 2 3 4 6 2
ADDCB reg, #data16 Add immediate byte data to direct register with Carry 2 8 4 6 8 12 4
ADDCB reg, mem Add direct byte memory to direct register with Carry 2 8 4 6 8 12 4
ADDCB mem, reg Add direct byte register to direct memory with Carry 2 8 4 6 8 12 4
CPL Rw Complement direct word GPR 2 6 2 3 4 6 2
CPLB Rb Complement direct byte GPR 2 6 2 3 4 6 2
DIV Rw Signed divide register MDL by direct GPR
(16-/16-bit) 20 24 20 21 22 24 2
DIVL Rw Signed long divide register MD by direct GPR
(32-/16-bit) 20 24 20 21 22 24 2
DIVLU Rw Unsigned long divide register MD by direct GPR
(32-/16-bit) 20 24 20 21 22 24 2
DIVU Rw Unsigned divide register MDL by direct GPR
(16-/16-bit) 20 24 20 21 22 24 2
MUL Rw, Rw Signed multiply direct GPR by direct GPR (16-16-bit) 10 14 10 11 12 14 2
MULU Rw, Rw Unsigned multiply direct GPR by direct GPR (16-16-bit) 10 14 10 11 12 14 2
NEG Rw Negate direct word GPR 2 6 2 3 4 6 2
NEGB Rb Negate direct byte GPR 2 6 2 3 4 6 2
SUB Rw, Rw Subtract direct word GPR from direct GPR 2 6 2 3 4 6 2
SUB Rw, [Rw] Subtract indirect word memory from direct GPR 2 6 2 3 4 6 2
SUB Rw, [Rw+] Subtract indirect word memory from direct GPR &
post-increment source pointer by 2 262346 2
SUB Rw, #data3Subtract immediate word data from direct GPR 2 6 2 3 4 6 2
SUB reg, #data16 Subtract immediate word data from direct register 2 8 4 6 8 12 4
SUB reg, mem Subtract direct word memory from direct register 2 8 4 6 8 12 4
SUB mem, reg Subtract direct word register from direct memory 2 8 4 6 8 12 4
SUBB Rb, Rb Subtract direct byte GPR from direct GPR 2 6 2 3 4 6 2
SUBB Rb, [Rw] Subtract indirect byte memory from direct GPR 2 6 2 3 4 6 2
SUBB Rb, [Rw+] Subtract indirect byte memory from direct GPR &
post-increment source pointer by 1 262346 2
SUBB Rb, #data3Subtract immediate byte data from direct GPR 2 6 2 3 4 6 2
SUBB reg, #data16 Subtract immediate byte data from direct register 2 8 4 6 8 12 4
Table 9 : Arithmetic instructions (continued)
Mnemonic Description
Int.ROM
Int.RAM
16-bit N-Mux
16-bit Mux
8-bit N-Mux
8-bit Mux
Bytes

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SUBB reg, mem Subtract direct byte memory from direct register 2 8 4 6 8 12 4
SUBB mem, reg Subtract direct byte register from direct memory 2 8 4 6 8 12 4
SUBC Rw, Rw Subtract direct word GPR from direct GPR with Carry 2 6 2 3 4 6 2
SUBC Rw, [Rw] Subtract indirect word memory from direct GPR with Carry 2 6 2 3 4 6 2
SUBC Rw, [Rw+] Subtract indirect word memory from direct GPR with Carry
and post-increment source pointer by 2 262346 2
SUBC Rw, #data3Subtract immediate word data from direct GPR with Carry 2 6 2 3 4 6 2
SUBC reg, #data16 Subtract immediate word data from direct register with
Carry 28468124
SUBC reg, mem Subtract direct word memory from direct register with Carry 2 8 4 6 8 12 4
SUBC mem, reg Subtract direct word register from direct memory with Carry 2 8 4 6 8 12 4
SUBCB Rb, Rb Subtract direct byte GPR from direct GPR with Carry 2 6 2 3 4 6 2
SUBCB Rb, [Rw] Subtract indirect byte memory from direct GPR with Carry 2 6 2 3 4 6 2
SUBCB Rb, [Rw+] Subtract indirect byte memory from direct GPR with Carry
and post-increment source pointer by 1 262346 2
SUBCB Rb, #data3Subtract immediate byte data from direct GPR with Carry 2 6 2 3 4 6 2
SUBCB reg, #data16 Subtract immediate byte data from direct register with Carry 2 8 4 6 8 12 4
SUBCB reg, mem Subtract direct byte memory from direct register with Carry 2 8 4 6 8 12 4
SUBCB mem, reg Subtract direct byte register from direct memory with Carry 2 8 4 6 8 12 4
Table 9 : Arithmetic instructions (continued)
Mnemonic Description
Int.ROM
Int.RAM
16-bit N-Mux
16-bit Mux
8-bit N-Mux
8-bit Mux
Bytes
Table 10 : Logical instructions
Mnemonic Description
Int ROM
Int. RAM
16-bit N-Mux
16-bit Mux
8-bit N-Mux
8-bit MUX
Bytes
AND Rw, Rw Bitwise AND direct word GPR with direct GPR 2 6 2 3 4 6 2
AND Rw, [Rw] Bitwise AND indirect word memory with direct GPR 2 6 2 3 4 6 2
AND Rw, [Rw+] Bitwise AND indirect word memory with direct GPR and
post-increment source pointer by 2 2623462
AND Rw, #data3Bitwise AND immediate word data with direct GPR 2 6 2 3 4 6 2
AND reg, #data16 Bitwise AND immediate word data with direct register 2 8 4 6 8 12 4
AND reg, mem Bitwise AND direct word memory with direct register 2 8 4 6 8 12 4
AND mem, reg Bitwise AND direct word register with direct memory 2 8 4 6 8 12 4
ANDB Rb, Rb Bitwise AND direct byte GPR with direct GPR 2 6 2 3 4 6 2
ANDB Rb, [Rw] Bitwise AND indirect byte memory with direct GPR 2 6 2 3 4 6 2