STMicroelectronics STM32L151RE User manual

This is information on a product in full production.
February 2016 DocID025433 Rev 8 1/134
STM32L151xE STM32L152xE
Ultra-low-power 32-bit MCU ARM®-based Cortex®-M3 with 512KB
Flash, 80KB SRAM, 16KB EEPROM, LCD, USB, ADC, DAC
Datasheet -production data
Features
•Ultra-low-power platform
– 1.65 V to 3.6 V power supply
–-40 °C to 105 °C temperature range
– 290 nA Standby mode (3 wakeup pins)
– 1.11 µA Standby mode + RTC
– 560 nA Stop mode (16 wakeup lines)
– 1.4 µA Stop mode + RTC
– 11 µA Low-power run mode down to 4.6 µA
in Low-power sleep mode
– 195 µA/MHz Run mode
– 10 nA ultra-low I/O leakage
– 8 µs wakeup time
•Core: ARM®Cortex®-M3 32-bit CPU
– From 32 kHz up to 32 MHz max
– 1.25 DMIPS/MHz (Dhrystone 2.1)
– Memory protection unit
•Up to 34 capacitive sensing channels
•CRC calculation unit, 96-bit unique ID
•Reset and supply management
– Low-power, ultrasafe BOR (brownout reset)
with 5 selectable thresholds
– Ultra-low-power POR/PDR
– Programmable voltage detector (PVD)
•Clock sources
– 1 to 24 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 16 MHz oscillator factory trimmed
RC(+/-1%) with PLL option
– Internal low-power 37 kHz oscillator
– Internal multispeed low-power 65 kHz to
4.2 MHz oscillator
– PLL for CPU clock and USB (48 MHz)
•Pre-programmed bootloader
– USB and USART supported
•Up to 116 fast I/Os (102 I/Os 5V tolerant), all
mappable on 16 external interrupt vectors
•Memories
– 512 KB Flash memory with ECC (with 2
banks of 256 KB enabling RWW capability)
– 80 KB RAM
– 16 KB of true EEPROM with ECC
– 128 Byte backup register
•LCD driver (except STM32L151xE devices) up
to 8x40 segments, contrast adjustment,
blinking mode, step-up converter
•Rich analog peripherals (down to 1.8 V)
– 2x operational amplifiers
– 12-bit ADC 1 Msps up to 40 channels
– 12-bit DAC 2 ch with output buffers
– 2x ultra-low-power comparators
(window mode and wake up capability)
•DMA controller 12x channels
•11x peripheral communication interfaces
– 1x USB 2.0 (internal 48 MHz PLL)
– 5x USARTs
– Up to 8x SPIs (2x I2S, 3x 16 Mbit/s)
– 2x I2Cs (SMBus/PMBus)
•11x timers: 1x 32-bit, 6x 16-bit with up to 4
IC/OC/PWM channels, 2x 16-bit basic timers,
2x watchdog timers (independent and window)
•Development support: serial wire debug, JTAG
and trace
Table 1. Device summary
Reference Part number
STM32L151xE STM32L151QE, STM32L151RE,
STM32L151VE, STM32L151ZE
STM32L152xE STM32L152QE, STM32L152RE,
STM32L152VE, STM32L152ZE
LQFP144 (20 × 20 mm)
LQFP100 (14 × 14 mm)
LQFP64 (10 × 10 mm)
UFBGA132
(7 × 7 mm)
WLCSP104

Contents STM32L151xE STM32L152xE
2/134 DocID025433 Rev 8
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2 Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.2 Shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.3 Common system strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 ARM®Cortex®-M3 core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5 Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 23
3.6 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.8 DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.9 LCD (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.11 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.12 Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.13 Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 27
3.14 System configuration controller and routing interface . . . . . . . . . . . . . . . 27
3.15 Touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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3.16 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.16.1 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and
TIM11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.16.2 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.16.3 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.16.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.16.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17.1 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 29
3.17.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.17.4 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.17.5 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.18 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 30
3.19 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.19.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.19.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.7 Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.1.8 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 61
6.3.3 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 63

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6.3.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.3.5 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.3.18 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3.19 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.3.20 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.3.21 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.3.22 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
7.1 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
7.2 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
7.3 LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
7.4 UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid
array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7.5 WLCSP104, 0.4 mm pitch wafer level chip scale package
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
7.6 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
7.6.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

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STM32L151xE STM32L152xE List of tables
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List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Ultra-low-power STM32L151xE and STM32L152xE device features and peripheral
counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 15
Table 4. CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Functionalities depending on the working mode (from Run/active down to
standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 7. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 8. STM32L151xE and STM32L152xE pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 9. Alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 10. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 11. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 12. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 13. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 14. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 15. Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 16. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 17. Current consumption in Run mode, code with data processing running from Flash. . . . . . 65
Table 18. Current consumption in Run mode, code with data processing running from RAM . . . . . . 66
Table 19. Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 20. Current consumption in Low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 21. Current consumption in Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 22. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 23. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 72
Table 24. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 25. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 26. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 27. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 28. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 29. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 30. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 31. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 32. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 33. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 34. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 35. Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 36. Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 85
Table 37. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 38. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 39. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 40. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 41. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 42. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 43. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 44. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 45. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 46. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

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Table 47. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 48. SCL frequency (fPCLK1= 32 MHz, VDD = VDD_I2C = 3.3 V). . . . . . . . . . . . . . . . . . . . . . . . 95
Table 49. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 50. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 51. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 52. USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 53. I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 54. ADC clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 55. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 56. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 57. Maximum source impedance RAIN max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 58. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 59. Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 60. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 61. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 62. Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 63. Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 64. LCD controller characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 65. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 115
Table 66. LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 117
Table 67. LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data. . . . . . . . . . 120
Table 68. UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 69. WLCSP104, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . 127
Table 70. WLCSP104, 0.4 mm pitch recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . 128
Table 71. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 72. STM32L151xE and STM32L152xE Ordering information scheme . . . . . . . . . . . . . . . . . . 131
Table 73. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

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STM32L151xE STM32L152xE List of figures
8
List of figures
Figure 1. Ultra-low-power STM32L151xE and STM32L152xE block diagram. . . . . . . . . . . . . . . . . . 13
Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 3. STM32L15xZE LQFP144 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 4. STM32L15xQE UFBGA132 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 5. STM32L15xVE LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 6. STM32L15xRE LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 7. STM32L15xVEY WLCSP104 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 8. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 9. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 11. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 12. Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 13. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 14. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 15. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 16. HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 17. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 18. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 19. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 20. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 21. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 22. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 23. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 24. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 25. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 26. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 27. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 28. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 29. Maximum dynamic current consumption on VREF+ supply pin during ADC
conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 30. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 31. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 114
Figure 32. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 33. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package top view example . . . . . . 116
Figure 34. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 117
Figure 35. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 36. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package top view example . . . . . . 119
Figure 37. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 120
Figure 38. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 39. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package top view example . . . . . . . . . 122
Figure 40. UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array package outline . . . . 123
Figure 41. UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 42. UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array package
top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

List of figures STM32L151xE STM32L152xE
8/134 DocID025433 Rev 8
Figure 43. WLCSP104, 0.4 mm pitch wafer level chip scale package outline . . . . . . . . . . . . . . . . . . 126
Figure 44. WLCSP104, 0.4 mm pitch wafer level chip scale package recommended footprint. . . . . 127
Figure 45. WLCSP104, 0.4 mm pitch wafer level chip scale package top view example . . . . . . . . . 128
Figure 46. Thermal resistance suffix 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 47. Thermal resistance suffix 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

DocID025433 Rev 8 9/134
STM32L151xE STM32L152xE Introduction
55
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32L151xE and STM32L152xE ultra-low-power ARM®Cortex®-M3 based
microcontroller product line. STM32L151xE and STM32L152xE devices are
microcontrollers with a Flash memory density of 512 Kbytes.
The ultra-low-power STM32L151xE and STM32L152xE family includes devices in 5
different package types: from 64 pins to 144 pins. Depending on the device chosen,
different sets of peripherals are included, the description below gives an overview of the
complete range of peripherals proposed in this family.
These features make the ultra-low-power STM32L151xE and STM32L152xE
microcontroller family suitable for a wide range of applications:
•Medical and handheld equipment
•Application control and user interface
•PC peripherals, gaming, GPS and sport equipment
•Alarm systems, wired and wireless sensors, video intercom
•Utility metering
This STM32L151xE and STM32L152xE datasheet should be read in conjunction with the
STM32L1xxxx reference manual (RM0038). The application note “Getting started with
STM32L1xxxx hardware development” (AN3216) gives a hardware implementation
overview. Both documents are available from the STMicroelectronics website www.st.com.
For information on the ARM®Cortex®-M3 core please refer to the ARM®Cortex®-M3
technical reference manual, available from the www.arm.com website. Figure 1 shows the
general block diagram of the device family.

Description STM32L151xE STM32L152xE
10/134 DocID025433 Rev 8
2 Description
The ultra-low-power STM32L151xE and STM32L152xE devices incorporate the
connectivity power of the universal serial bus (USB) with the high-performance ARM®
Cortex®-M3 32-bit RISC core operating at a frequency of 32 MHz (33.3 DMIPS), a memory
protection unit (MPU), high-speed embedded memories (Flash memory up to 512 Kbytes
and RAM up to 80 Kbytes), and an extensive range of enhanced I/Os and peripherals
connected to two APB buses.
The STM32L151xE and STM32L152xE devices offer two operational amplifiers, one 12-bit
ADC, two DACs, two ultra-low-power comparators, one general-purpose 32-bit timer, six
general-purpose 16-bit timers and two basic timers, which can be used as time bases.
Moreover, the STM32L151xE and STM32L152xE devices contain standard and advanced
communication interfaces: up to two I2Cs, three SPIs, two I2S, three USARTs, two UARTs
and an USB. The STM32L151xE and STM32L152xE devices offer up to 34 capacitive
sensing channels to simply add a touch sensing functionality to any application.
They also include a real-time clock and a set of backup registers that remain powered in
Standby mode.
Finally, the integrated LCD controller (except STM32L151xE devices) has a built-in LCD
voltage generator that allows to drive up to 8 multiplexed LCDs with the contrast
independent of the supply voltage.
The ultra-low-power STM32L151xE and STM32L152xE devices operate from a 1.8 to 3.6 V
power supply (down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power
supply without BOR option. They are available in the -40 to +85 °C and -40 to +105 °C
temperature ranges. A comprehensive set of power-saving modes allows the design of low-
power applications.

DocID025433 Rev 8 11/134
STM32L151xE STM32L152xE Description
55
2.1 Device overview
Table 2. Ultra-low-power STM32L151xE and STM32L152xE device features and peripheral
counts
Peripheral STM32L15xRE STM32L15xVE STM32L15xQE STM32L15xZE
Flash (Kbytes) 512
Data EEPROM (Kbytes) 16
RAM (Kbytes) 80
Timers
32 bit 1
General-purpose 6
Basic 2
Communication
interfaces
SPI 8(3)(1)
I2S2
I2C2
USART 5
USB 1
GPIOs 51 83 109 115
Operational amplifiers 2
12-bit synchronized ADC
Number of channels
1
21
1
25
1
40
1
40
12-bit DAC
Number of channels
2
2
LCD (2)
COM x SEG
1
4x32 or 8x28
1
4x44 or 8x40
Comparators 2
Capacitive sensing channels 23 33 34
Max. CPU frequency 32 MHz
Operating voltage 1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option
1.65 V to 3.6 V without BOR option
Operating temperatures Ambient operating temperature: -40 °C to 85 °C / -40 °C to 105 °C
Junction temperature: –40 to + 110 °C
Packages LQFP64 LQFP100,
WLCSP104 UFBGA132 LQFP144
1. 5 SPIs are USART configured in synchronous mode emulating SPI master.
2. STM32L152xx devices only.

Description STM32L151xE STM32L152xE
12/134 DocID025433 Rev 8
2.2 Ultra-low-power device continuum
The ultra-low-power family offers a large choice of cores and features. From proprietary 8-
bit to up to Cortex-M3, including the Cortex-M0+, the STM32Lx series are the best choice to
answer the user needs, in terms of ultra-low-power features. The STM32 ultra-low-power
series are the best fit, for instance, for gas/water meter, keyboard/mouse or fitness and
healthcare, wearable applications. Several built-in features like LCD drivers, dual-bank
memory, Low-power run mode, op-amp, AES 128-bit, DAC, USB crystal-less and many
others will clearly allow to build very cost-optimized applications by reducing BOM.
Note: STMicroelectronics as a reliable and long-term manufacturer ensures as much as possible
the pin-to-pin compatibility between any STM8Lxxxxx and STM32Lxxxxx devices and
between any of the STM32Lx and STM32Fx series. Thanks to this unprecedented
scalability, the old applications can be upgraded to respond to the latest market features and
efficiency demand.
2.2.1 Performance
All families incorporate highly energy-efficient cores with both Harvard architecture and
pipelined execution: advanced STM8 core for STM8L families and ARM Cortex-M3 core for
STM32L family. In addition specific care for the design architecture has been taken to
optimize the mA/DMIPS and mA/MHz ratios.
This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs.
2.2.2 Shared peripherals
STM8L15xxx, STM32L15xxx and STM32L162xx share identical peripherals which ensure a
very easy migration from one family to another:
•Analog peripherals: ADC, DAC and comparators
•Digital peripherals: RTC and some communication interfaces
2.2.3 Common system strategy.
To offer flexibility and optimize performance, the STM8L15xxx, STM32L15xxx and
STM32L162xx family uses a common architecture:
•Same power supply range from 1.65 V to 3.6 V
•Architecture optimized to reach ultra-low consumption both in low-power modes and
Run mode
•Fast startup strategy from low-power modes
•Flexible system clock
•Ultrasafe reset: same reset strategy including power-on reset, power-down reset,
brownout reset and programmable voltage detector
2.2.4 Features
ST ultra-low-power continuum also lies in feature compatibility:
•More than 15 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm
•Memory density ranging from 2 to 512 Kbytes

DocID025433 Rev 8 13/134
STM32L151xE STM32L152xE Functional overview
55
3 Functional overview
Figure 1. Ultra-low-power STM32L151xE and STM32L152xE block diagram
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Functional overview STM32L151xE STM32L152xE
14/134 DocID025433 Rev 8
3.1 Low-power modes
The ultra-low-power STM32L151xE and STM32L152xE devices support dynamic voltage
scaling to optimize its power consumption in run mode. The voltage from the internal low-
drop regulator that supplies the logic can be adjusted according to the system’s maximum
operating frequency and the external voltage supply.
There are three power consumption ranges:
•Range 1 (VDD range limited to 1.71 V - 3.6 V), with the CPU running at up to 32 MHz
•Range 2 (full VDD range), with a maximum CPU frequency of 16 MHz
•Range 3 (full VDD range), with a maximum CPU frequency limited to 4 MHz (generated
only with the multispeed internal RC oscillator clock source)
Seven low-power modes are provided to achieve the best compromise between low-power
consumption, short startup time and available wakeup sources:
•Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at
16 MHz is about 1 mA with all peripherals off.
•Low-power run mode
This mode is achieved with the multispeed internal (MSI) RC oscillator set to the
minimum clock (131 kHz), execution from SRAM or Flash memory, and internal
regulator in low-power mode to minimize the regulator's operating current. In low-power
run mode, the clock frequency and the number of enabled peripherals are both limited.
•Low-power sleep mode
This mode is achieved by entering Sleep mode with the internal voltage regulator in
Low-power mode to minimize the regulator’s operating current. In Low-power sleep
mode, both the clock frequency and the number of enabled peripherals are limited; a
typical example would be to have a timer running at 32 kHz.
When wakeup is triggered by an event or an interrupt, the system reverts to the run
mode with the regulator on.
•Stop mode with RTC
Stop mode achieves the lowest power consumption while retaining the RAM and
register contents and real time clock. All clocks in the VCORE domain are stopped, the
PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The LSE or LSI is still
running. The voltage regulator is in the low-power mode.
The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Comparator 1 event or Comparator 2 event (if internal reference voltage is on), it can
be the RTC alarm(s), the USB wakeup, the RTC tamper events, the RTC timestamp
event or the RTC wakeup.

DocID025433 Rev 8 15/134
STM32L151xE STM32L152xE Functional overview
55
•Stop mode without RTC
Stop mode achieves the lowest power consumption while retaining the RAM and
register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, LSE and
HSE crystal oscillators are disabled. The voltage regulator is in the low-power mode.
The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Comparator 1 event or Comparator 2 event (if internal reference voltage is on). It can
also be wakened by the USB wakeup.
•Standby mode with RTC
Standby mode is used to achieve the lowest power consumption and real time clock.
The internal voltage regulator is switched off so that the entire VCORE domain is
powered off. The PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched
off. The LSE or LSI is still running. After entering Standby mode, the RAM and register
contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,
RTC, LSI, LSE Crystal 32K osc, RCC_CSR).
The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG
reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),
RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.
•Standby mode without RTC
Standby mode is used to achieve the lowest power consumption. The internal voltage
regulator is switched off so that the entire VCORE domain is powered off. The PLL, MSI
RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off. After
entering Standby mode, the RAM and register contents are lost except for registers in
the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc,
RCC_CSR).
The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising
edge on one of the three WKUP pin occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by
entering Stop or Standby mode.
Table 3. Functionalities depending on the operating power supply range
Functionalities depending on the operating power supply range
Operating power supply
range
DAC and ADC
operation USB Dynamic voltage
scaling range I/O operation
VDD= VDDA = 1.65 to 1.71 V Not functional Not functional Range 2 or
Range 3
Degraded speed
performance
VDD=VDDA= 1.71 to 1.8 V(1) Not functional Not functional Range 1, Range 2
or Range 3
Degraded speed
performance
VDD=VDDA= 1.8 to 2.0 V(1) Conversion time up
to 500 Ksps Not functional
Range 1, Range 2
or
Range 3
Degraded speed
performance

Functional overview STM32L151xE STM32L152xE
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VDD=VDDA = 2.0 to 2.4 V Conversion time up
to 500 Ksps Functional(2) Range 1, Range 2
or Range 3 Full speed operation
VDD=VDDA = 2.4 to 3.6 V Conversion time up
to 1 Msps Functional(2) Range 1, Range 2
or Range 3 Full speed operation
1. CPU frequency changes from initial to final must respect “FCPU initial < 4*FCPU final” to limit VCORE drop due to current
consumption peak when frequency increases. It must also respect 5 µs delay between two changes. For example to switch
from 4.2 MHz to 32 MHz, the user can switch from 4.2 MHz to 16 MHz, wait 5 µs, then switch from 16 MHz to 32 MHz.
2. Should be USB compliant from I/O voltage standpoint, the minimum VDD is 3.0 V.
Table 3. Functionalities depending on the operating power supply range (continued)
Functionalities depending on the operating power supply range
Operating power supply
range
DAC and ADC
operation USB Dynamic voltage scaling range I/O operation
Table 4. CPU frequency range depending on dynamic voltage scaling
CPU frequency range Dynamic voltage scaling range
16 MHz to 32 MHz (1ws)
32 kHz to 16 MHz (0ws) Range 1
8 MHz to 16 MHz (1ws)
32 kHz to 8 MHz (0ws) Range 2
2.1MHz to 4.2 MHz (1ws)
32 kHz to 2.1 MHz (0ws) Range 3

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STM32L151xE STM32L152xE Functional overview
55
Table 5. Functionalities depending on the working mode (from Run/active down to
standby)
Ips Run/Active Sleep
Low-
power
Run
Low-
power
Sleep
Stop Standby
Wakeup
capability
Wakeup
capability
CPU Y -- Y -- -- -- -- --
Flash Y Y Y Y -- -- -- --
RAM Y Y Y Y Y -- -- --
Backup Registers Y Y Y Y Y -- Y --
EEPROM Y Y Y Y Y -- -- --
Brown-out rest
(BOR) YYYYYYY--
DMA Y Y Y Y -- -- -- --
Programmable
Voltage Detector
(PVD)
YYYYYYY--
Power On Reset
(POR) YYYYYYY--
Power Down Rest
(PDR) YYYYY--Y--
High Speed
Internal (HSI) Y Y -- -- -- -- -- --
High Speed
External (HSE) Y Y -- -- -- -- -- --
Low Speed Internal
(LSI) YYYYY--Y--
Low Speed
External (LSE) YYYYY--Y--
Multi-Speed
Internal (MSI) Y Y Y Y -- -- -- --
Inter-Connect
Controller Y Y Y Y -- -- -- --
RTC Y Y Y Y Y Y Y --
RTC Tamper Y Y Y Y Y Y Y Y
Auto WakeUp
(AWU) YYYYYYYY
LCD Y Y Y Y Y -- -- --
USB Y Y -- -- -- Y -- --
USART Y Y Y Y Y (1) -- --
SPI Y Y Y Y -- -- -- --
I2C Y Y Y Y -- (1) -- --

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3.2 ARM®Cortex®-M3 core with MPU
The ARM®Cortex®-M3 processor is the industry leading processor for embedded systems.
It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM®Cortex®-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
ADC Y Y -- -- -- -- -- --
DAC Y Y Y Y Y -- -- --
Tempsensor Y Y Y Y Y -- -- --
OP amp Y Y Y Y Y -- -- --
Comparators Y Y Y Y Y Y -- --
16-bit and 32-bit
Timers Y Y Y Y -- -- -- --
IWDG Y Y Y Y Y Y Y Y
WWDG Y Y Y Y -- -- -- --
Touch sensing Y Y -- -- -- -- -- --
Systic Timer Y Y Y Y -- -- --
GPIOs Y Y Y Y Y Y -- 3 pins
Wakeup time to
Run mode 0 µs 0.4 µs 3 µs 46 µs < 8 µs 58 µs
Consumption
VDD=1.8 to 3.6 V
(Typ)
Down to 195
µA/MHz (from
Flash)
Down to 38
µA/MHz (from
Flash)
Down to
11 µA
Down to
4.6 µA
0.53 µA
(no RTC)
VDD=1.8V
0.285 µA
(no RTC)
VDD=1.8V
1.2 µA
(with RTC)
VDD=1.8V
0.97 µA
(with RTC)
VDD=1.8V
0.56 µA
(no RTC)
VDD=3.0V
0.29 µA
(no RTC)
VDD=3.0V
1.4 µA
(with RTC)
VDD=3.0V
1.11 µA
(with RTC)
VDD=3.0V
1. The startup on communication line wakes the CPU which was made possible by an EXTI, this induces a delay before
entering run mode.
Table 5. Functionalities depending on the working mode (from Run/active down to
standby) (continued)
Ips Run/Active Sleep
Low-
power
Run
Low-
power
Sleep
Stop Standby
Wakeup
capability
Wakeup
capability

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STM32L151xE STM32L152xE Functional overview
55
The memory protection unit (MPU) improves system reliability by defining the memory
attributes (such as read/write access permissions) for different memory regions. It provides
up to eight different regions and an optional predefined background region.
Owing to its embedded ARM core, the STM32L151xE and STM32L152xE devices are
compatible with all ARM tools and software.
Nested vectored interrupt controller (NVIC)
The ultra-low-power STM32L151xE and STM32L152xE devices embed a nested vectored
interrupt controller able to handle up to 56 maskable interrupt channels (not including the 16
interrupt lines of ARM®Cortex®-M3) and 16 priority levels.
•Closely coupled NVIC gives low-latency interrupt processing
•Interrupt entry vector table address passed directly to the core
•Closely coupled NVIC core interface
•Allows early processing of interrupts
•Processing of late arriving, higher-priority interrupts
•Support for tail-chaining
•Processor state automatically saved
•Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.3 Reset and supply management
3.3.1 Power supply schemes
•VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
externally through VDD pins.
•VSSA, VDDA = 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
and PLL (minimum voltage to be applied to VDDA is 1.8 V when the ADC is used). VDDA
and VSSA must be connected to VDD and VSS, respectively.
3.3.2 Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
The device exists in two versions:
•The version with BOR activated at power-on operates between 1.8 V and 3.6 V.
•The other version without BOR operates between 1.65 V and 3.6 V.
After the VDD threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or
not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes
1.65 V (whatever the version, BOR active or not, at power-on).
When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the

Functional overview STM32L151xE STM32L152xE
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power ramp-up should guarantee that 1.65 V is reached on VDD at least 1 ms after it exits
the POR area.
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Stop mode, it is possible to automatically switch off the
internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when
VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external
reset circuit.
Note: The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the start-
up time at power-on can be decreased down to 1 ms typically for deviceswith BOR inactive
at power-up.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when
VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
3.3.3 Voltage regulator
The regulator has three operation modes: main (MR), low-power (LPR) and power down.
•MR is used in Run mode (nominal regulation)
•LPR is used in the Low-power run, Low-power sleep and Stop modes
•Power down is used in Standby mode. The regulator output is high impedance, the
kernel circuitry is powered down, inducing zero consumption but the contents of the
registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,
LSI, LSE crystal 32K osc, RCC_CSR).
3.3.4 Boot modes
At startup, boot pins are used to select one of three boot options:
•Boot from Flash memory
•Boot from System memory
•Boot from embedded RAM
The boot from Flash usually boots at the beginning of the Flash (bank 1). An additional boot
mechanism is available through user option byte, to allow booting from bank 2 when bank 2
contains valid code. This dual boot capability can be used to easily implement a secure field
software update mechanism.
The boot loader is located in System memory. It is used to reprogram the Flash memory by
using USART1, USART2 or USB. See Application note “STM32 microcontroller system
memory boot mode” (AN2606) for details.