Tektronix Tds 520 Operating instructions

1---

WARNING I

The following servicing instructions

are for use by qualified service

personnel only.

avoid personal

injury,

not perform any servicing

unless you are qualified

so.

Refer

the Safety Summary prior

performing any service.

Please

check

for

CHANGE INFORMATION

the

rear

this

manual.

Part No. 070-8313-00

Product Group 55

lHE

TDS520

DIGITIZING

OSCILLOSCOPE

Component Level

Diagnostic and

Repair Manual

Volume 2

COMMITTED

EJCCEL1.ENCE

DIGITALY REMASTERED

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,.---

WARRANTY

Tektronix warrants that this product will be free from defects

materials and workmanship for a period of three

(3)

years

from the date of shipment. If any such product proves defective during this warranty period, Tektronix,

its option, either

will repair the defective product without charge for parts and labor. or will provide a replacement in exchange for the

defective product.

order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration of the

warranty period and make suitable arrangements for the performance of service. Customer shall be responsible for

packaging and shipping the defective product to the service center designated by Tektronix, with shipping charges

prepaid. Tektronix shall pay for the return of the product to Customer if the shipment is to a location within the country

which the Tektronix service center is located. Customer shall be responsible for paying all shipping charges. duties. taxes.

and any other charges for products returned to any other locations.

This warranty shall not apply to any defect, failure or damage caused by improper use or improper

inadequate

maintenance and care. Tektronix shall not be obligated to furnish service under this warranty

repair damage resulting

from attempts

personnel other than Tektronix representatives to install, repair

service the product;

to repair

damage resulting from improper use

connection to incompatible equipment; or c) to service a product that has been

modified

integrated with other products when the effect

such modification or integration increases the time or

difficulty

servicing the product.

THIS WARRANTY

GIVEN

TEKTRONIX WITH RESPECT TO THIS PRODUCT IN LIEU OF ANY OTHER

WARRANTIES, EXPRESS OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES

OF MERCHANTABILITY

FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX' RESPONSIBILITY TO REPAIR

REPLACE DEFECTIVE PRODUCTS IS THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER

FOR BREACH

THIS

WARRANTY. TEKTRONIX AND ITS VENDORS WILL

NOT

LIABLE FOR ANY INDIRECT,

SPECIAL, INCIDENTAL,

CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER TEKTRONIX

THE

VENDOR

HAS

ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.

Instrument Serial Numbers

Each instrument manufactured

Tektronix has a serial number

a panel insert or tag, or stamped on the

chassis. The first letter

the serial number designates the country of manufacture. The last five digits of the

serial number are assigned sequentially and are unique to each instrument. Those manufactured

the United

States have six unique digits. The country of manufacture is identified as follows:

B010000

E200000

J300000

H700000

Tektronix, Inc., Beaverton, Oregon,

USA

Tektronix United Kingdom, Ltd., London

SonyfTektronix, Japan

Tektronix Holland,

NV,

Heerenveen,

The

Netherlands

Instruments manufactured for Tektronix

external vendors outside the United States

are

assigned a two digit

alpha code to identify the country of manufacture (e.g., JP for Japan,

for Hong Kong, IL for Israel, etc.).

Tektronix, Inc.,

P.O.

Box 500, Beaverton,

97077

Printed

U.S.A.

U.S.

and foreign

patents, issued and pending. The following are registered trademarks:

TEKTRONIX,

TEK,

TEKPROBE, SCOPEMOBILE and

Deskjet, HPGL, Laserjet and Thinkjet

are

products of the Hewlett-Packard Company.

Epson is a registered trademark of Epson America, Inc.

Interleaf is a trademark of Interleaf, Inc.

PostScript is a registered trademark of Adobe Systems, Inc.

'-:-,'

.~"'.

Vol.

2 Figure

Semiconductor Lead Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Vol.

2 Figure ii: Locating Components

Circuit Board

Schematic

Diagram.

. . . . . . . . . .

Vol.

2 v

A10 Acquisition

Vol. 2 Figure

9-1:

Attenuator Programming

........................................

Vol.

9-1

Vol. 2 Figure 9-2: A

Attenuator Board Programming Troubleshooting Procedure

........

Vol.

9-1

Vol. 2 Figure 9-3: Acquisition Digital Control Troubleshooting Procedure

................

Vol.

9-2

Vol. 2 Figure 9-4: Acquisition

ProcPs~or

fro.Jbleshooting Procedure

...................

Vol.

9-4

Vol. 2 Figure 9-5: Nonnal

Path

of the Vertical Channels

..............................

Vol.

9-5

Vol. 2 Figure 9-6:

Converter Troubleshooting Procedure

..........................

Vol.

9-5

Vol. 2 Figure 9-7: Analog

DAC

Control Troubleshooting Procedure

....................

Vol.

2 9-6

Vol. 2 Figure 9-8:

6 of U931.

U932. U933.

and U934

.............................

Vol.

9-7

Vol. 2 Figure 9-9:

TP903

(PCO)

..................................................

Vol.

9-7

Vol. 2 Figure 9-10:

TP906

(PC3). .

...............................................

Vol.

9-7

Vol. 2 Figure 9-11:

TP909

......................................................

Vol.

9-7

Vol. 2 Figure 9-12:

TP911

......................................................

Vol.

9-7

Vol. 2 Figure 9-13:

TP904

(PC1)

.................................................

Vol.

9-7

Vol. 2 Figure 9-14:

TP911

......................................................

Vol.

9-8

Vol. 2 Figure 9-15:

TP912

......................................................

Vol.

9-8

Vol. 2 Figure 9-16:

TP904

(PC1)

.................................................

Vol.

9-8

Vol. 2 Figure 9-17:

TP905

(PC2)

.................................................

Vol.

9-8

Vol. 2 Figure 9-18:

U601

pin 3

(PC7)

.............................................

Vol.

9-8

Vol. 2 Figure 9-19: Analog Holdoff

Trou~!~shC'oting

Procedure

........................

Vol.

9-9

Vol. 2 Figure 9-20: Analog Trigger Troubleshooting Procedure

........................

Vol.

9-11

Vol. 2 Figure 9-21:

AUX

1 Front

End

Troubleshooting Procedure .

.....................

Vol.

2 9-12

Vol. 2 Figure

9-22:

AUX

2 Front

End

Troubleshooting Procedure

.......................

Vol.

9-13

Vol. 2 Figure 9-23:

U1800

Pins

2,6,

and

with

kHz 1 Division Input

.............

Vol.

9-14

Vol. 2 Figure 9-24: C and DTrigger Troubleshooting Procedure

.......................

Vol.

9-14

Vol. 2 Figure 9-25:

Front

End

Troubleshooting Procedure

........................

Vol.

2 9-15

Vol.

2 Figure 9-26:

2 Front

End

Troubleshooting Procedure

........................

Vol.

9-16

Vol.

2 Figure 9-27: Clock System Troubleshooting Procedure

.........................

Vol.

2 9-17

Vol.

2 Figure 9-28: Reference Oscillator (U504 pin

...............................

Vol.

9-18

Vol. 2 Figure

9-29:

MHz

Loopback to the

VCO

(U504

13)

.......................

Vol.

9-18

Vol. 2 Figure

9-30:

Delay

Trigger·

Troubleshooting Procedure

.........................

Vol.

9-19

Vol. 2 Figure

9-31:

Demultiplexer Diagnostic Troubleshooting Procedure

...............

Vol.

2 9-20

Vol. 2 Figure

9-32:

Demultiplexer Screen Troubleshooting Procedure

..................

Vol.

9-21

TDS

520

Component

Level

Diagnostic

and

Repair

Manual

Contents

Vol.

2 Figure 9-33: Extended Trigger Troubleshooting Procedure

......................

Vol.

9-22

Vol.

2 Figure 9-34: Glitch Triggering

..............................................

Vol.

9-23

Vol.

2 Figure 9-35: Logic Trigger Troubleshooting Procedure

.........................

Vol.

9~24

Vol.

2 Figure 9-36: Time Interpolator Ramps

.......................................

Vol.

9-25

Vol.

2 Figure 9-37: Time Interpolator Troubleshooting Procedure

......................

Vol.

9-25

Vol.

2 Figure 9-38: Trigger Logic Failure Areas

.....................................

Vol.

9-26

Vol.

2 Figure 9-39: Trigger Logic Troubleshooting Procedure

.........................

. Vol. 2

9-26

Vol. 2 Figure 9-40: Probe Connection Troubleshooting Procedure

.....................

Vol.

9-27

Vol.

2 Figure 9-41: A

Acquisition Board (Section

Front)

..........................

. Vol. 2 9-28

Vol. 2 Figure 9-42:

A10

Acquisition Board (Section

Front)

..........................

. Vol. 2

9-29

Vol. 2

figure

9-43: A10 Acquisition Board (Section

Front)

..........................

. Vol. 2 9-30

Vol. 2 Figure 9-44: A10 Acquisition Board (Section

Front)

..........................

. Vol. 2

9-31

Vol.

2 Figure 9-45: A10 Acquisition Board (Section

Back)

..........................

. Vol. 2 9-32

Vol. 2 Figure 9-46: A10 Acquisition Board (Section

Back)

..........................

. Vol. 2

9-33

Vol. 2 Figure 9-47: A10 Acquisition Board (Section

Back)

..........................

. Vol. 2 9-34

Vol. 2 Figure 9-48: A10 Acquisition Board (Section

Back)

..........................

. Vol. 2 9-35

10 Acquisition Component Locator

...............................................

Vol.

2 9-36

Vol.

2 Figure 9-49: A

Acquisition Waveforms

....................................

Vol.

2 9-40

DRAM Processor/Display

Vol.

2 Figure 9-50: Bdsack Troubleshooting Procedure

.......................

. . . . . .

Vol. 2 9-42

Vol. 2 Figure 9-51: BootROM Control Troubleshooting Procedure

.......................

Vol. 2

9-43

Vol. 2 Figure 9-52: Bus Control Register Troubleshooting Procedure

....................

Vol. 2 9-44

Vol. 2 Figure

9-5.3:

Byte Enable Decoder Troubleshooting Procedure. . . . . . . . . . . . . . . . . .

Vol.

2 9-45

Vol. 2 Figure 9-54:

CPU

Troubleshooting Procedure

.................................

Vol.

2 9-46

Vol.

2 Figure 9-55: Bus

Error

Circuitry Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Vol. 2

9-47

Vol.

2 Figure 9-56:

CPU

Bus Error Troubleshooting Procedure

.........................

Vol. 2

9-47

Vol.

2 Figure 9-57:

CPU

DIP

Switch Troubleshooting Procedure

........................

Vol.

9-48

Vol.

2 Figure 9-58: U1069 Signals When the

CPU

Forcefully Accesses the

DSP

(U1097) Bus

Vol.

9-49

Vol. 2 Figure 9-59:

CPU

Forced Bus From

DSP

Troubleshooting Procedure

..............

Vol.

9-49

Vol.

2 Figure 9-60: U1069 Signals During

Implicit

DSP

(U1097)

Bus

Access

the

CPU

Vol.

9-50

Vol.

2 Figure 9-61:

CPU

Implicit Bus From

DSP

Troubleshooting Procedure

..............

Vol.

2 9-50

Vol.

2 Figure 9-62:

CPU

Interrupt Troubleshooting Procedure

..........................

Vol. 2

9-51

Vol.

2 Figure 9-63:

CPU

LED

Troubleshooting Procedure

.............................

Vol.

2 9-52

Vol.

2 Figure 9-64: U1069 Signals When

tRe

CPU

Requests Access to the

DSP

(U1097)

Bus

Vol.

9-53

Vol.

2 Figure 9-65:

CPU

Request Bus From

DSP

Troubleshooting Procedure

.............

Vol.

9-53

"--"

Vol.

2 Figure 9-66:

Memory Troubleshooting Procedure

............................

Vol.

9-54

Vol.

2 Figure

9-67:

Display Reset Register Troubleshooting Procedure . . . . . . . . . . . . . . . .

Vol.

9-55

Vol.

2 Figure

9-68:

Dsack Troubleshooting Procedure . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .

Vol.

9-56

Vol.

2 Figure

9-69:

DSP

Troubleshooting Procedure. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . .

Vol.

9-57

Vol.

2 Figure

9-70:

DSP

Dsack Troubleshooting Procedure

...........................

Vol.

9-58

Vol.

2 Figure

9-71:

DSP

Instruction Memory Troubleshooting Procedure

.................

Vol.

9-59

Vol.

2 Figure

9-72:

DSP

Interrupt Troubleshooting Procedure

..........................

Vol.

9-60

Vol.

2 Figure

9-73:

DSP

Memory Access Troubleshooting Procedure

....................

Vol.

9-61

Vol.

2 Figure

9-74:

DRAM

Control Troubleshooting Procedure

.........................

Vol.

9-62

Vol.

2 Figure

9-75:

Reset

Ul110 at Power

....................................

Vol.

9-63

Vol.

2 Figure

9-76:

Ull10

Bus

Interface signals

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Vol.

9-63

Vol.

2 Figure

9-77:

UlllO

Output Control Signals

...................................

Vol.

9-63

Vol.

2 Figure

9-78:

Typical

DRAM

Dsack Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Vol.

9-64

Vol.

2 Figure

9-79:

DRAM

Dsack Signals During Refresh

.............................

Vol.

9-64

Vol.

2 Figure

9-80:

DRAM

Dsack Troubleshooting Procedure

..........................

Vol.

9-64

Vol.

2 Figure

9-81:

DUART

Troubleshooting Procedure

...............................

Vol.

9-65

Vol.

2 Figure

9-82:

FIFO

Troubleshooting Procedure

.................................

Vol.

9-66

Vol.

2 Figure

9-83:

GPIB

Troubleshooting Procedure

...

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Vol.

2 9-67

Vol. 2 Figure

9-84:

............................

Vol.

9-68

Vol. 2 Figure

9-85:

Kernel

Troubleshooting Procedure

.. . . . . . . . . . . . . . . . . . . . . . . . . . .

Vol.

9-69

Vol.

2 Figure

9-86:

Kernel

Control Signals

..........................................

Vol.

2 9-70

Vol.

2 Figure

9-87:

Reset

.......................................................

Vol.

9-70

Vol.

2 Figure

9-88:

Kernel

Dsack Signals

..........................................

Vol.

9-71

Vol.

2 Figure

9-89:

Kernel

Dsack Troubleshooting Procedure

........................

Vol.

9-71

Vol.

2 Figure

9-90:

Kernel

RAM

Troubleshooting Procedure

.....

".....................

Vol.

2 9-72

Vol.

2 Figure

9-91:

Ul107

(NVRAM)

Control Signals

.................................

Vol.

9-73

Vol.

2 Figure

9-92:

NVRAM

Troubleshooting Procedure

...............................

Vol.

9-73

Vol.

2 Figure

9-93:

On/Standby Troubleshooting Procedure

........................

Vol.

2 9-74

Vol.

2 Figure

9-94:

Pixel Processor Register Troubleshooting Procedure

..........

". . . .

Vol.

2 9-75

Vol.

2 Figure

9-95:

RamDac Troubleshooting Procedure

..............................

Vol.

2 9-76

Vol.

2 Figure

9-96:

Random Dot Mode Troubleshooting Procedure

Vol.

9-77

Vol.

2 Figure

9-97:

Rasterizer Troubleshooting Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . .

Vol.

9-78

Vol.

2 Figure

9-98:

Rasterizer Mode Troubleshooting Procedure

.....................

Vol.

9-79

Vol.

2 Figure

9-99:

Reset and

VCC

........................

...........

..........

Vol.

9-80

Vol.

2 Figure

9-100:

Reset Troubleshooting Procedure

...........................

...

Vol.

9-80

Vol.

2 Figure

9-101:

Text

Memory Troubleshooting Procedure . . . . . . . . . . . . . . . . . . . . . . . .

Vol.

9-81

Vol.

2 Figure

9-102:

Timer Interrupt Troubleshooting Procedure

........................

Vol.

9-82

Vol.

2 Figure

9-103:

Vector List Memory Troubleshooting Procedure

....................

Vol.

9-83

Vol.

2 Figure

9-104:

Video Troubleshooting Procedure

...............................

Vol.

9-84

Vol.

2 Figure

9-105:

Video

Out

Signal

.............................................

Vol.

9-85

Vol.

2 Figure

9-106:

VSC

.........................

Vol.

9-86

Vol.

2 Figure

9-107:

Waveform Memory Troubleshooting Procedure . . . . . . . . . . . . . . . . . . .

Vol.

9-87

Vol.

2 Figure

9-108:

Mode Troubleshooting Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . .

Vol.

9-88

Vol.

2 Figure

9-109:

All

DRAM

Processor/Display

Boar~

(Section

...................

Vol.

9-89

TDS

520

Component

Level

Diagnostic

and Repair

Manual

------~~~~~~

--~-

-~-~~-

Vol.

2 Figure 9-110: A

DRAM

Processor/Display Board (Section

..................

Vol.

2 9-90

Vol.

2 Figure 9-111: A

DRAM

Processor/Display Board (Section

..................

Vol.

9-91

Vol.

2 Figure 9-112: A

DRAM

Processor/Display Board (Section

..................

Vol.

9-92

DRAM

Processor/Display Component Locator

...................................

Vol.

9-93

Vol.

2 Figure 9-113: A

DRAM

Processor/Display Waveforms

........................

Vol.

9-96

Front Panel

Vol.

2 Figure 9-114: A12

Front

Panel System Troubleshooting Procedure

...............

Vol.

2 9-97

Vol.

2 Figure 9-115:

PC1

and PC2 Timing

.........................................

Vol.

2 9-98

Vol.

2 Figure 9-116: PC5 Timing

.................................................

Vol.

9-98

Vol.

2 Figure 9-117:

PCO

Timing

.................................................

Vol.

2 9-98

Vol.

2 Figure 9-118:

PCO

Timing

.................................................

Vol.

2 9-98

Vol. 2 Figure 9-119: Row

1-8

Timing

.............................................

. Vol. 2 9-98

Vol.

2 Figure 9-120: Row

1-8

Timing

.............................................

Vol.

2 9-98

Vol. 2 Figure 9-121: Bell Troubleshooting Procedure,

................................

Vol.

2 9-99

Vol.

2 Figure 9-122: Front Panel

LED

Troubleshooting Procedure

......................

Vol.

2 9-100

Vol.

2 Figure 9-123: Front Panel

LED

Test Loop Waveforms

..........................

Vol.

9-101

Vol.

2 Figure 9-124: Front Panel

LED

Test

Loop Troubleshooting Procedure

.............

Vol.

9-101

Vol.

2 Figure 9-125: Front Panel Mux Test Loop Waveforms

..........................

Vol.

2 9-102

Vol.

2 Figure 9-126: Front Panel Mux

Test

Loop Troubleshooting Procedure

.............

Vol.

2 9-102

Vol.

2 Figure 9-127: Front Panel Processor Troubleshooting Procedure

.................

Vol.

2 9-103

Vol. 2 Figure 9-128: PC2

(TP20)

Timing Signal During the Front Panel Self Diagnostic

Loop.

Vol.

2 9-104

Vol.2

Figure 9-129: Front Panel Self Diagnostic Loop Troubleshooting Procedure

........

Vol.

2 9-104

Vol.2

Figure 9-130: Front Panel Switch

Test

Loop Waveforms

........................

Vol.

2 9-105

Vol.

2 Figure 9-131: Front Panel Switch Test Loop Troubleshooting Procedure

...........

Vol.

2 9-105

Vol. 2 Figure 9-132: Probe Compensator Troubleshooting Procedure

...................

. Vol. 2 9-106

Vol. 2 Figure 9-133: A12

Front

Panel Board (Front)

..................................

Vol.

2 9-107

Vol.

2 Figure 9-134: A12

Front

Panel Board (Back)

..................................

Vol.

2 9-108

A12 Front Panel Component Locator

..............................................

Vol.

2 9-109

Vol. 2 Figure 9-135: A12

Front

Panel Waveforms

...................................

Vol.

2 9-110

Firmface

Vol. 2 Figure 9-136: Firmface Troubleshooting Procedure

...................

. . . . . . . .

Vol.

9-111

Vol. 2 Figure 9-137: A

Firmface Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Vol.

2 9-112

Firmface Component Locator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Vol.

2 9-113

Vol.2

A14

Bus

Vol.

2 Figure 9-138: A

Bus Board . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .

Vol.

2 9-114

Bus Component Locator

...................................................

Vol.

9-115

A15 Attenuator

Vol. 2 Figure 9-139: Attenuator Troubleshooting Procedure. . . . . . .. . . . . . . . . . . . . . . . . . .

Vol.

2 9-116

Vol. 2 Figure 9-140: Attenuator Hybrid

.............................................

Vol.

2 9-117

Vol. 2 Figure 9-141: A15 Attenuator Board

.........................................

Vol.

9-118

A15 Attenuator Component Locator

................................................

Vol. 2

9-119

A16 (A17, A18, A19) Low Voltage Power

Supply

Vol. 2 Figure 9-142: A16 Low Voltage Power Supply Module Isolation Troubleshooting

Procedure

...........................................................

. Vol. 2 9-120

Vol. 2 Figure 9-143: Boost Control Troubleshooting Procedure

........................

. Vol. 2

9-121

Vol. 2 Figure 9-144:

and Q6 Gate Drive Wavefonns

..............................

. Vol. 2 9-122

Vol. 2 Figure 9-145:

FEr

DRIVE

Wavefonn

........................................

Vol.

2 9-122

Vol. 2 Figure 9-146: LowVoltage Power Supply Troubleshooting Procedure

.............

. Vol. 2 9-123

Vol. 2

Vol. 2 Figure 9-147: Main Converter Control Troubleshooting Procedure

................

Figure 9-148: Q7 and Q8

GATE

DRIVE

......................................

Vol.

2 9-124

Vol. 2 9-125

Vol. 2 Figure 9-149:

GATE

DRIVE

................................................

. Vol. 2 9-125

Vol. 2 Figure 9-150:

Pin 7

...................................................

Vol.

2 9-125

Vol. 2 Figure 9-151: Q5 and

Gate Drive

........................................

. Vol. 2 9-126

Vol. 2 Figure 9-152: Power Supply Primary Troubleshooting Procedure

.................

Vol.

2 9-126

Vol. 2 Figure 9-153: Q7 and

Gate Drive

........................................

. Vol. 2 9-127

Vol.

2 Figure 9-154: Power Supply Secondary Troubleshooting Procedure

..............

Vol.

2 9-127

Vol.

2 Figure 9-155: A17 Main

Power Supply Board (Section

.....................

. Vol. 2 9-128

lDS

520

Component

Level

Diagnostic

and Repair

Manual

Vol.

2 Figure 9-156: A

Main

Power Supply Board (Section

.....................

. Vol. 2 9-129

Vol.

2 Figure 9-157:

A17

Main

Power Supply Board (Section

....................

. Vol. 2 9-130

Vol.

2 Figure 9-158: A

Main

Power Supply Board (Section

....................

. Vol. 2

9-131

Main

Power Supply Component Locator

.....................................

. Vol. 2 9-132

Vol.

2 Figure 9-159:

A17

Main

Power Supply Waveforms

..........................

. Vol. 2 9-133

Vol.

2 Figure 9-160: A

Main Converter Control Board

..............................

. Vol. 2 9-136

Main Converter Control Component Locator

.....................................

. Vol. 2 9-137

Vol.

2 Figure 9-161: A

Main Converter Control Waveforms

.........................

. Vol. 2 9-138

Vol.

2 Figure 9-162: A

Power Factor Control Board

...............................

. Vol. 2 9-139

Power Factor Control Component Locator

......................................

. Vol. 2 9-140

A20 CRT Driver

Vol.

2 Figure 9-163: Display Distortion Troubleshooting Procedure

.....................

. Vol. 2

9-141

Vol.

2 Figure 9-164: Display Driver Troubleshooting Procedure

........................

. Vol. 2 9-142

Vol. 2 Figure 9-165: Video, Sync, and Scan Troubleshooting Procedure

................

. Vol. 2 9-143

Vol.

2 Figure 9-166:

A20

eRT Driver Board

........................................

. Vol. 2 9-144

A2.0

CRT

Driver Component Locator

...............................................

. Vol. 2 9-145

Vol. 2 Figure 9-167:

A2.0

eRT Driver Waveforms

....................................

. Vol. 2 9-146

A21

VCO Board

Vol. 2 Figure 9-168:

A2.1

veo

Board Vol. 2 9-149

A2.1

veo

Board Component Locator

...............................................

Vol. 2 9-150

Schematics and Block Diagrams

Vol.2

Iii

A10

•

Change

the vertical

SCALE

any channel

from

50 mV to 100

from 500

to 1V.

Cao

you

hea

the

attenuater relays

click?

Change tile

Vertical

ALE

from 200

SOOmV.

can

Connect a

probe

to - ATTNSTRB (TP638)

and connect another probe to

CCATTN

(TP637j. Trigger

the

-ATTNSTRB

signa

Change

the Vertical

SCALE

of any

channe

Irom

50 mV

100 mV or

Irom

500 mV to 1 V

you

..-;0

....

the

attenuatar relays

click?

y",

Change

the

Vertical

upling of the

selected channel.

Can

you

hear

the

attenuator relays

....

----

-----'

click?

y.,

there

still a

probl

fil

with the

attenuato(?

y",

Perform the Attenuator

troubleshooti

procedure

No There

not a

prOblem

with

the

A15

AttenuatOf

Board

Programming

TDS 520

Component

Level Diagnostic and Repair Manual

the

signals

look

ike

those

shown

Figure

9--1?

Scans

Artekmedia

011

No Check

and

repair U624.

US29,

and

associated

circuitry.

Connect

probe

(TP636),

and

connect another

probe

CCATTN

(TP637). Trigger on the

CCATTI~

signal. Change the

Vertical

SCALE

setting

any channel

from

50 mV to

100

from

500

rnVto 1V.

Is the

data

correct?

!See

Figure 9-1 and

Table

3-1.)

There

not aproblem

with

1he

A15 Attenuater

Board

Programming

Check

and repair

the

attenualor

and

associated

rcuitry

-ATTNSTRB J L

CCATTN

nruuuu

Vol. 2 Fi

gure

9·1:

Atte

nuator

Programming

Vol. 2 Figure

9·2:

Attenuator

Board

ogrammi

Troubleshoot

ing

Procedure

Al0

Acquisition

Vol. 2 9·1

•

Uoo this

prooodure

you

SUSpect

aproblem with

programming the A1a

Acquisition board.

there

a problem

with

programm

ing the

A15 Attenuator board?

{You

Yes

can"t change the vertical scale.

>--~

the

vertical scale is

not

correct

the

channel

coupling

not

correct.)

then>

problem

with

Perform the A15 Attenualor

Board Programming

troubleshooting procedure.

there

a problem

with

programming one ofthe

preamps?

(You

can not

change

the

vertical scale.

the

vertical

scale

not

correct.

the

IXQb

lem

with

Programming

the

trigger source or holdoff'?

(You

>N_

_________

can

not

change

the trigger

p-<>gramming

the

triggercou

ing

mode?

:;..:::....-.

(The

triggermode

channel coupling

not

correct

y",

Connect a

probe

eitner

eel

(TP639) for

CC23

(TP64O)

CC3C

(TP65O)

for

CC4D

(TP6511

lot

CH 4.

Connect another

probe

(TP636).

Tngger

al1he

CC1A-CC40

signal. Change the

Vertical

SCALE

Coupling

SOlXce,

or the

trigger

hoIdoff

too long.)

the

SROA-Sf\2A

SROB-SR2B

and

HOLDOFF1--4 signals

co~

(see

Tables

9-1

and

9-2)?

Check

and

repair

Ul551, U1552,

and

associated circuitry.

the

data

correct?

(See

tables 3-2

and

3-3.) >

c.N::

Check

and

epair

U602,

U624. U625.

and

associated circuitry.

There

no problem

with programming

the

preamp

520

Compon

ent

evel

Diagnostic

and

epa

Manual

Check

and

repair U621.

U622.

and

associated

circuitry.

a coupling

not

oonectl

Vos

Connect a

probe

either

TR1GCCA

(TP631)

orTRIGCCB

(TP632) of

the

desired trigger I

Cor1nec1

another

probe

CO (TP636). Triggar

the

TAIGCCA-8 signal.

Change the trigger Source

or Coupling.

the bit

pattern

COlTect

(see

Table

9-3)?

Check and repair

U602, U624.

and

associat8d

circuitry

PeOOrm

the Analog DAC

""""'"

pwcedure.

" there

sUIi

a problem with

the trigger

mode

coupling

programming?

jeans

AileAMed,a

20;

There is not a problem

with programming ttle

Ala

Acquisition bOard.

Cheek

and

repair

Ul551 ,

SS2.

and

the

IlfOSOCiatcd

oirCtJitry

Vol. 2 Figure 9·3: Acquisition Digital

Control

Troubleshooting Procedure

Acquisition

Vol

9·2

Scans

Art

ekmedia

Vol. 2 Table 9-

SROA-$R2A and SROB-SR2B Signals

• Selected

input

SR2A/B SR1A/B

SROA

CH5

CH1 0

CH2

CH1

and CH2 0 0

CH5 0

CH3

0 0

4 0 0

and CH2 0 0 0

Vol

. 2

Table

9·2:

HOLDOFFl-4

Signals

HOLDOFF4 HOLDOFF3 HOLDOFF2 HOLDOFFI

Repair o o o o

Don't

Care

All

her

Comb

ons

• Vol. 2 Table

9-3

: Trigger

Signal

nigger

Mode

7 6 5 4 3 2 1

DC 0 0 0 0 o o o

Reject 0 0 0 0 o 0

Reject 0 0 0 o o o

Reject 0 0 0 o 0

HF Reject 0 0 0 o o o

AC HF Reject 0 0 0 o 0

Direct Noise Reject 0 0 o o o

Noi

Reject (20 Hz High Pass) 0 0 o 0

This

bit

will

a 1

negative slope is selected.

• Vol

Figure 9-3: Acquisition Digital Control Troubleshooting Procedure (Cont.)

TDS 520

Component

Level Di

agnost

end Repair Manual A

Acquisition

•

Use this procedure

check

the Acquisition

Processor.

Run

the

aCQProcThermistor

diagnostic.

Check

and

repair

. RT617,

5 of

USOO

and

associated

circuitry.

Check

and

repair

hi'

DUART

(U1317 on the

All

DRAM

JDiSp£ay

board), A14 01

Bus

board ooonections.

and

USOO

The

Acquisition

stY

Is ok.

IDS

520

Component

Level Diagn

ostic

and Repair Manual

U600

pin 8 at

+5V

and

U600

pin 7 at

g",""",

Ched<

and

repair the

associated circuitry.

Check and repair

R60

1-R608.

CROO

1-CR604,

and

Cl50-C

l53

. Check the

COM9Ctions

to the A

Attenuator.

_U600

Scans

td,ilJeoia

I r

Vol.:1 Figure 9-4: Acquisition Processor Troubleshooting Procedure

A10 Acquisition

Vol.

2 9-4

•

Use this

procedure

troubleshoot

AID

converter

problem

(U700

and

U750)

NOle:

Depending on the setup of

the

oscilloscope, the AiD

converter

can

get

Its

input

signal from

any

the

preamps

Select

the

vertical channel that is defective. Connect a

5.0

MHz

500

peak-to-peak

sine

wave

the

selected

vertical input.

Press

VERTICAL MENU. COUPLING, and

. Set Offset to 0

Sellhe

vertical SCALE to

mV, and

the horizontal SCALE to 200

the

input signal from

the

preamp

reachir,g

the selected

/vi)

converter

(pins 4

and

6, pin 12.

pins

and

11).

and

500

Per10rm the appropriate

tronl~

troubleshooting

procedure.

---

differential

signal?

Yeo

Using the vertical

POSITION

control,

center

the differential

signal around

0.0

Are

the

signals

pin 1

and

pin 2 selecting the

input signal (see

Table

9-4)?

pins

and

the

AID

convener

MHz

-Eel

clocks?

Check

and

repair

the

appropriate

preamp

control circuity.

and

verify

the

oscilloscope

setup

pins 23. 24, 82.

and

the

AID

converter 250 MHz

-ECL

clocks?

Replace the

converter.

Perfoon

the

Clock

System

troubleshooting

procedure

TOS 520

Component

Level

Diagnostic

and

Repair

Manual

Scans

Artekmedia

2011

,,,

all A and B

data

outputs

the selected

AID

converter

toggling.

and are

they toggling on the rising

edge aftha signal

71?

I, the

voltage

-0

V to

-l.OV

and

the voltage

pin 35

+0.9Vto

+1.0V?

r::-------,-,-----,-----,

The

problem

not

tre

AID

converter

Perform

the Analog CAe

Control troubleshooting

pr'Y'..t:rdure.

CH'

CH2

CH'

Vol.

Table

9-4:

AID

Converter

Input

~elec

tion

Input

CH2

CAL

Not

Allowed

1 Atlenuatof

Preamp 1

Atlenuator

Preamp 2

3 Atlenuatof

Preamp 3

Attenuator

Preamp 4

CALSEL

(Pin

Low

High

NO Converter A

AID

Converter

AID

Converter C

Ala Converter D

CH2SEL (Pin

Low

High

Don't

Care

High

Demultiplexer

Vol.

Figur

9-5:

Normal

Path

the

Vertical

Channels

Display

2 Display

3 Display

4 Display

Vol.

Figure

9-6:

AID

Converter

Troubleshooting

Procedure

AlO

Acquisit

ion

Vo/.2

9-5

•

This procedure

assumes

D/A

Converter system voltage problem.

the bad

DAC

voltage

LATHRESHOLDI through

LATHRESHOLO<I.

VA'UO.

ETL

FAST.

ETl2FAST.

ATTNCAL?

Locate the

bad

DAC

vottage

at1he output of

U931

-U934.

Does

the

voltage al

TP91

the

OAC

chan9l'

about every 60

J.ls

UId

vary

over the

.:!:

1.71 V

range

(see

Figure 9-14)?

000.

...

voltage

TP912

lJ903

change about

every

jJ.s

and

vary

overthe

I .71 V range

(see

FlQure

9-15)?

Does

the

voltage

pin 3 of

US03

change about every

J.ls

and

stay

thin

the:!:

1.71

range?

Check and Repair u003.

Change

the-

D/A

converter

voltage

value

from

0 to 4095

(+10.24

-10.24

using

the DAC

diagllOSlics.

Change

the

O/A

converter

voltage

value

from 0 to 4095

(+1.71

Vto

-1

using

theDAC

diagnostics.

y",

Check

and

repair

the

connection

betweeo

U903

pin 1

ond

the

""'09

multiplexer.

Do.,

the

voltage

vary

over

the f

ull

range

the

output of

interest

U907

U908

(see

Figure

"""

the

voltage-

vary

over

the

full

range at the

output

U931

U9345.

U940,

U941?

pins 9,

10,

and

of the IC

HCMOS

logic

levels

and

changing

aboIi

every 10

J.ls

(see

F"J9Ures

9-9,

9-16, and 9-1

7)?

Check

and

repair U600

and

associated

components.

TDS

520

nent l

eve

l Diag

and

epai

ual

y.,

Do..

the

voltage

U900 pin 9

chance about every

}.ls

and

stay

with

the

±10.24 V

range?

Ye,

Check and repair U905,

U907,

and

U908.

the

voltage

range?

Yes

Check

and

repair

lJ9OO.

R9OO.

ROOt

R902

. and C900.

Trace

the

signal through

its

voltage buffers

and

associated oompooents. " necessary change

the

OIA

converter

vortage

value from 0

4095

-1.71

using

the

OAC Diagnostics.

Measured voltages should agree

with

the

voltages

the

schema1ic.

pin 6

HCMOS

Vto

pulse

every 100

J.ls

pulses)

followed

a 6 ms pause

(see Figure 9-8)1

Check

and

repair

the

analog

ulti~exe

(U931-U934)

and

associated components.

TP9Q6,

TP907,

and

TP908

001<

FlQure

9-IO?

Check

and

ropair

U600

and associated

components.

Scans

ArlekMeala

201

the

voltage

in range

bl.J\

not

changing?

Check and

repai

U900

and

its

control signals.

Check

and

repair

U901

and

associated

components.

the

data

and

address lines of

U900

HCMOS logic

levels

changing

aooUl

every

J.ls

(10

J.ls

100

J.ls)?

U601 pin 2 a pulse

about

every

100 Jls?

Check

and

repai

r U600

and associated

components.

Check and

repair U9Xl.

Check

and

repair power

supplies to

U900

Check

ond

repairU601

",d

associated

componerrts.

Figure 9·7: Analog DAC Con

tro

l T

ublesh

oot

Procedure

Al 0Ac qu

isitio

l.2

9·6

•

Slopped: 506 Acquisi

tions

---T---

..;-

- - I

•

t.-

•

_1-1--

'--

1--

'. .

en1

""Iuu

ulll...nIJ

$l)l>mv

Vol. 2 Figure 9-8: Pin 6

U931, U932, U933, and

U934. This burst

eight 68 J.l-s-strobes

occurs

once

every

3.7

Stopped

: S2 Acquisitions

['-+

! I- I

[).

3io~s

<l4J.1S

- - I t

I !

.. ..

;,.,

I t

T -

_.L

1 +

r t

.,.......

· j

T -

L..

Y:--

L-..

I ,

j f

f -

224

"mV

06v

T M

eli

l j -

T ; ,

; _i

Vol. 2 Figure 9-9: TP903 (peO)

TDS 520

Component

Level

Diagnostic

and

Repair

.6.

10.00kH

030kH

~S.5

til

the

next bUrst.

Scans

Artekmedia =>

2011

Stopped

: 15

Acq

uisitions

.,----,

. I

-I

- - 1

_ _ J

- - -- I

. .

enl 2.

V-

[..-

.:r

+--

----

-i----

-<1

t+-tHL

.~+

+--+>+;

"";''';''

_H_

i ·

- -

,.-

,<uu

jJ ...11 1 J

84m

Vol. 2 Figure 9-10: TP906 (pe3)_

TP907 (PC4) and TP9

(peS)

are similar.

Stopped:

Acquisition

.:r

--+-

..+ .

'---!.

--T

--l

,..,.,

-__I

'-,----

. '

.60

: 370

J.l

@: 444J.lS

"1""

M100.0

j.J.

· '

Cti

i J

. ,

Vol. 2 Figure 9-11: TP909. Sometimes t

frequen

signal

varies or there are

pulses

missi

several cycles.

.6.:

740J.1s

SSS}!S

•

Stopped: 235 Ac

qui

tion

Stopped'

r i

• -

-.-.--i-

[

---

---------T

----

--------

)

Vol

Figure 9-12: TP911

qui

ition

[

.:r

--+

- - I

)

- -a :

3'1

444

C"'"

- - - - -

'------c

L-.

lil

V -M "O

O.O

jl· Ch1 J

22"4

; .T -; ;

Vol.2

Figure

9-13:

TP904

(PC1)

Vol. 2 Figure 9-7: Analog CAG

Control

Troublesh

ooting

Procedure (Cont.)

Al0

Acquisl1ion

Vo/.2

9-7

•

StoppeQ:

235

Acqu

isitio

5.00 V

1---

--------

Vol.2

gur

e 9-14: TP911

Stopped:

336

Acquisitions

1.00 V

I T

Vol. 2 Figure 9-15: TP912

S 520

Component

Level Diagnostic

and

epair

Manual

stopp

ed: Sl

t:fll . '

2.00

.1:

quisit

-·

--T

-+-

--f----

----

I·,t

:'·

6 :

HOps

44oClJ,lS

'1"

10:0

.0j..t

: 'Ch1 J " '2:

Vol. 2 Figure 9-16: TP904

C1)

Stopped:

Acquisitions

2.00V .

---"

.:t.

iioi-as'

til: "44).15

.. :

...

:. r

,-+

_~-,-------:-J

..1

...

. O\l106.o}j' Ch l :

.I"

224mV

Vol. 2 Figure 9-17: TP905 (PC2)

Scans by ArtekMedla

2011

Stopped

: 747 I

Acquisitions

, ,

---

+.f-H-t++-~

[ I I

til

' . .

___

' ,

_<l1fI<

! ..

..........

. 2

:0C

: 1

. M .

sOOji

Ch1

. . .

.T"

;

Rgu

,.9-18:

U601 pin 3 (

PC7

)

t"'

Vol. 2 Figure 9·7: Analog DAC Control Troubleshooting

Proced

(Cont.)

A10

Acqu

isition Vo/.2 9-8

•

This procedure is tor

troubleshooting

the

Analog

Trigger

Hoidoff

citcUi1Iy.

Yes

U1S01B pin 9

high

UI501S

pin 9

(MTHO)

low'?

Oleck

and

repair Uloo1

(MAT).

Ul501

and related circuitry.

"""'

MTHO toggle

the v/liiable

hoIooft

increased?

y.,

Check

and repair UI503.

Al539

540,

AI54

and

associated

circuitsy.

Scans

Artekmedia""

2011

Check and repair path

tom

U620

III

the

t.oldofl

ramp low?

Yes

pin 9

HOSEr

low) throogh U1S01A

>-'-'----1

-1

and

U1S01

B to MTHO. Check

and

repair 01543, 01531. AI542.

RI548

and

associated

circuitry

Check

and

repair path from

U620

pin 9 C HOSET high)

through

Ul501A

and

UI 50

to MTH

Chec

and

repair

01543,01531

, RI

54S,

502,

and

associated circui1ly.

Iu.

both

the

slow

range

10 ms) and the

fast range « 10

ms)

(MTHO toggles in

the

Check

and

repair

the

HOLDOFF4 signal

(U633 pin 12). 0 1526,

and related clrcUtry.

I5018

pin 9 No

(MTHO)

for all

~C-

___

____

-I

variable hoIdoff

programmed time

range)?

y",

•

MTHO No

(U15Q1

ping)

>--

toggling?

Yes

O>ockand_

all

timi~ranges

-+t

HOLDOFF1-HOLDOFF3.

worK?

CR1525-CR1531,

and

Yos

Changing the variable hoIdofI

DAC VOltage through its

lull

range should change MTHO

the

amount

shown

Table

9-5

related clrcui1ly.

Check

and

repair

VARHO

(U9OB

2).

U15OOA

and

circuitry.

Vol, 2 Figure 9-19: Analog HoldoN Troubleshooting Procedure

~-:~-~~------~--~-~-~~-

~--------------------------------------

------------

---------~A~'~O~A~'~q~u~IS~"~,O~n;_-----VVbol.l.:2~S9~.99

TDS 520 Component Level Diagnostic and Repair Manual

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