Holtek HT32F52243 User manual
Holtek 32-Bit Microcontroller with Arm®Cortex®-M0+ Core
HT32F52243/HT32F52253
User Manual
Revision: V1.20 Date: September 19, 2018
Rev. 1.20 2 of 501 September 19, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52243/HT32F52253
Table of Contents
Table of Contents
1 Introduction........................................................................................................... 22
Overview.............................................................................................................................. 22
Features............................................................................................................................... 23
Device Information............................................................................................................... 27
Block Diagram ..................................................................................................................... 28
2 Document Conventions ....................................................................................... 29
3 System Architecture............................................................................................. 30
Arm®Cortex®-M0+ Processor .............................................................................................. 30
Bus Architecture................................................................................................................... 31
Memory Organization .......................................................................................................... 32
Memory Map................................................................................................................................... 33
Embedded Flash Memory............................................................................................................... 35
Embedded SRAM Memory ............................................................................................................. 35
AHB Peripherals ............................................................................................................................. 35
APB Peripherals ............................................................................................................................. 35
4 Flash Memory Controller (FMC) .......................................................................... 36
Introduction .......................................................................................................................... 36
Features............................................................................................................................... 36
Functional Descriptions ....................................................................................................... 37
Flash Memory Map ......................................................................................................................... 37
Flash Memory Architecture ............................................................................................................. 38
Wait State Setting ........................................................................................................................... 38
Booting Conguration ..................................................................................................................... 39
Page Erase ..................................................................................................................................... 40
Mass Erase..................................................................................................................................... 41
Word Programming......................................................................................................................... 42
Option Byte Description .................................................................................................................. 43
Page Erase/Program Protection ..................................................................................................... 44
Security Protection.......................................................................................................................... 45
Register Map ....................................................................................................................... 46
Register Descriptions........................................................................................................... 47
Flash Target Address Register – TADR .......................................................................................... 47
Flash Write Data Register – WRDR ............................................................................................... 48
Flash Operation Command Register – OCMR ............................................................................... 49
Flash Operation Control Register – OPCR..................................................................................... 50
Flash Operation Interrupt Enable Register – OIER ........................................................................ 51
Flash Operation Interrupt and Status Register – OISR .................................................................. 52
Flash Page Erase/Program Protection Status Register – PPSR.................................................... 53
Flash Security Protection Status Register – CPSR ........................................................................ 54
Rev. 1.20 3 of 501 September 19, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52243/HT32F52253
Table of Contents
Table of Contents
Flash Vector Mapping Control Register – VMCR ........................................................................... 55
Flash Manufacturer and Device ID Register – MDID...................................................................... 56
Flash Page Number Status Register – PNSR ................................................................................ 57
Flash Page Size Status Register – PSSR ...................................................................................... 58
Device ID Register – DIDR ............................................................................................................. 58
Flash Pre-fetch Control Register – CFCR ...................................................................................... 59
Custom ID Register n – CIDRn (n = 0 ~ 3) ..................................................................................... 60
5 Power Control Unit (PWRCU) .............................................................................. 61
Introduction .......................................................................................................................... 61
Features............................................................................................................................... 62
Functional Descriptions ....................................................................................................... 62
VDD Power Domain.......................................................................................................................... 62
1.5 V Power Domain....................................................................................................................... 64
Operation Modes ............................................................................................................................ 64
Register Map ....................................................................................................................... 66
Register Descriptions........................................................................................................... 67
Power Control Status Register – PWRSR ...................................................................................... 67
Power Control Register – PWRCR ................................................................................................. 68
VDD Power Domain Test Register – PWRTEST............................................................................... 70
Low Voltage / Brown Out Detect Control and Status Register – LVDCSR ..................................... 70
6 Clock Control Unit (CKCU) .................................................................................. 72
Introduction .......................................................................................................................... 72
Features............................................................................................................................... 72
Function Descriptions .......................................................................................................... 74
High Speed External Crystal Oscillator – HSE ............................................................................... 74
High Speed Internal RC Oscillator – HSI........................................................................................ 75
Auto Trimming of High Speed Internal RC Oscillator – HSI............................................................ 75
Phase Locked Loop – PLL.............................................................................................................. 76
Low Speed External Crystal Oscillator – LSE................................................................................. 78
Low Speed Internal RC Oscillator – LSI ......................................................................................... 78
Clock Ready Flag ........................................................................................................................... 78
System Clock (CK_SYS) Selection ................................................................................................ 79
HSE Clock Monitor ......................................................................................................................... 80
Clock Output Capability .................................................................................................................. 80
Register Map ....................................................................................................................... 81
Register Descriptions........................................................................................................... 82
Global Clock Conguration Register – GCFGR.............................................................................. 82
Global Clock Control Register – GCCR.......................................................................................... 83
Global Clock Status Register – GCSR ........................................................................................... 84
Global Clock Interrupt Register – GCIR.......................................................................................... 85
PLL Conguration Register – PLLCFGR ........................................................................................ 86
PLL Control Register – PLLCR....................................................................................................... 86
Rev. 1.20 4 of 501 September 19, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52243/HT32F52253
Table of Contents
AHB Conguration Register – AHBCFGR ...................................................................................... 87
AHB Clock Control Register – AHBCCR ........................................................................................ 88
APB Conguration Register – APBCFGR....................................................................................... 90
APB Clock Control Register 0 – APBCCR0.................................................................................... 91
APB Clock Control Register 1 – APBCCR1.................................................................................... 92
Clock Source Status Register – CKST ........................................................................................... 94
APB Peripheral Clock Selection Register 0 – APBPCSR0............................................................. 95
APB Peripheral Clock Selection Register 1 – APBPCSR1............................................................. 97
HSI Control Register – HSICR........................................................................................................ 99
HSI Auto Trimming Counter Register – HSIATCR ........................................................................ 100
MCU Debug Control Register – MCUDBGCR.............................................................................. 101
7 Reset Control Unit (RSTCU) .............................................................................. 104
Introduction ........................................................................................................................ 104
Functional Descriptions ..................................................................................................... 105
Power On Reset ........................................................................................................................... 105
System Reset ............................................................................................................................... 105
AHB and APB Unit Reset.............................................................................................................. 105
Register Map ..................................................................................................................... 106
Register Descriptions......................................................................................................... 107
Global Reset Status Register – GRSR ......................................................................................... 107
AHB Peripheral Reset Register – AHBPRSTR............................................................................. 108
APB Peripheral Reset Register 0 – APBPRSTR0 ........................................................................ 109
APB Peripheral Reset Register 1 – APBPRSTR1 .........................................................................110
8 General Purpose I/O (GPIO)............................................................................... 112
Introduction ........................................................................................................................ 112
Features............................................................................................................................. 113
Functional Descriptions ..................................................................................................... 113
Default GPIO Pin Conguration.....................................................................................................113
General Purpose I/O – GPIO.........................................................................................................113
GPIO Locking Mechanism .............................................................................................................115
Register Map ..................................................................................................................... 115
Register Descriptions......................................................................................................... 116
Port A Data Direction Control Register – PADIRCR ......................................................................116
Port A Input Function Enable Control Register – PAINER.............................................................117
Port A Pull-Up Selection Register – PAPUR ..................................................................................118
Port A Pull-Down Selection Register – PAPDR .............................................................................119
Port A Open Drain Selection Register – PAODR.......................................................................... 120
Port A Output Current Drive Selection Register – PADRVR ......................................................... 121
Port A Lock Register – PALOCKR ................................................................................................ 122
Port A Data Input Register – PADINR........................................................................................... 123
Port A Output Data Register – PADOUTR .................................................................................... 123
Port A Output Set/Reset Control Register – PASRR .................................................................... 124
Rev. 1.20 5 of 501 September 19, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52243/HT32F52253
Table of Contents
Table of Contents
Port A Output Reset Register – PARR.......................................................................................... 125
Port B Data Direction Control Register – PBDIRCR..................................................................... 125
Port B Input Function Enable Control Register – PBINER ........................................................... 126
Port B Pull-Up Selection Register – PBPUR ................................................................................ 127
Port B Pull-Down Selection Register – PBPDR............................................................................ 128
Port B Open Drain Selection Register – PBODR ......................................................................... 129
Port B Output Current Drive Selection Register – PBDRVR ........................................................ 130
Port B Lock Register – PBLOCKR................................................................................................ 131
Port B Data Input Register – PBDINR .......................................................................................... 132
Port B Output Data Register – PBDOUTR ................................................................................... 132
Port B Output Set/Reset Control Register – PBSRR.................................................................... 133
Port B Output Reset Register – PBRR ......................................................................................... 134
Port C Data Direction Control Register – PCDIRCR .................................................................... 134
Port C Input Function Enable Control Register – PCINER ........................................................... 135
Port C Pull-Up Selection Register – PCPUR ................................................................................ 136
Port C Pull-Down Selection Register – PCPDR ........................................................................... 137
Port C Open Drain Selection Register – PCODR ......................................................................... 138
Port C Output Current Drive Selection Register – PCDRVR ........................................................ 139
Port C Lock Register – PCLOCKR ............................................................................................... 140
Port C Data Input Register – PCDINR.......................................................................................... 141
Port C Output Data Register – PCDOUTR ................................................................................... 141
Port C Output Set/Reset Control Register – PCSRR ................................................................... 142
Port C Output Reset Register – PCRR......................................................................................... 143
Port D Data Direction Control Register – PDDIRCR .................................................................... 143
Port D Input Function Enable Control Register – PDINER ........................................................... 144
Port D Pull-Up Selection Register – PDPUR ................................................................................ 145
Port D Pull-Down Selection Register – PDPDR ........................................................................... 146
Port D Open Drain Selection Register – PDODR ......................................................................... 147
Port D Output Current Drive Selection Register – PDDRVR ........................................................ 148
Port D Lock Register – PDLOCKR ............................................................................................... 149
Port D Data Input Register – PDDINR.......................................................................................... 150
Port D Output Data Register – PDDOUTR ................................................................................... 150
Port D Output Set/Reset Control Register – PDSRR ................................................................... 151
Port D Output Reset Register – PDRR......................................................................................... 152
9 Alternate Function Input/Output Control Unit (AFIO)...................................... 153
Introduction ........................................................................................................................ 153
Features............................................................................................................................. 154
Functional Descriptions ..................................................................................................... 154
External Interrupt Pin Selection .................................................................................................... 154
Alternate Function......................................................................................................................... 155
Lock Mechanism .......................................................................................................................... 155
Register Map ..................................................................................................................... 155
Register Descriptions......................................................................................................... 156
EXTI Source Selection Register 0 – ESSR0 ................................................................................ 156
Rev. 1.20 6 of 501 September 19, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52243/HT32F52253
Table of Contents
EXTI Source Selection Register 1 – ESSR1 ................................................................................ 157
GPIO Port x Conguration Low Register – GPxCFGLR, x = A, B, C, D ....................................... 158
GPIO Port x Conguration High Register – GPxCFGHR, x = A, B, C, D...................................... 159
10 Nested Vectored Interrupt Controller (NVIC).................................................. 160
Introduction ........................................................................................................................ 160
Features............................................................................................................................. 161
Function Descriptions ........................................................................................................ 162
SysTick Calibration ....................................................................................................................... 162
Register Map ..................................................................................................................... 162
11 External Interrupt / Event Controller (EXTI).................................................... 163
Introduction ........................................................................................................................ 163
Features............................................................................................................................. 163
Function Descriptions ........................................................................................................ 164
Wakeup Event Management......................................................................................................... 164
External Interrupt/Event Line Mapping ......................................................................................... 165
Interrupt and Debounce ................................................................................................................ 165
Register Map .................................................................................................................... 166
Register Descriptions......................................................................................................... 167
EXTI Interrupt Conguration Register n – EXTICFGRn, n = 0 ~ 15 ............................................. 167
EXTI Interrupt Control Register – EXTICR ................................................................................... 168
EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR................................................................ 169
EXTI Interrupt Edge Status Register – EXTIEDGESR ................................................................. 170
EXTI Interrupt Software Set Command Register – EXTISSCR.................................................... 170
EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR ........................................................ 171
EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR ................................................... 172
EXTI Interrupt Wakeup Flag Register – EXTIWAKUPFLG........................................................... 172
12 Analog to Digital Converter (ADC) .................................................................. 173
Introduction ........................................................................................................................ 173
Features............................................................................................................................. 174
Function Descriptions ........................................................................................................ 175
ADC Clock Setup.......................................................................................................................... 175
Channel Selection......................................................................................................................... 175
Conversion Mode.......................................................................................................................... 175
Start Conversion on External Event.............................................................................................. 178
Sampling Time Setting.................................................................................................................. 179
Data Format.................................................................................................................................. 179
Analog Watchdog.......................................................................................................................... 179
Interrupts....................................................................................................................................... 180
Register Map ..................................................................................................................... 181
Register Descriptions......................................................................................................... 182
ADC Conversion Control Register – ADCCR ............................................................................... 182
Rev. 1.20 7 of 501 September 19, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52243/HT32F52253
Table of Contents
Table of Contents
ADC Conversion List Register 0 – ADCLST0............................................................................... 183
ADC Conversion List Register 1 – ADCLST1............................................................................... 184
ADC Input Sampling Time Register – ADCSTR ........................................................................... 185
ADC Conversion Data Register y – ADCDRy, y = 0 ~ 7 ............................................................... 186
ADC Trigger Control Register – ADCTCR .................................................................................... 187
ADC Trigger Source Register – ADCTSR..................................................................................... 188
ADC Watchdog Control Register – ADCWCR .............................................................................. 189
ADC Watchdog Threshold Register – ADCTR.............................................................................. 190
ADC Interrupt Enable Register – ADCIER................................................................................... 191
ADC Interrupt Raw Status Register – ADCIRAW ......................................................................... 192
ADC Interrupt Status Register – ADCISR..................................................................................... 193
ADC Interrupt Clear Register – ADCICLR .................................................................................... 194
13 General-Purpose Timer (GPTM) ...................................................................... 195
Introduction ........................................................................................................................ 195
Features............................................................................................................................. 196
Functional Descriptions ..................................................................................................... 196
Counter Mode ............................................................................................................................... 196
Clock Controller ............................................................................................................................ 198
Trigger Controller.......................................................................................................................... 199
Slave Controller ............................................................................................................................ 201
Master Controller .......................................................................................................................... 203
Channel Controller........................................................................................................................ 203
Input Stage ................................................................................................................................... 206
Quadrature Decoder ..................................................................................................................... 207
Output Stage................................................................................................................................. 209
Update Management .................................................................................................................... 213
Single Pulse Mode........................................................................................................................ 213
Asymmetric PWM Mode ............................................................................................................... 215
Timer Interconnection ................................................................................................................... 216
Trigger ADC Start.......................................................................................................................... 219
PDMA Request ............................................................................................................................. 219
Register Map ..................................................................................................................... 220
Register Descriptions......................................................................................................... 221
Timer Counter Conguration Register – CNTCFR ....................................................................... 221
Timer Mode Conguration Register – MDCFR............................................................................. 222
Timer Trigger Conguration Register – TRCFR............................................................................ 225
Timer Control Register – CTR ...................................................................................................... 226
Channel 0 Input Conguration Register – CH0ICFR .................................................................... 227
Channel 1 Input Conguration Register – CH1ICFR .................................................................... 229
Channel 2 Input Conguration Register – CH2ICFR .................................................................... 231
Channel 3 Input Conguration Register – CH3ICFR .................................................................... 233
Channel 0 Output Conguration Register – CH0OCFR ............................................................... 235
Channel 1 Output Conguration Register – CH1OCFR ............................................................... 237
Rev. 1.20 8 of 501 September 19, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52243/HT32F52253
Table of Contents
Channel 2 Output Conguration Register – CH2OCFR ............................................................... 239
Channel 3 Output Conguration Register – CH3OCFR ............................................................... 241
Channel Control Register – CHCTR............................................................................................. 243
Channel Polarity Conguration Register – CHPOLR.................................................................... 244
Timer PDMA/Interrupt Control Register – DICTR......................................................................... 245
Timer Event Generator Register – EVGR..................................................................................... 246
Timer Interrupt Status Register – INTSR...................................................................................... 248
Timer Counter Register – CNTR................................................................................................... 250
Timer Prescaler Register – PSCR ................................................................................................ 250
Timer Counter Reload Register – CRR ........................................................................................ 251
Channel 0 Capture/Compare Register – CH0CCR ...................................................................... 251
Channel 1 Capture/Compare Register – CH1CCR ...................................................................... 252
Channel 2 Capture/Compare Register – CH2CCR ...................................................................... 253
Channel 3 Capture/Compare Register – CH3CCR ...................................................................... 254
Channel 0 Asymmetric Compare Register – CH0ACR................................................................. 255
Channel 1 Asymmetric Compare Register – CH1ACR................................................................. 255
Channel 2 Asymmetric Compare Register – CH2ACR................................................................. 256
Channel 3 Asymmetric Compare Register – CH3ACR................................................................. 256
14 Basic Function Timer (BFTM).......................................................................... 257
Introduction ........................................................................................................................ 257
Features............................................................................................................................. 257
Functional Description ....................................................................................................... 258
Repetitive Mode............................................................................................................................ 258
One Shot Mode............................................................................................................................. 259
Trigger ADC Start.......................................................................................................................... 260
Register Map ..................................................................................................................... 260
Register Descriptions......................................................................................................... 261
BFTM Control Register – BFTMCR .............................................................................................. 261
BFTM Status Register – BFTMSR................................................................................................ 262
BFTM Counter Register – BFTMCNTR ........................................................................................ 263
BFTM Compare Value Register – BFTMCMPR ........................................................................... 263
15 Motor Control Timer (MCTM) ........................................................................... 264
Introduction ........................................................................................................................ 264
Features............................................................................................................................. 265
Functional Descriptions ..................................................................................................... 266
Counter Mode ............................................................................................................................... 266
Clock Controller ............................................................................................................................ 269
Trigger Controller.......................................................................................................................... 269
Slave Controller ............................................................................................................................ 271
Master Controller .......................................................................................................................... 273
Channel Controller........................................................................................................................ 274
Input Stage ................................................................................................................................... 275
Rev. 1.20 9 of 501 September 19, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52243/HT32F52253
Table of Contents
Table of Contents
Output Stage................................................................................................................................. 277
Update Management .................................................................................................................... 287
Single Pulse Mode........................................................................................................................ 289
Asymmetric PWM Mode ............................................................................................................... 291
Timer Interconnection ................................................................................................................... 292
Trigger ADC Start.......................................................................................................................... 296
Lock Level Table ........................................................................................................................... 296
PDMA Request ............................................................................................................................. 297
Register Map ..................................................................................................................... 298
Register Descriptions......................................................................................................... 299
Timer Counter Conguration Register – CNTCFR ....................................................................... 299
Timer Mode Conguration Register – MDCFR............................................................................. 300
Timer Trigger Conguration Register – TRCFR............................................................................ 303
Timer Control Register – CTR ...................................................................................................... 304
Channel 0 Input Conguration Register – CH0ICFR .................................................................... 305
Channel 1 Input Conguration Register – CH1ICFR .................................................................... 307
Channel 2 Input Conguration Register – CH2ICFR .................................................................... 309
Channel 3 Input Conguration Register – CH3ICFR .....................................................................311
Channel 0 Output Conguration Register – CH0OCFR ............................................................... 313
Channel 1 Output Conguration Register – CH1OCFR ............................................................... 315
Channel 2 Output Conguration Register – CH2OCFR ............................................................... 317
Channel 3 Output Conguration Register – CH3OCFR ............................................................... 319
Channel Control Register – CHCTR............................................................................................. 321
Channel Polarity Conguration Register – CHPOLR.................................................................... 323
Channel Break Conguration Register – CHBRKCFR ................................................................. 324
Channel Break Control Register – CHBRKCTR ........................................................................... 325
Timer PDMA/Interrupt Control Register – DICTR......................................................................... 327
Timer Event Generator Register – EVGR..................................................................................... 329
Timer Interrupt Status Register – INTSR...................................................................................... 331
Timer Counter Register – CNTR................................................................................................... 333
Timer Prescaler Register – PSCR ................................................................................................ 334
Timer Counter Reload Register – CRR ........................................................................................ 335
Timer Repetition Register – REPR ............................................................................................... 335
Channel 0 Capture/Compare Register – CH0CCR ...................................................................... 336
Channel 1 Capture/Compare Register – CH1CCR ...................................................................... 337
Channel 2 Capture/Compare Register – CH2CCR ...................................................................... 338
Channel 3 Capture/Compare Register – CH3CCR ...................................................................... 339
Channel 0 Asymmetric Compare Register – CH0ACR................................................................. 340
Channel 1 Asymmetric Compare Register – CH1ACR................................................................. 340
Channel 2 Asymmetric Compare Register – CH2ACR................................................................. 341
Channel 3 Asymmetric Compare Register – CH3ACR................................................................. 341
Rev. 1.20 10 of 501 September 19, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52243/HT32F52253
Table of Contents
16 Single-Channel Timer (SCTM) ......................................................................... 342
Introduction ........................................................................................................................ 342
Features............................................................................................................................. 342
Functional Descriptions ..................................................................................................... 343
Counter Mode ............................................................................................................................... 343
Clock Controller ............................................................................................................................ 343
Trigger Controller.......................................................................................................................... 344
Slave Controller ............................................................................................................................ 346
Channel Controller........................................................................................................................ 348
Input Stage ................................................................................................................................... 349
Output Stage................................................................................................................................. 350
Update Management .................................................................................................................... 353
Register Map ..................................................................................................................... 354
Register Descriptions......................................................................................................... 355
Timer Counter Conguration Register – CNTCFR ....................................................................... 355
Timer Mode Conguration Register – MDCFR............................................................................. 356
Timer Trigger Conguration Register – TRCFR............................................................................ 357
Timer Control Register – CTR ...................................................................................................... 358
Channel Input Conguration Register – CHICFR ......................................................................... 359
Channel Output Conguration Register – CHOCFR .................................................................... 361
Channel Control Register – CHCTR............................................................................................. 362
Channel Polarity Conguration Register – CHPOLR.................................................................... 363
Timer Interrupt Control Register – DICTR .................................................................................... 364
Timer Event Generator Register – EVGR..................................................................................... 365
Timer Interrupt Status Register – INTSR...................................................................................... 366
Timer Counter Register – CNTR................................................................................................... 367
Timer Prescaler Register – PSCR ................................................................................................ 367
Timer Counter Reload Register – CRR ........................................................................................ 368
Channel Capture/Compare Register – CHCCR ........................................................................... 369
17 Real Time Clock (RTC) ..................................................................................... 370
Introduction ........................................................................................................................ 370
Features............................................................................................................................. 370
Functional Descriptions ..................................................................................................... 371
RTC Related Register Reset ........................................................................................................ 371
Reading RTC Register.................................................................................................................. 371
Low Speed Clock Conguration ................................................................................................... 371
RTC Counter Operation................................................................................................................ 372
Interrupt and Wakeup Control....................................................................................................... 372
RTCOUT Output Pin Conguration............................................................................................... 373
Register Map ..................................................................................................................... 374
Register Descriptions......................................................................................................... 374
RTC Counter Register – RTCCNT................................................................................................ 374
RTC Compare Register – RTCCMP............................................................................................. 375
Rev. 1.20 11 of 501 September 19, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52243/HT32F52253
Table of Contents
Table of Contents
RTC Control Register – RTCCR................................................................................................... 376
RTC Status Register – RTCSR..................................................................................................... 378
RTC Interrupt and Wakeup Enable Register – RTCIWEN............................................................ 379
18 Watchdog Timer (WDT) .................................................................................... 380
Introduction ........................................................................................................................ 380
Features............................................................................................................................. 380
Functional Description ....................................................................................................... 381
Register Map ..................................................................................................................... 382
Register Descriptions......................................................................................................... 383
Watchdog Timer Control Register – WDTCR ............................................................................... 383
Watchdog Timer Mode Register 0 – WDTMR0............................................................................. 384
Watchdog Timer Mode Register 1 – WDTMR1............................................................................. 385
Watchdog Timer Status Register – WDTSR ................................................................................. 386
Watchdog Timer Protection Register – WDTPR ........................................................................... 387
Watchdog Timer Clock Selection Register – WDTCSR................................................................ 388
19 Inter-Integrated Circuit – I2C............................................................................ 389
Introduction ........................................................................................................................ 389
Features............................................................................................................................. 390
Functional Descriptions ..................................................................................................... 390
Two Wire Serial Interface.............................................................................................................. 390
START and STOP Conditions....................................................................................................... 390
Data Validity.................................................................................................................................. 391
Addressing Format ....................................................................................................................... 392
Data Transfer and Acknowledge................................................................................................... 393
Clock Synchronization .................................................................................................................. 394
Arbitration ..................................................................................................................................... 395
General Call Address.................................................................................................................... 395
Bus Error....................................................................................................................................... 395
Address Mask Enable................................................................................................................... 396
Address Snoop ............................................................................................................................. 396
Operation Mode ............................................................................................................................ 396
Master Transmitter Mode.............................................................................................................. 396
Master Receiver Mode.................................................................................................................. 397
Slave Transmitter Mode................................................................................................................ 399
Slave Receiver Mode.................................................................................................................... 400
Conditions of Holding SCL Line.................................................................................................... 401
I2C Timeout Function .................................................................................................................... 402
PDMA Interface............................................................................................................................. 402
Register Map ..................................................................................................................... 403
Register Descriptions......................................................................................................... 404
I2C Control Register – I2CCR ....................................................................................................... 404
I2C Interrupt Enable Register – I2CIER ........................................................................................ 406
Rev. 1.20 12 of 501 September 19, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52243/HT32F52253
Table of Contents
I2C Address Register – I2CADDR................................................................................................. 407
I2C Status Register – I2CSR......................................................................................................... 408
I2C SCL High Period Generation Register – I2CSHPGR...............................................................411
I2C SCL Low Period Generation Register – I2CSLPGR ............................................................... 412
I2C Data Register – I2CDR ........................................................................................................... 413
I2C Target Register – I2CTAR ....................................................................................................... 414
I2C Address Mask Register – I2CADDMR .................................................................................... 415
I2C Address Snoop Register – I2CADDSR................................................................................... 416
I2C Timeout Register – I2CTOUT.................................................................................................. 417
20 Serial Peripheral Interface (SPI) ...................................................................... 418
Introduction ........................................................................................................................ 418
Features............................................................................................................................. 419
Function Descriptions ........................................................................................................ 419
Master Mode................................................................................................................................. 419
Slave Mode................................................................................................................................... 419
SPI Serial Frame Format .............................................................................................................. 420
Status Flags.................................................................................................................................. 424
PDMA Interface............................................................................................................................. 427
Register Map ..................................................................................................................... 427
Register Descriptions......................................................................................................... 428
SPI Control Register 0 – SPICR0 ................................................................................................. 428
SPI Control Register 1 – SPICR1 ................................................................................................. 430
SPI Interrupt Enable Register – SPIIER ....................................................................................... 432
SPI Clock Prescaler Register – SPICPR ...................................................................................... 433
SPI Data Register – SPIDR .......................................................................................................... 434
SPI Status Register – SPISR........................................................................................................ 435
SPI FIFO Control Register – SPIFCR........................................................................................... 436
SPI FIFO Status Register – SPIFSR ............................................................................................ 437
SPI FIFO Time Out Counter Register – SPIFTOCR..................................................................... 438
21 Universal Synchronous Asynchronous Receiver Transmitter (USART) .... 439
Introduction ........................................................................................................................ 439
Features............................................................................................................................ 440
Function Descriptions ........................................................................................................ 441
Serial Data Format........................................................................................................................ 441
Baud Rate Generation .................................................................................................................. 442
Hardware Flow Control ................................................................................................................. 443
IrDA............................................................................................................................................... 445
RS485 Mode................................................................................................................................. 447
Synchronous Master Mode........................................................................................................... 449
Interrupts and Status .................................................................................................................... 451
PDMA Interface............................................................................................................................. 451
Register Map ..................................................................................................................... 452
Rev. 1.20 13 of 501 September 19, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52243/HT32F52253
Table of Contents
Table of Contents
Register Descriptions......................................................................................................... 453
USART Data Register – USRDR.................................................................................................. 453
USART Control Register – USRCR.............................................................................................. 454
USART FIFO Control Register – USRFCR................................................................................... 456
USART Interrupt Enable Register – USRIER ............................................................................... 457
USART Status & Interrupt Flag Register – USRSIFR................................................................... 458
USART Timing Parameter Register – USRTPR ........................................................................... 460
USART IrDA Control Register – IrDACR ..................................................................................... 461
USART RS485 Control Register – RS485CR............................................................................... 462
USART Synchronous Control Register – SYNCR ........................................................................ 463
USART Divider Latch Register – USRDLR.................................................................................. 464
USART Test Register – USRTSTR.............................................................................................. 465
22 Universal Asynchronous Receiver Transmitter (UART)............................... 466
Introduction ........................................................................................................................ 466
Features............................................................................................................................ 467
Function Descriptions ........................................................................................................ 467
Serial Data Format........................................................................................................................ 467
Baud Rate Generation .................................................................................................................. 468
Interrupts and Status .................................................................................................................... 469
PDMA Interface............................................................................................................................. 469
Register Map ..................................................................................................................... 470
Register Descriptions......................................................................................................... 470
UART Data Register – URDR....................................................................................................... 470
UART Control Register – URCR................................................................................................... 471
UART Interrupt Enable Register – URIER.................................................................................... 473
UART Status & Interrupt Flag Register – URSIFR ....................................................................... 474
UART Divider Latch Register – URDLR ....................................................................................... 475
UART Test Register – URTSTR................................................................................................... 476
23 Peripheral Direct Memory Access (PDMA)..................................................... 477
Introduction ........................................................................................................................ 477
Features............................................................................................................................. 477
Functional Description ....................................................................................................... 478
AHB Master .................................................................................................................................. 478
PDMA Channel ............................................................................................................................. 478
PDMA Request Mapping .............................................................................................................. 478
Channel transfer ........................................................................................................................... 479
Channel Priority ............................................................................................................................ 479
Transfer Request .......................................................................................................................... 480
Address Mode............................................................................................................................... 480
Auto-Reload.................................................................................................................................. 481
Transfer Interrupt .......................................................................................................................... 481
Register Map ..................................................................................................................... 482
Rev. 1.20 14 of 501 September 19, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52243/HT32F52253
Table of Contents
Register Descriptions......................................................................................................... 483
PDMA Channel n Control Register – PDMACHnCR, n = 0 ~ 5 .................................................... 483
PDMA Channel n Source Address Register – PDMACHnSADR, n = 0 ~ 5.................................. 485
PDMA Channel n Destination Address Register – PDMACHnDADR, n = 0 ~ 5........................... 485
PDMA Channel n Transfer Size Register – PDMACHnTSR, n = 0 ~ 5........................................ 486
PDMA Channel n Current Transfer Size Register – PDMACHnCTSR, n = 0 ~ 5......................... 487
PDMA Interrupt Status Register – PDMAISR ............................................................................... 487
PDMA Interrupt Status Clear Register – PDMAISCR................................................................... 489
PDMA Interrupt Enable Register – PDMAIER .............................................................................. 490
24 Cyclic Redundancy Check (CRC).................................................................... 491
Introduction ....................................................................................................................... 491
Features............................................................................................................................. 491
Function Descriptions ........................................................................................................ 492
CRC Computation......................................................................................................................... 492
Byte and Bit Reversal for CRC Computation................................................................................ 492
CRC with PDMA ........................................................................................................................... 493
Register Map ..................................................................................................................... 493
Register Descriptions......................................................................................................... 494
CRC Control Register – CRCCR .................................................................................................. 494
CRC Seed Register – CRCSDR................................................................................................... 495
CRC Checksum Register – CRCCSR .......................................................................................... 495
CRC Data Register – CRCDR ...................................................................................................... 496
25 Divider (DIV) ...................................................................................................... 497
Introduction ........................................................................................................................ 497
Features............................................................................................................................. 497
Functional Descriptions ..................................................................................................... 497
Register Map ..................................................................................................................... 498
Register Descriptions......................................................................................................... 498
Divider Control Register – CR ...................................................................................................... 498
Dividend Data Register – DDR ..................................................................................................... 499
Divisor Data Register – DSR ........................................................................................................ 499
Quotient Data Register – QTR...................................................................................................... 500
Remainder Data Register – RMR ................................................................................................. 500
Rev. 1.20 15 of 501 September 19, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52243/HT32F52253
Table of Contents
List of Tables
List of Tables
Table 1. Features and Peripheral List ..................................................................................................... 27
Table 2. Document Conventions............................................................................................................. 29
Table 3. Register Map............................................................................................................................. 34
Table 4. Flash Memory and Option Byte................................................................................................. 38
Table 5. Relationship between wait state cycle and HCLK..................................................................... 38
Table 6. Booting Modes .......................................................................................................................... 39
Table 7. Option Byte Memory Map ......................................................................................................... 43
Table 8. Access Permission of Protected Main Flash Page.................................................................... 44
Table 9. Access Permission When Security Protection is Enabled......................................................... 45
Table 10. FMC Register Map .................................................................................................................. 46
Table 11. Operation Mode Denitions..................................................................................................... 64
Table 12. Enter/Exit Power Saving Modes.............................................................................................. 65
Table 13. Power Status After System Reset ........................................................................................... 66
Table 14. PWRCU Register Map ............................................................................................................ 66
Table 15. Output Divider2 Value Mapping............................................................................................... 77
Table 16. Feedback Divider2 Value Mapping.......................................................................................... 77
Table 17. CKOUT Clock Source ............................................................................................................. 80
Table 18. CKCU Register Map ............................................................................................................... 81
Table 19. RSTCU Register Map ........................................................................................................... 106
Table 20. AFIO, GPIO and IO Pad Control Signal True Table................................................................114
Table 21. GPIO Register Map................................................................................................................115
Table 22. AFIO Selection for Peripheral Map Example......................................................................... 155
Table 23. AFIO Register Map................................................................................................................ 155
Table 24. Exception Types.................................................................................................................... 160
Table 25. NVIC Register Map ............................................................................................................... 162
Table 26. EXTI Register Map................................................................................................................ 166
Table 27. Data format in ADCDR [15:0] ................................................................................................ 179
Table 28. A/D Converter Register Map ................................................................................................. 181
Table 29. Counting Direction and Encoding Signals............................................................................. 208
Table 30. Compare Match Output Setup .............................................................................................. 210
Table 31. GPTM Register Map ............................................................................................................. 220
Table 32. GPTM Internal Trigger Connection ....................................................................................... 225
Table 33. BFTM Register Map .............................................................................................................. 260
Table 34. Compare Match Output Setup .............................................................................................. 278
Table 35. Output Control Bits for Complementary Output with a Break Event Occurrence.................. 286
Table 36. Lock Level Table.................................................................................................................... 296
Table 37. MCTM Register Map ............................................................................................................. 298
Table 38. MCTM Internal Trigger Connection ....................................................................................... 303
Table 39. Compare Match Output Setup .............................................................................................. 351
Rev. 1.20 16 of 501 September 19, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52243/HT32F52253
List of Tables
Table 40. SCTM Register Map.............................................................................................................. 354
Table 41. LSE Startup Mode Operating Current and Startup Time....................................................... 371
Table 42. RTCOUT Output Mode and Active Level Setting .................................................................. 373
Table 43. RTC Register Map................................................................................................................. 374
Table 44. Watchdog Timer Register Map.............................................................................................. 382
Table 45. Conditions of Holding SCL line.............................................................................................. 401
Table 46. I2C Register Map ................................................................................................................... 403
Table 47. I2C Clock Setting Example .................................................................................................... 412
Table 48. SPI Interface Format Setup................................................................................................... 420
Table 49. SPI Mode Fault Trigger Conditions ....................................................................................... 425
Table 50. SPI Master Mode SEL Pin Status. ........................................................................................ 426
Table 51. SPI Register Map .................................................................................................................. 427
Table 52. Baud Rate Deviation Error Calculation – CK_USART = 40 MHz.......................................... 442
Table 53. Baud Rate Deviation Error Calculation – CK_USART = 48 MHz.......................................... 443
Table 54. USART Register Map............................................................................................................ 452
Table 55. Baud Rate Deviation Error Calculation – CK_UART = 40 MHz. ........................................... 468
Table 56. Baud Rate Deviation Error Calculation – CK_UART = 48 MHz. ........................................... 469
Table 57. UART Register Map .............................................................................................................. 470
Table 58. PDMA Channel Assignments ................................................................................................ 479
Table 59. PDMA Address Modes .......................................................................................................... 480
Table 60. PDMA Register Map.............................................................................................................. 482
Table 61. CRC Register Map ................................................................................................................ 493
Table 62. DIV Register Map.................................................................................................................. 498
Rev. 1.20 17 of 501 September 19, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52243/HT32F52253
List of Tables
List of Figures
List of Figures
Figure 1. Block Diagram ......................................................................................................................... 28
Figure 2. Cortex®-M0+ Block Diagram.................................................................................................... 31
Figure 3. Bus Architecture ...................................................................................................................... 32
Figure 4. Memory Map............................................................................................................................ 33
Figure 5. Flash Memory Controller Block Diagram................................................................................. 36
Figure 6. Flash Memory Map.................................................................................................................. 37
Figure 7. Vector Remapping ................................................................................................................... 39
Figure 8. Page Erase Operation Flowchart ............................................................................................ 40
Figure 9. Mass Erase Operation Flowchart ............................................................................................ 41
Figure 10. Word Programming Operation Flowchart .............................................................................. 42
Figure 11. PWRCU Block Diagram......................................................................................................... 61
Figure 12. Power On Reset / Power Down Reset Waveform ................................................................. 63
Figure 13. CKCU Block Diagram ............................................................................................................ 73
Figure 14. External Crystal, Ceramic, and Resonators for HSE............................................................. 74
Figure 15. HSI Auto Trimming Block Diagram ........................................................................................ 76
Figure 16. PLL Block Diagram ................................................................................................................ 76
Figure 17. External Crystal, Ceramic, and Resonators for LSE ............................................................ 78
Figure 18. RSTCU Block Diagram........................................................................................................ 104
Figure 19. Power On Reset Sequence ................................................................................................. 105
Figure 20. GPIO Block Diagram ............................................................................................................112
Figure 21. AFIO/GPIO Control Signal....................................................................................................114
Figure 22. AFIO Block Diagram ............................................................................................................ 153
Figure 23. EXTI Channel Input Selection ............................................................................................. 154
Figure 24. EXTI Block Diagram ............................................................................................................ 163
Figure 25. EXTI Wake-up Event Management ..................................................................................... 164
Figure 26. EXTI Interrupt Debounce Function ...................................................................................... 165
Figure 27. ADC Block Diagram............................................................................................................. 173
Figure 28. One Shot Conversion Mode ................................................................................................ 176
Figure 29. Continuous Conversion Mode ............................................................................................. 176
Figure 30. Discontinuous Conversion Mode......................................................................................... 178
Figure 31. GPTM Block Diagram.......................................................................................................... 195
Figure 32. Up-counting Example .......................................................................................................... 197
Figure 33. Down-counting Example...................................................................................................... 197
Figure 34. Center-aligned Counting Example....................................................................................... 198
Figure 35. GPTM Clock Selection Source ............................................................................................ 199
Figure 36. Trigger Control Block ........................................................................................................... 200
Figure 37. Slave Controller Diagram .................................................................................................... 201
Figure 38. GPTM in Restart Mode........................................................................................................ 201
Figure 39. GPTM in Pause Mode ......................................................................................................... 202
Rev. 1.20 18 of 501 September 19, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52243/HT32F52253
List of Figures
Figure 40. GPTM in Trigger Mode ........................................................................................................ 202
Figure 41. Master GPTMn and Slave GPTMm/MCTMm Connection................................................... 203
Figure 42. MTO Selection..................................................................................................................... 203
Figure 43. Capture/Compare Block Diagram........................................................................................ 204
Figure 44. Input Capture Mode............................................................................................................. 204
Figure 45. PWM Pulse Width Measurement Example.......................................................................... 205
Figure 46. Channel 0 and Channel 1 Input Stages............................................................................... 206
Figure 47. Channel 2 and Channel 3 Input Stages............................................................................... 206
Figure 48. TI0 Digital Filter Diagram with N = 2.................................................................................... 207
Figure 49. Input Stage and Quadrature Decoder Block Diagram ......................................................... 208
Figure 50. Both TI0 and TI1 Quadrature Decoder Counting................................................................. 209
Figure 51. Output Stage Block Diagram ............................................................................................... 209
Figure 52. Toggle Mode Channel Output Reference Signal (CHxPRE = 0) ......................................... 210
Figure 53. Toggle Mode Channel Output Reference Signal (CHxPRE = 1) ..........................................211
Figure 54. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode .............211
Figure 55. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ....... 212
Figure 56. PWM Mode Channel Output Reference Signal and Counter in Center-align Mode............ 212
Figure 57. Update Event Setting Diagram ............................................................................................ 213
Figure 58. Single Pulse Mode............................................................................................................... 214
Figure 59. Immediate Active Mode Minimum Delay ............................................................................. 215
Figure 60. Asymmetric PWM Mode versus Center Align Counting Mode............................................. 216
Figure 61. Pausing MCTM using the GPTM CH0OREF Signal............................................................ 217
Figure 62. Triggering MCTM with GPTM Update Event ....................................................................... 217
Figure 63. Trigger GPTM and MCTM with the GPTM CH0 Input ......................................................... 218
Figure 64. GPTM PDMA Mapping Diagram.......................................................................................... 219
Figure 65. BFTM Block Diagram .......................................................................................................... 257
Figure 66. BFTM – Repetitive Mode..................................................................................................... 258
Figure 67. BFTM – One Shot Mode...................................................................................................... 259
Figure 68. BFTM – One Shot Mode Counter Updating ....................................................................... 259
Figure 69. MCTM Block Diagram ......................................................................................................... 264
Figure 70. Up-counting Example .......................................................................................................... 266
Figure 71. Down-counting Example...................................................................................................... 267
Figure 72. Center-aligned Counting Example....................................................................................... 267
Figure 73. Update Event 1 Dependent Repetition Mechanism Example.............................................. 268
Figure 74. MCTM Clock Selection Source............................................................................................ 269
Figure 75. Trigger Controller Block ....................................................................................................... 270
Figure 76. Slave Controller Diagram .................................................................................................... 271
Figure 77. MCTM in Restart Mode ....................................................................................................... 271
Figure 78. MCTM in Pause Mode......................................................................................................... 272
Figure 79. MCTM in Trigger Mode........................................................................................................ 272
Figure 80. Master MCTMn and Slave GPTM Connection .................................................................... 273
Rev. 1.20 19 of 501 September 19, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52243/HT32F52253
List of Figures
List of Figures
Figure 81. MTO Selection..................................................................................................................... 273
Figure 82. Capture/Compare Block Diagram........................................................................................ 274
Figure 83. Input Capture Mode............................................................................................................. 274
Figure 84. PWM Pulse Width Measurement Example.......................................................................... 275
Figure 85. Channel 0 and Channel 1 Input Stages............................................................................... 276
Figure 86. Channel 2 and Channel 3 Input Stages............................................................................... 276
Figure 87. TI0 Digital Filter Diagram with N = 2.................................................................................... 277
Figure 88. Output Stage Block Diagram ............................................................................................... 278
Figure 89. Toggle Mode Channel Output Reference Signal – CHxPRE = 0......................................... 279
Figure 90. Toggle Mode Channel Output Reference Signal – CHxPRE = 1......................................... 279
Figure 91. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode ............ 280
Figure 92. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ....... 280
Figure 93. PWM Mode 1 Channel Output Reference Signal and Counter in Center-aligned Counting
Mode...................................................................................................................................................... 281
Figure 94. Dead-time Insertion Performed for Complementary Outputs .............................................. 282
Figure 95. MCTM Break Signal Bolck Diagram .................................................................................... 282
Figure 96. MT_BRK Pin Digital Filter Diagram with N = 2 .................................................................... 283
Figure 97. Channel 3 Output with a Break Event Occurrence.............................................................. 284
Figure 98. Channel 0 ~2 Complementary Outputs with a Break Event Occurrence............................. 284
Figure 99. Channel 0 ~2 Only One Output Enabled when Break Event Occurs .................................. 285
Figure 100. Hardware Protection When Both CHxO and CHxNO are in Active Condition ................... 285
Figure 101. Update Event 1 Setup Diagram......................................................................................... 287
Figure 102. CHxE, CHxNE and CHxOM Updated by Update Event 2 ................................................. 288
Figure 103. Update Event 2 Setup Diagram......................................................................................... 288
Figure 104. Single Pulse Mode............................................................................................................. 289
Figure 105. Immediate Active Mode Minimum Delay ........................................................................... 290
Figure 106. Asymmetric PWM Mode versus Center-aligned Counting Mode....................................... 291
Figure 107. Pausing GPTM using the MCTM CH0OREF Signal.......................................................... 292
Figure 108. Triggering GPTM with MCTM Update Event 1 .................................................................. 293
Figure 109. Trigger MCTM and GPTM with the MCTM CH0 Input....................................................... 294
Figure 110. CH1XOR Input as Hall Sensor Interface............................................................................ 295
Figure 111. MCTM PDMA Mapping Diagram........................................................................................ 297
Figure 112. SCTM Block Diagram ........................................................................................................ 342
Figure 113. Up-counting Example......................................................................................................... 343
Figure 114. SCTM Clock Selection Source........................................................................................... 344
Figure 115. Trigger Control Block ......................................................................................................... 345
Figure 116. Slave Controller Diagram................................................................................................... 346
Figure 117. SCTM in Restart Mode ...................................................................................................... 346
Figure 118. SCTM in Pause Mode........................................................................................................ 347
Figure 119. SCTM in Trigger Mode....................................................................................................... 347
Figure 120. Capture/Compare Block Diagram...................................................................................... 348
Rev. 1.20 20 of 501 September 19, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52243/HT32F52253
List of Figures
Figure 121. Input Capture Mode........................................................................................................... 349
Figure 122. Channel Input Stages ........................................................................................................ 349
Figure 123. TI Digital Filter Diagram with N = 2.................................................................................... 350
Figure 124. Output Stage Block Diagram ............................................................................................. 350
Figure 125. Toggle Mode Channel Output Reference Signal (CHPRE = 0) ......................................... 351
Figure 126. Toggle Mode Channel Output Reference Signal (CHPRE = 1) ......................................... 352
Figure 127. PWM Mode Channel Output Reference Signal ................................................................. 352
Figure 128. Update Event Setting Diagram .......................................................................................... 353
Figure 129. RTC Block Diagram........................................................................................................... 370
Figure 130. Watchdog Timer Block Diagram ........................................................................................ 380
Figure 131. Watchdog Timer Behavior ................................................................................................. 382
Figure 132. I2C Module Block Diagram................................................................................................. 389
Figure 133. START and STOP Condition ............................................................................................ 391
Figure 134. Data Validity...................................................................................................................... 391
Figure 135. 7-bit Addressing Mode....................................................................................................... 392
Figure 136. 10-bit Addressing Write Transmit Mode............................................................................. 393
Figure 137. 10-bits Addressing Read Receive Mode .......................................................................... 393
Figure 138. I2C Bus Acknowledge ........................................................................................................ 394
Figure 139. Clock Synchronization during Arbitration........................................................................... 394
Figure 140. Two Master Arbitration Procedure ..................................................................................... 395
Figure 141. Master Transmitter Timing Diagram .................................................................................. 397
Figure 142. Master Receiver Timing Diagram ...................................................................................... 398
Figure 143. Slave Transmitter Timing Diagram .................................................................................... 399
Figure 144. Slave Receiver Timing Diagram ........................................................................................ 400
Figure 145. SCL Timing Diagram.......................................................................................................... 412
Figure 146. SPI Block Diagram ............................................................................................................ 418
Figure 147. SPI Single Byte Transfer Timing Diagram – CPOL = 0, CPHA = 0.................................... 420
Figure 148. SPI Continuous Data Transfer Timing Diagram – CPOL = 0, CPHA = 0........................... 421
Figure 149. SPI Single Byte Transfer Timing Diagram – CPOL = 0, CPHA = 1.................................... 421
Figure 150. SPI Continuous Transfer Timing Diagram – CPOL = 0, CPHA = 1.................................... 422
Figure 151. SPI Single Byte Transfer Timing Diagram – CPOL = 1, CPHA = 0.................................... 422
Figure 152. SPI Continuous Transfer Timing Diagram – CPOL = 1, CPHA = 0.................................... 423
Figure 153. SPI Single Byte Transfer Timing Diagram – CPOL = 1, CPHA = 1.................................... 423
Figure 154. SPI Continuous Transfer Timing Diagram – CPOL = 1, CPHA = 1.................................... 424
Figure 155. SPI Multi-Master Slave Environment................................................................................. 425
Figure 156. USART Block Diagram ...................................................................................................... 439
Figure 157. USART Serial Data Format ............................................................................................... 441
Figure 158. USART Clock CK_USART and Data Frame Timing.......................................................... 442
Figure 159. Hardware Flow Control between 2 USARTs...................................................................... 443
Figure 160. USART RTS Flow Control ................................................................................................. 444
Figure 161. USART CTS Flow Control ................................................................................................. 444
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