Epson S1C17F13 User manual

Rev. 1.0
CMOS 16-BIT SINGLE CHIP MICROCONTROLLER
S1C17F13
Technical Manual

©
SEIKO EPSON CORPORATION 2012, All rights reserved.
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko
Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability
of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and,
further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical prod-
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Devices
S1 C 17xxx F 00E1
Packing specifications
00 : Besides tape & reel
0A : TCP BL 2 directions
0B : Tape & reel BACK
0C : TCP BR 2 directions
0D : TCP BT 2 directions
0E : TCP BD 2 directions
0F : Tape & reel FRONT
0G: TCP BT 4 directions
0H : TCP BD 4 directions
0J : TCP SL 2 directions
0K : TCP SR 2 directions
0L : Tape & reel LEFT
0M: TCP ST 2 directions
0N : TCP SD 2 directions
0P : TCP ST 4 directions
0Q: TCP SD 4 directions
0R : Tape & reel RIGHT
99 : Specs not fixed
Specification
Package
D: die form; F: QFP, B: BGA, WCSP
Model number
Model name
C: microcomputer, digital products
Product classification
S1: semiconductor
Development tools
S5U1 C 17000 H2 1
Packing specifications
00: standard packing
Version
1: Version 1
Tool type
Hx : ICE
Dx : Evaluation board
Ex : ROM emulation board
Mx: Emulation memory for external ROM
Tx : A socket for mounting
Cx : Compiler package
Sx : Middleware package
Yx : Writer software
Corresponding model number
17xxx: for S1C17xxx
Tool classification
C: microcomputer use
Product classification
S5U1: development tool for semiconductor products
00
00
Configuration of product number
CONFIGURATION OF PRODUCT NUMBER
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation i
(Rev. 1.0)
Configuration of product number

PREFACE
ii Seiko Epson Corporation S1C17F13 TECHNICAL MANUAL
(Rev. 1.0)
Preface
This is a technical manual for designers and programmers who develop a product using the S1C17F13. This
document describes the functions of the IC, embedded peripheral circuit operations, and their control methods.
For the CPU functions and instructions, refer to the “S1C17 Family S1C17 Core Manual.” For the functions
and operations of the debugging tools, refer to the respective tool manuals. (Our “Products: Document Down-
loads” website provides the downloadable manuals.)
Notational conventions and symbols in this manual
Register address
Peripheral circuit chapters do not provide control register addresses. Refer to “Peripheral Circuit Area” in
the “Memory and Bus” chapter or “List of Peripheral Circuit Control Registers” in the Appendix.
Register and control bit names
In this manual, the register and control bit names are described as shown below to distinguish from signal
and pin names.
XXX register: Represents a register including its all bits.
XXX.YYY bit: Represents the one control bit YYY in the XXX register.
XXX.ZZZ[1:0] bits: Represents the two control bits ZZZ1 and ZZZ0 in the XXX register.
Register table contents and symbols
Initial: Value set at initialization
Reset: Initialization condition. The initialization condition depends on the reset group (H0, H1, or S0).
For more information on the reset groups, refer to “Initialization Conditions (Reset Groups)” in the
“Power Supply, Reset, and Clocks” chapter.
R/W: R = Read only bit
W = Write only bit
WP = Write only bit with a write protection using the MSCPROT.PROT[15:0] bits
R/W = Read/write bit
R/WP = Read/write bit with a write protection using the MSCPROT.PROT[15:0] bits
Control bit read/write values
This manual describes control bit values in a hexadecimal notation except for one-bit values (and except
when decimal or binary notation is required in terms of explanation). The values are described as shown
below according to the control bit width.
1 bit: 0 or 1
2 to 4 bits: 0x0 to 0xf
5 to 8 bits: 0x00 to 0xff
9 to 12 bits: 0x000 to 0xfff
13 to 16 bits: 0x0000 to 0xffff
Decimal: 0 to 9999...
Binary: 0b0000... to 0b1111...
Channel number
Multiple channels may be implemented in some peripheral circuits (e.g., 16-bit timer, etc.). The peripheral
circuit chapters use ‘n’ as the value that represents the channel number in the register and pin names regard-
less of the number of channel actually implemented. Normally, the descriptions are applied to all channels.
If there is a channel that has different functions from others, the channel number is specified clearly.
Example) T16_nCTL register of the 16-bit timer
If one channel is implemented (Ch.0 only): T16_nCTL = T16_0CTL only
If two channels are implemented (Ch.0 and Ch.1): T16_nCTL = T16_0CTL and T16_1CTL
For the number of channels implemented in the peripheral circuits of this IC, refer to “Features” in the
“Overview” chapter.

CONTENTS
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation iii
(Rev. 1.0)
– Contents –
Configuration of product number..............................................................................................i
Preface..................................................................................................................................... ii
Notational conventions and symbols in this manual ............................................................... ii
1 Overview........................................................................................................................1-1
1.1 Features .......................................................................................................................... 1-1
1.2 Block Diagram................................................................................................................. 1-3
1.3 Pins ................................................................................................................................. 1-4
1.3.1 Pin Configuration Diagram (TQFP13-64pin) ..................................................... 1-4
1.3.2 Pad Configuration Diagram (Chip).................................................................... 1-5
1.3.3 Pin Descriptions................................................................................................ 1-6
2 Power Supply, Reset, and Clocks ...............................................................................2-1
2.1 Power Generator (PWG).................................................................................................. 2-1
2.1.1 Overview ........................................................................................................... 2-1
2.1.2 Pins................................................................................................................... 2-2
2.1.3 VD1 Regulator.................................................................................................... 2-2
2.1.4 VOSC Regulator.................................................................................................. 2-2
2.1.5 Flash Programming Power Supply (VPP)........................................................... 2-2
2.2 System Reset Controller (SRC)....................................................................................... 2-2
2.2.1 Overview ........................................................................................................... 2-2
2.2.2 Input Pin............................................................................................................ 2-3
2.2.3 Reset Sources .................................................................................................. 2-3
2.2.4 Initialization Conditions (Reset Groups)............................................................ 2-4
2.3 Clock Generator (CLG).................................................................................................... 2-5
2.3.1 Overview ........................................................................................................... 2-5
2.3.2 Input/Output Pins ............................................................................................. 2-6
2.3.3 Clock Sources .................................................................................................. 2-6
2.3.4 Operations ........................................................................................................ 2-8
2.4 Operating Mode ............................................................................................................. 2-11
2.4.1 Initial Boot Sequence....................................................................................... 2-11
2.4.2 Transition between Operating Modes.............................................................. 2-11
2.5 Interrupts........................................................................................................................ 2-12
2.6 Control Registers ........................................................................................................... 2-13
PWG VD1 Regulator Control Register ....................................................................................... 2-13
CLG System Clock Control Register........................................................................................ 2-13
CLG Oscillation Control Register ............................................................................................. 2-14
CLG OSC3B Control Register.................................................................................................. 2-15
CLG OSC1 Control Register .................................................................................................... 2-15
CLG OSC3A Control Register .................................................................................................. 2-16
CLG Interrupt Flag Register ..................................................................................................... 2-16
CLG Interrupt Enable Register ................................................................................................. 2-17
CLG FOUT Control Register..................................................................................................... 2-17
3 CPU and Debugger ......................................................................................................3-1
3.1 Overview ......................................................................................................................... 3-1
3.2 CPU Core........................................................................................................................ 3-2
3.2.1 CPU Registers .................................................................................................. 3-2
3.2.2 Instruction Set .................................................................................................. 3-2
3.2.3 Reading PSR .................................................................................................... 3-2
3.2.4 I/O Area Reserved for the S1C17 Core ............................................................ 3-2

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3.3 Debugger ........................................................................................................................ 3-2
3.3.1 Debugging Functions........................................................................................ 3-2
3.3.2 Resource Requirements and Debugging Tools ................................................ 3-2
3.3.3 List of debugger input/output pins ................................................................... 3-3
3.3.4 External Connection ......................................................................................... 3-3
3.4 Control Register .............................................................................................................. 3-3
MISC PSR Register ................................................................................................................... 3-3
Debug RAM Base Register ....................................................................................................... 3-4
4 Memory and Bus ..........................................................................................................4-1
4.1 Overview ......................................................................................................................... 4-1
4.2 Bus Access Cycle ........................................................................................................... 4-1
4.3 Flash Memory ................................................................................................................. 4-2
4.3.1 Flash Bus Access Cycle Setting....................................................................... 4-2
4.3.2 Flash Programming........................................................................................... 4-2
4.3.3 Flash Security Function .................................................................................... 4-3
4.4 RAM1 .............................................................................................................................. 4-3
4.5 RAM2 .............................................................................................................................. 4-3
4.6 Peripheral Circuit Control Registers................................................................................ 4-3
4.6.1 System-Protect Function.................................................................................. 4-7
4.7 Control Registers ............................................................................................................ 4-7
MISC System Protect Register ................................................................................................. 4-7
MISC IRAM Size Register.......................................................................................................... 4-7
FLASHC Flash Read Cycle Register ......................................................................................... 4-8
5 Interrupt Controller (ITC) .............................................................................................5-1
5.1 Overview ......................................................................................................................... 5-1
5.2 Vector Table .................................................................................................................... 5-1
5.2.1 Vector Table Base Address (TTBR)................................................................... 5-3
5.3 Initialization ..................................................................................................................... 5-3
5.4 Maskable Interrupt Control and Operations ................................................................... 5-3
5.4.1 Peripheral Circuit Interrupt Control................................................................... 5-3
5.4.2 ITC Interrupt Request Processing .................................................................... 5-4
5.4.3 Conditions to Accept Interrupt Requests by the CPU...................................... 5-4
5.5 NMI.................................................................................................................................. 5-4
5.6 Software Interrupts ......................................................................................................... 5-4
5.7 Interrupt Processing by the CPU .................................................................................... 5-5
5.8 Control Registers ............................................................................................................ 5-5
MISC Vector Table Address Low Register ................................................................................ 5-5
MISC Vector Table Address High Register................................................................................ 5-5
ITC Interrupt Level Setup Register x......................................................................................... 5-5
6 I/O Ports (PPORT).........................................................................................................6-1
6.1 Overview ......................................................................................................................... 6-1
6.2 I/O Cell Structure and Functions..................................................................................... 6-2
6.2.1 Schmitt Input .................................................................................................... 6-2
6.2.2 Over Voltage Tolerant Fail-Safe Type I/O Cell................................................... 6-2
6.2.3 Pull-Up/Pull-Down ............................................................................................ 6-2
6.2.4 CMOS Output and High Impedance State....................................................... 6-3
6.3 Clock Settings................................................................................................................. 6-3
6.3.1 PPORT Operating Clock................................................................................... 6-3
6.3.2 Clock Supply in SLEEP Mode .......................................................................... 6-3
6.3.3 Clock Supply in DEBUG Mode......................................................................... 6-3

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6.4 Operations ...................................................................................................................... 6-3
6.4.1 Initialization ....................................................................................................... 6-3
6.4.2 Port Input/Output Control................................................................................. 6-5
6.5 Interrupts......................................................................................................................... 6-6
6.6 Control Registers ............................................................................................................ 6-6
PxPort Data Register................................................................................................................ 6-6
PxPort Enable Register ............................................................................................................ 6-7
PxPort Pull-up/down Control Register..................................................................................... 6-7
PxPort Interrupt Flag Register.................................................................................................. 6-8
PxPort Interrupt Control Register............................................................................................. 6-8
PxPort Chattering Filter Enable Register.................................................................................. 6-8
PxPort Mode Select Register ................................................................................................... 6-8
PxPort Function Select Register .............................................................................................. 6-9
P Port Clock Control Register ................................................................................................... 6-9
P Port Interrupt Flag Group Register........................................................................................ 6-10
6.7 Control Register and Port Function Configuration of this IC ......................................... 6-11
6.7.1 P0 Port Group.................................................................................................. 6-11
6.7.2 P1 Port Group.................................................................................................. 6-12
6.7.3 P2 Port Group.................................................................................................. 6-12
6.7.4 P3 Port Group.................................................................................................. 6-13
6.7.5 P4 Port Group.................................................................................................. 6-14
6.7.6 Pd Port Group.................................................................................................. 6-15
6.7.7 Common Registers between Port Groups....................................................... 6-15
7 Watchdog Timer (WDT)................................................................................................7-1
7.1 Overview ......................................................................................................................... 7-1
7.2 Clock Settings................................................................................................................. 7-1
7.2.1 WDT Operating Clock....................................................................................... 7-1
7.2.2 Clock Supply in DEBUG Mode......................................................................... 7-2
7.3 Operations ...................................................................................................................... 7-2
7.3.1 WDT Control ..................................................................................................... 7-2
7.3.2 Operations in HALT and SLEEP Modes............................................................ 7-2
7.4 Control Registers ............................................................................................................ 7-3
WDT Clock Control Register ..................................................................................................... 7-3
WDT Control Register ............................................................................................................... 7-3
8 Supply Voltage Detector (SVD)....................................................................................8-1
8.1 Overview ......................................................................................................................... 8-1
8.2 Input Pin and External Connection ................................................................................. 8-2
8.2.1 Input Pin............................................................................................................ 8-2
8.2.2 External Connection ......................................................................................... 8-2
8.3 Clock Settings................................................................................................................. 8-2
8.3.1 SVD Operating Clock........................................................................................ 8-2
8.3.2 Clock Supply in SLEEP Mode .......................................................................... 8-2
8.3.3 Clock Supply in DEBUG Mode......................................................................... 8-3
8.4 Operations ...................................................................................................................... 8-3
8.4.1 SVD Control ...................................................................................................... 8-3
8.4.2 SVD Operations ................................................................................................ 8-4
8.5 SVD Interrupt and Reset ................................................................................................. 8-4
8.5.1 SVD Interrupt .................................................................................................... 8-4
8.5.2 SVD Reset......................................................................................................... 8-5
8.6 Control Registers ............................................................................................................ 8-5
SVD Clock Control Register ...................................................................................................... 8-5
SVD Control Register ................................................................................................................ 8-6

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SVD Status and Interrupt Flag Register .................................................................................... 8-7
SVD Interrupt Enable Register .................................................................................................. 8-8
9 16-bit Timers (T16)........................................................................................................9-1
9.1 Overview ......................................................................................................................... 9-1
9.2 Input Pin.......................................................................................................................... 9-1
9.3 Clock Settings................................................................................................................. 9-2
9.3.1 T16 Operating Clock......................................................................................... 9-2
9.3.2 Clock Supply in SLEEP Mode .......................................................................... 9-2
9.3.3 Clock Supply in DEBUG Mode......................................................................... 9-2
9.3.4 Event Counter Clock......................................................................................... 9-2
9.4 Operations ...................................................................................................................... 9-2
9.4.1 Initialization ....................................................................................................... 9-2
9.4.2 Counter Underflow ........................................................................................... 9-3
9.4.3 Operations in Repeat Mode.............................................................................. 9-3
9.4.4 Operations in One-shot Mode .......................................................................... 9-3
9.4.5 Counter Value Read.......................................................................................... 9-4
9.5 Interrupt........................................................................................................................... 9-4
9.6 Control Registers ............................................................................................................ 9-4
T16 Ch.nClock Control Register .............................................................................................. 9-4
T16 Ch.nMode Register ........................................................................................................... 9-5
T16 Ch.nControl Register......................................................................................................... 9-5
T16 Ch.nReload Data Register................................................................................................. 9-6
T16 Ch.nCounter Data Register ............................................................................................... 9-6
T16 Ch.nInterrupt Flag Register ............................................................................................... 9-6
T16 Ch.nInterrupt Enable Register........................................................................................... 9-7
10 UART (UART)..............................................................................................................10-1
10.1 Overview ...................................................................................................................... 10-1
10.2 Input/Output Pins and External Connections .............................................................. 10-2
10.2.1 List of Input/Output Pins................................................................................ 10-2
10.2.2 External Connections .................................................................................... 10-2
10.2.3 Input Pin Pull-Up Function............................................................................. 10-2
10.2.4 Output Pin Open-Drain Output Function ...................................................... 10-2
10.3 Clock Settings.............................................................................................................. 10-2
10.3.1 UART Operating Clock .................................................................................. 10-2
10.3.2 Clock Supply in SLEEP Mode ....................................................................... 10-2
10.3.3 Clock Supply in DEBUG Mode...................................................................... 10-3
10.3.4 Baud Rate Generator..................................................................................... 10-3
10.4 Data Format ................................................................................................................. 10-3
10.5 Operations ................................................................................................................... 10-4
10.5.1 Initialization .................................................................................................... 10-4
10.5.2 Data Transmission ......................................................................................... 10-4
10.5.3 Data Reception .............................................................................................. 10-5
10.5.4 IrDA Interface................................................................................................. 10-6
10.6 Receive Errors.............................................................................................................. 10-7
10.6.1 Framing Error ................................................................................................. 10-7
10.6.2 Parity Error..................................................................................................... 10-8
10.6.3 Overrun Error ................................................................................................. 10-8
10.7 Interrupts...................................................................................................................... 10-8
10.8 Control Registers ......................................................................................................... 10-8
UART Ch.nClock Control Register .......................................................................................... 10-8
UART Ch.nMode Register....................................................................................................... 10-9
UART Ch.nBaud–Rate Register ............................................................................................. 10-10

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UART Ch.nControl Register ................................................................................................... 10-10
UART Ch.nTransmit Data Register ......................................................................................... 10-11
UART Ch.nReceive Data Register.......................................................................................... 10-11
UART Ch.nStatus and Interrupt Flag Register ....................................................................... 10-11
UART Ch.nInterrupt Enable Register...................................................................................... 10-12
11 Synchronous Serial Interface (SPI) ..........................................................................11-1
11.1 Overview ...................................................................................................................... 11-1
11.2 Input/Output Pins and External Connections .............................................................. 11-2
11.2.1 List of Input/Output Pins................................................................................ 11-2
11.2.2 External Connections .................................................................................... 11-2
11.2.3 Pin Functions in Master Mode and Slave Mode............................................ 11-3
11.2.4 Input Pin Pull-Up/Pull-Down Function .......................................................... 11-3
11.3 Clock Settings.............................................................................................................. 11-3
11.3.1 SPI Operating Clock ...................................................................................... 11-3
11.3.2 Clock Supply in DEBUG Mode...................................................................... 11-4
11.3.3 SPI Clock (SPICLKn) Phase and Polarity ...................................................... 11-4
11.4 Data Format ................................................................................................................. 11-5
11.5 Operations ................................................................................................................... 11-5
11.5.1 Initialization .................................................................................................... 11-5
11.5.2 Data Transmission in Master Mode ............................................................... 11-5
11.5.3 Data Reception in Master Mode.................................................................... 11-7
11.5.4 Terminating Data Transfer in Master Mode.................................................... 11-8
11.5.5 Data Transfer in Slave Mode.......................................................................... 11-8
11.5.6 Terminating Data Transfer in Slave Mode ..................................................... 11-10
11.6 Interrupts..................................................................................................................... 11-10
11.7 Control Registers ........................................................................................................ 11-11
SPI Ch.nMode Register.......................................................................................................... 11-11
SPI Ch.nControl Register ....................................................................................................... 11-11
SPI Ch.nTransmit Data Register............................................................................................. 11-12
SPI Ch.nReceive Data Register.............................................................................................. 11-12
SPI Ch.nInterrupt Flag Register ............................................................................................. 11-12
SPI Ch.nInterrupt Enable Register ......................................................................................... 11-13
12 I2C (I2C).......................................................................................................................12-1
12.1 Overview ...................................................................................................................... 12-1
12.2 Input/Output Pins and External Connections .............................................................. 12-2
12.2.1 List of Input/Output Pins................................................................................ 12-2
12.2.2 External Connections .................................................................................... 12-2
12.3 Clock Settings.............................................................................................................. 12-3
12.3.1 I2C Operating Clock ...................................................................................... 12-3
12.3.2 Clock Supply in DEBUG Mode...................................................................... 12-3
12.3.3 Baud Rate Generator..................................................................................... 12-3
12.4 Operations ................................................................................................................... 12-4
12.4.1 Initialization .................................................................................................... 12-4
12.4.2 Data Transmission in Master Mode ............................................................... 12-5
12.4.3 Data Reception in Master Mode.................................................................... 12-7
12.4.4 10-bit Addressing in Master Mode ................................................................ 12-9
12.4.5 Data Transmission in Slave Mode................................................................. 12-10
12.4.6 Data Reception in Slave Mode ..................................................................... 12-12
12.4.7 Slave Operations in 10-bit Address Mode.................................................... 12-14
12.4.8 Automatic Bus Clearing Operation............................................................... 12-14
12.4.9 Error Detection.............................................................................................. 12-15
12.5 Interrupts..................................................................................................................... 12-16

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12.6 Control Registers ........................................................................................................ 12-17
I2C Ch.nClock Control Register............................................................................................. 12-17
I2C Ch.nMode Register.......................................................................................................... 12-18
I2C Ch.nBaud-Rate Register.................................................................................................. 12-18
I2C Ch.nOwn Address Register ............................................................................................. 12-18
I2C Ch.nControl Register ....................................................................................................... 12-19
I2C Ch.nTransmit Data Register............................................................................................. 12-20
I2C Ch.nReceive Data Register.............................................................................................. 12-20
I2C Ch.nStatus and Interrupt Flag Register ........................................................................... 12-20
I2C Ch.nInterrupt Enable Register ......................................................................................... 12-21
13 Clock Timer (CT)........................................................................................................13-1
13.1 Overview ...................................................................................................................... 13-1
13.2 Clock Settings.............................................................................................................. 13-1
13.3 Operations ................................................................................................................... 13-1
13.4 Interrupts...................................................................................................................... 13-2
13.5 Control Registers ......................................................................................................... 13-3
CT Control Register.................................................................................................................. 13-3
CT Counter Data Register ........................................................................................................ 13-3
CT Interrupt Flag Register ........................................................................................................ 13-4
CT Interrupt Enable Register.................................................................................................... 13-4
14 Real-Time Clock (RTC)..............................................................................................14-1
14.1 Overview ...................................................................................................................... 14-1
14.2 Clock Settings.............................................................................................................. 14-1
14.3 RTC Counters .............................................................................................................. 14-1
14.4 Operations ................................................................................................................... 14-3
14.4.1 Time Setting................................................................................................... 14-3
14.4.2 Time Read...................................................................................................... 14-4
14.5 Interrupts...................................................................................................................... 14-4
14.6 Control Registers ......................................................................................................... 14-5
RTC Control Register ............................................................................................................... 14-5
RTC Interrupt Enable Register ................................................................................................. 14-6
RTC Interrupt Flag Register...................................................................................................... 14-6
RTC Minute/Second Register................................................................................................... 14-7
RTC Hour Register ................................................................................................................... 14-7
15 Theoretical Regulation (TR)......................................................................................15-1
15.1 Overview ...................................................................................................................... 15-1
15.2 Output Pin .................................................................................................................... 15-1
15.3 Operations ................................................................................................................... 15-1
15.3.1 Executing Theoretical Regulation .................................................................. 15-1
15.3.2 Regulated Clock External Monitor................................................................. 15-3
15.4 Control Register ........................................................................................................... 15-3
Theoretical Regulation Control Register .................................................................................. 15-3
16 16-bit PWM Timers (T16A3) ......................................................................................16-1
16.1 Overview ...................................................................................................................... 16-1
16.2 Input/Output Pins......................................................................................................... 16-2
16.3 Clock Settings.............................................................................................................. 16-2
16.3.1 T16A3 Operating Clock ................................................................................. 16-2
16.3.2 Clock Supply in SLEEP Mode ....................................................................... 16-3
16.3.3 Clock Supply in DEBUG Mode...................................................................... 16-3
16.3.4 Event Counter Clock...................................................................................... 16-3

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16.4 Operations ................................................................................................................... 16-3
16.4.1 Initialization .................................................................................................... 16-3
16.4.2 Counter Block Operations ............................................................................. 16-4
16.4.3 Comparator/Capture Block Operations......................................................... 16-5
16.4.4 TOUT Output Control .................................................................................... 16-9
16.5 Interrupt....................................................................................................................... 16-11
16.6 Control Registers ........................................................................................................ 16-11
T16A3 Ch.nClock Control Register ........................................................................................ 16-11
T16A3 Counter Ch.nControl Register .................................................................................... 16-12
T16A3 Counter Ch.nData Register......................................................................................... 16-13
T16A3 Comparator/Capture Ch.nControl Register ................................................................ 16-14
T16A3 Comparator/Capture Ch.nA Data Register................................................................. 16-15
T16A3 Comparator/Capture Ch.nB Data Register................................................................. 16-15
T16A3 Ch.nInterrupt Flag Register......................................................................................... 16-16
T16A3 Ch.nInterrupt Enable Register..................................................................................... 16-16
17 Parallel Interface (PIO) ..............................................................................................17-1
17.1 Overview ...................................................................................................................... 17-1
17.2 Input/Output Pins and External Connections .............................................................. 17-1
17.2.1 List of Input/Output Pins................................................................................ 17-1
17.2.2 External Connections .................................................................................... 17-2
17.2.3 Pin Pull-Up Function...................................................................................... 17-2
17.3 Clock Settings.............................................................................................................. 17-2
17.3.1 PIO Operating Clock...................................................................................... 17-2
17.3.2 Clock Supply in SLEEP Mode ....................................................................... 17-2
17.3.3 Clock Supply in DEBUG Mode...................................................................... 17-2
17.4 Operations ................................................................................................................... 17-2
17.4.1 Initialization .................................................................................................... 17-2
17.4.2 Operations in SRAM Mode............................................................................ 17-3
17.4.3 Operations in GPIO Mode ............................................................................. 17-4
17.5 Control Registers ......................................................................................................... 17-5
PIO Clock Control Register ...................................................................................................... 17-5
PIO Mode Register................................................................................................................... 17-5
PIO Control Register ................................................................................................................ 17-6
PIO Address/Write Data Register............................................................................................. 17-6
PIO Read Data Register ........................................................................................................... 17-6
PIO Status Register.................................................................................................................. 17-7
18 EPD Timing Controller (EPD Tcon)...........................................................................18-1
18.1 Overview ...................................................................................................................... 18-1
18.2 Interrupt........................................................................................................................ 18-1
18.3 Control Registers ......................................................................................................... 18-2
EPD Tcon Control Register....................................................................................................... 18-2
EPD Tcon Interrupt Flag and Status Register........................................................................... 18-2
EPD Tcon Interrupt Enable Register......................................................................................... 18-2
19 R/F Converter (RFC)..................................................................................................19-1
19.1 Overview ...................................................................................................................... 19-1
19.2 Input/Output Pins and External Connections .............................................................. 19-2
19.2.1 List of Input/Output Pins................................................................................ 19-2
19.2.2 External Connections .................................................................................... 19-2
19.3 Clock Settings.............................................................................................................. 19-3
19.3.1 RFC Operating Clock..................................................................................... 19-3
19.3.2 Clock Supply in SLEEP Mode ....................................................................... 19-3
19.3.3 Clock Supply in DEBUG Mode...................................................................... 19-3

CONTENTS
xSeiko Epson Corporation S1C17F13 TECHNICAL MANUAL
(Rev. 1.0)
19.4 Operations ................................................................................................................... 19-3
19.4.1 Initialization .................................................................................................... 19-3
19.4.2 Operating Modes........................................................................................... 19-4
19.4.3 RFC Counters ................................................................................................ 19-4
19.4.4 Converting Operations and Control Procedure ............................................. 19-5
19.4.5 CR Oscillation Frequency Monitoring Function............................................. 19-7
19.5 Interrupts...................................................................................................................... 19-7
19.6 Control Registers ......................................................................................................... 19-8
RFC Ch.nClock Control Register ............................................................................................ 19-8
RFC Ch.nControl Register....................................................................................................... 19-8
RFC Ch.nOscillation Trigger Register...................................................................................... 19-9
RFC Ch.nMeasurement Counter Low and High Registers .................................................... 19-10
RFC Ch.nTime Base Counter Low and High Registers ......................................................... 19-10
RFC Ch.nInterrupt Flag Register............................................................................................ 19-11
RFC Ch.nInterrupt Enable Register........................................................................................ 19-11
20 Temperature Detection Circuit (TEM)......................................................................20-1
20.1 Overview ...................................................................................................................... 20-1
20.2 Clock Settings.............................................................................................................. 20-2
20.2.1 TEM Operating Clock .................................................................................... 20-2
20.2.2 Clock Supply in SLEEP Mode ....................................................................... 20-2
20.2.3 Clock Supply in DEBUG Mode...................................................................... 20-2
20.3 Operations ................................................................................................................... 20-2
20.3.1 Initialization .................................................................................................... 20-2
20.3.2 Comparison Time Setting.............................................................................. 20-2
20.3.3 Temperature Detection ................................................................................. 20-3
20.4 Interrupt........................................................................................................................ 20-5
20.5 Control Registers ......................................................................................................... 20-5
TEM Clock Control Register..................................................................................................... 20-5
TEM Timing Register ................................................................................................................ 20-5
TEM Control Register............................................................................................................... 20-6
TEM Conversion Result Register ............................................................................................. 20-6
TEM Interrupt Flag and Status Register................................................................................... 20-6
TEM Interrupt Enable Register ................................................................................................. 20-7
21 Multiplier/Divider (COPRO).......................................................................................21-1
21.1 Overview ...................................................................................................................... 21-1
21.2 Operation Mode and Output Mode.............................................................................. 21-1
21.3 Multiplication................................................................................................................ 21-2
21.4 Division......................................................................................................................... 21-3
21.5 MAC ............................................................................................................................. 21-4
21.6 Reading Operation Results .......................................................................................... 21-6
22 Electrical Characteristics .........................................................................................22-1
22.1 Absolute Maximum Ratings ......................................................................................... 22-1
22.2 Recommended Operating Conditions ......................................................................... 22-1
22.3 Current Consumption................................................................................................... 22-2
22.4 System Reset Controller (SRC) Characteristics........................................................... 22-4
22.5 Clock Generator (CLG) Characteristics........................................................................ 22-5
22.6 Flash Memory Characteristics ..................................................................................... 22-6
22.7 Input/Output Port (PPORT) Characteristics ................................................................. 22-7
22.8 Supply Voltage Detector (SVD) Characteristics ........................................................... 22-8
22.9 UART (UART) Characteristics ...................................................................................... 22-9
22.10 Synchronous Serial Interface (SPIA) Characteristics ................................................. 22-9

CONTENTS
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation xi
(Rev. 1.0)
22.11 I2C (I2C) Characteristics............................................................................................ 22-10
22.12 Parallel Interface (PIO) Characteristics ..................................................................... 22-10
22.13 EPD Timing Controller (EPD Tcon) Characteristics................................................... 22-11
22.14 R/F Converter (RFC) Characteristics......................................................................... 22-11
22.15 Temperature Detection Circuit Characteristics ......................................................... 22-12
23 Basic External Connection Diagram .......................................................................23-1
24 Package......................................................................................................................24-1
Appendix A List of Peripheral Circuit Control Registers ......................................... AP-A-1
0x4000–0x4008 Misc Registers (MISC) ........................................................... AP-A-1
0x4020 Power Generator (PWG) ........................................................ AP-A-1
0x4040–0x404e Clock Generator (CLG) .......................................................... AP-A-1
0x4052 Theoretical Regulation (TR).................................................... AP-A-2
0x4080–0x4092 Interrupt Controller (ITC) ........................................................ AP-A-2
0x40a0–0x40a2 Watchdog Timer (WDT).......................................................... AP-A-3
0x40c0–0x40c8 Real-time Clock (RTC) ........................................................... AP-A-4
0x4100–0x4106 Supply Voltage Detector (SVD) .............................................. AP-A-4
0x4160–0x416c 16-bit Timer (T16) Ch.0.......................................................... AP-A-5
0x41b0 Flash Controller (FLASHC)..................................................... AP-A-5
0x4200–0x42e2 I/O Ports (PPORT).................................................................. AP-A-5
0x4380–0x438e UART (UART) ......................................................................... AP-A-8
0x43a0–0x43ac 16-bit Timer (T16) Ch.1.......................................................... AP-A-9
0x43b0–0x43ba SPI (SPI) Ch.0 ....................................................................... AP-A-10
0x43c0–0x43d2 I2C (I2C)................................................................................. AP-A-10
0x5000–0x500e 16-bit PWM Timer (T16A3) Ch.0........................................... AP-A-11
0x5020–0x502e 16-bit PWM Timer (T16A3) Ch.1........................................... AP-A-12
0x5180–0x5186 Clock Timer (CT) ................................................................... AP-A-13
0x5260–0x526c 16-bit Timer (T16) Ch.2......................................................... AP-A-14
0x5270–0x527a SPI (SPI) Ch.1 ....................................................................... AP-A-14
0x5280–0x528c 16-bit Timer (T16) Ch.3......................................................... AP-A-15
0x5290–0x529a SPI (SPI) Ch.2 ....................................................................... AP-A-15
0x52e0–0x52ea Parallel Interface (PIO) .......................................................... AP-A-16
0x5380–0x5384 EPD Timing Controller (EPD Tcon)........................................ AP-A-16
0x5440–0x5450 R/F Converter (RFC) Ch.0..................................................... AP-A-17
0x5460–0x5470 R/F Converter (RFC) Ch.1..................................................... AP-A-18
0x54c0–0x54ca Temperature Detection Circuit (TEM).................................... AP-A-19
0xffff90 Debugger (DBG) ................................................................... AP-A-19
Appendix B Power Saving .......................................................................................... AP-B-1
B.1 Operating Status Configuration Examples for Power Saving...................................... AP-B-1
B.2 Other Power Saving Methods ..................................................................................... AP-B-2
Appendix C Mounting Precautions............................................................................ AP-C-1
Appendix D Measures Against Noise ........................................................................ AP-D-1
Appendix E Initialization Routine ............................................................................... AP-E-1
Revision History

1 OVERVIEW
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation 1-1
(Rev. 1.0)
Overview1
The S1C17F13 is an ultra low-power MCU equipped with a display memory and an EPD timing controller to send
display data for using the active EPD panels. This IC includes the synchronous serial interface, parallel interface,
UART, and I2C to communicate with an EPD panel and other devices. This IC allows measurement of various envi-
ronmental conditions such as a temperature and humidity measurement using the R/F converter, and a supply volt-
age measurement using the supply voltage detector and brownout reset circuits.
Features1.1
1.1 FeaturesTable 1.
Model S1C17F13
CPU
CPU core Seiko Epson original 16-bit RISC CPU core S1C17
Multiplier/Divider (COPRO) 16-bit ×16-bit multiplier
16-bit ×16-bit + 32-bit multiply and accumulation unit
16-bit ÷16-bit divider
Other On-chip debugger
Embedded Flash memory
Capacity 128K bytes (for both instructions and data) *1
Erase/program count 50 times (min.) *Programming by the debugging tool ICDmini
Other Security function to protect from reading/programming by ICDmini
On-board programming function using ICDmini
Embedded Flash voltage booster to generate the Flash erasing/programming voltage
Embedded RAM
Capacity 6K bytes (area accessed by CPU only)
14K bytes (area accessed by CPU and EPD Tcon)
Clock generator (CLG)
System clock source 5 sources (OSC3B, OSC3A, OSC1B, OSC1A, and EXOSC)
System clock frequency (operating frequency) 20 MHz (max.)
OSC3B internal high-speed oscillator circuit
(boot clock source)
20/16/12/8 MHz (typ.) selectable via software
OSC1B internal low-speed oscillator circuit 32 kHz (typ.)
OSC3A high-speed oscillator circuit 20 MHz (max.) crystal or ceramic oscillator circuit
OSC1A low-speed oscillator circuit 32.768 kHz (typ.) crystal oscillator circuit
EXOSC clock input 20 MHz (max.) square or sine wave input
Other Configurable system clock division ratio
Configurable system clock (except for OSC1A and OSC1B) used at wake up from
SLEEP state
Operating clock frequency for the CPU and all peripheral circuits is selectable.
I/O port (PPORT)
Number of
general-purpose I/O ports 37 bits (max.) (Pins are shared with the peripheral I/O.)
Number of input interrupt ports 8 bits
Other All pins contain a pull-up/down resistor that can be enabled/disabled via software.
16 bits contain an interrupt function and a chattering filter function.
Display control
EPD timing controller (EPD Tcon) Controls display on the active-matrix EPD via the embedded SPI or PIO.
Includes a display data read function from the embedded RAM (area for both CPU
and EPD Tcon).
Can be controlled with the dedicated API library.
Communication interfaces
UART (UART) 1 channel
IrDA1.0 supported
Embedded baud-rate generator
Synchronous serial interface (SPI) 3 channels
Configurable as the communication interface for EPD Tcon (SPI Ch.1)
I2C (I2C) 1 channel
Master and slave operations supported
Embedded baud-rate generator
Parallel interface (PIO) Address length: 8 bits (max.)
Data width: 8 bits (max.)
Control signals: #CE, #RD, #WR
Configurable as the communication interface for EPD Tcon

1 OVERVIEW
1-2 Seiko Epson Corporation S1C17F13 TECHNICAL MANUAL
(Rev. 1.0)
Timers
Watchdog timer (WDT) 1 channel
Generates NMI or watchdog timer reset.
16-bit timer (T16) 4 channels
Generates the SPI master clocks. (Ch.1 to Ch.3)
Clock timer (CT) 1 channel
128–1 Hz counter
Real-time clock (RTC) Hour, minute, and second counters
Theoretical regulation function (TR) Time adjustment function in -31/32,768 to +32/32,768 second units (applied to T16A3,
CT, and RTC clocks)
Supports correction value alteration according to temperature variations.
16-bit PWM timer (T16A3) 2 channels
PWM output, event counter, and count capture functions
Supply voltage detector (SVD)
Detection level 19 values (1.8 to 3.6 V)
Other Intermittent operation mode
Generates an interrupt or reset according to the detection level evaluation.
R/F converter (RFC)
Conversion method CR oscillation type with 24-bit counters
Number of conversion channels 2 channels (Up to four sensors can be connected.)
Supported sensors DC-bias resistive sensors and AC-bias resistive sensors
Temperature detection circuit (TEM)
Resolution/accuracy 1 °C steps, ±5 °C accuracy
Reset
#RESET pin Reset when the reset pin is set to low.
Power-on reset Reset at power-on.
Brownout reset Reset when brownout (VDD = 1.45 V typ.) is detected.
Key entry reset Reset when the P00 to P01/P02/P03 keys are pressed simultaneously (can be en-
abled/disabled using a register).
Watchdog timer reset Reset when the watchdog timer overflows (can be enabled/disabled using a register).
Supply voltage detector reset
Reset when the supply voltage detector detects the set voltage level (can be enabled/
disabled using a register).
Interrupt
Non-maskable interrupt 4 systems (Reset, address misaligned interrupt, debug, NMI)
Programmable interrupt External interrupt: 1 system (8 levels)
Internal interrupt: 19 systems (8 levels)
Power supply voltage
VDD operating voltage 2.0 to 3.6 V
Operating temperature
Operating temperature range -20 to 70 °C
Current consumption
SLEEP mode 0.35 µA
OSC1 = OFF, RTC = OFF, OSC3B = OFF, OSC3A = OFF
HALT mode 0.78 µA
OSC1 = 32 kHz (OSC1A), RTC = OFF, OSC3B = OFF, OSC3A = OFF
0.80 µA
OSC1 = 32 kHz (OSC1A), RTC = ON, OSC3B = OFF, OSC3A = OFF
RUN mode 11.9 µA
OSC1 = 32 kHz (OSC1A), RTC = OFF, OSC3B = OFF, OSC3A = OFF
5.43 mA
OSC1 = OFF, RTC = OFF, OSC3B = OFF, OSC3A = 20 MHz ceramic
5.50 mA
OSC1 = OFF, RTC = OFF, OSC3B = 20 MHz, OSC3A = OFF
Shipping form
1 TQFP13-64pin (Lead pitch: 0.5 mm)
2 Chip (Pad pitch: 90 µm)
*1
When using the EPD timing controller (EPD Tcon), an area for storing the timing parameters must be allocated in the Flash memory.
When using the internal Flash voltage booster as the Flash programing power supply, an area for storing the control program
must be allocated
in the Flash memory.

1 OVERVIEW
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation 1-3
(Rev. 1.0)
Block Diagram1.2
OSC3B
oscillator
OSC1B
oscillator
OSC1A
oscillator
EXOSC
input circuit
Clock generator
(CLG)
Power-on reset
(POR)
Brownout reset
(BOR)
Power generator
(PWG)
System reset controller
(SRC)
V
DD
V SS
V D1
V OSC
V PP
C 1N , C 1P , C 1H
C 2N , C 2P
IREF_M
FOUT
OSC1
OSC2
OSC3
OSC4
EXOSC
#RESET
OSC3A
oscillator
CPU core & debugger
(S1C17)
Internal RAM
6K bytes
System clock Interrupt request
Interrupt signal
DCLK
DSIO
DST2
32-bit RAM bus
Internal RAM
14K bytes
32-bit RAM bus
Instruction bus
16-bit internal bus
SDA0
SCL0
EXSVD
P00–07,
P10–17,
P20–27,
P30–37,
P40–41,
PD0–D2
Interrupt
controller
(ITC)
I/O port
(PPORT)
Watchdog timer
(WDT)
Clock timer
(CT)
Real-time clock
(RTC)
Theoretical
Regulation
(TR)
I
2
C
(I2C)
Temperature
detection circuit
(TEM)
R/F converter
(RFC)
Ch.0–1
Supply voltage
detector
(SVD)
16-bit timer
(T16)
Ch.0–3
EXCL0–1
TOUTA0/CAPA0–1
TOUTB0/CAPB0–1
SDI0, 2
SDO0, 2
SPICLK0, 2
#SPISS0, 2
RFIN0–1
REF0–1
SENA0–1
SENB0–1
RFCLKO0–1
VM1–2
Synchronous
serial interface
(SPI)
Ch.0, 2
SDI1
SDO1
SPICLK1
#SPISS1
REGMON
Synchro-
nous serial
interface
(SPI) Ch.1
PIOA[7:0]
PIOD[7:0]
#PIOCE
#PIORD
#PIOWR
Parallel
interface
(PIO)
16-bit PWM timer
(T16A3)
Ch.0–1
USIN0
USOUT0
UART
(UART)
EPD timing
controller
(EPD Tcon)
Flash memory
128K bytes
2.1 S1C17F13 Block DiagramFigure 1.

1 OVERVIEW
1-4 Seiko Epson Corporation S1C17F13 TECHNICAL MANUAL
(Rev. 1.0)
Pins1.3
Pin Configuration Diagram (TQFP13-64pin)1.3.1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P31 P32 P33
VDD
VSS
P34 P35 P36 P37 P40 P41
PD0 PD1 PD2
P00 P01
P31/REGMON/RFCLKO1/EXSVD
P32/TOUTB1/CAPB1/PIOA0 P33/TOUTA1/CAPA1/PIOA1
VDD
VSS
P34/USIN0/PIOA2
P35/USOUT0/PIOA3
P36/SCL0/PIOD0
P37/SDA0/PIOD1
P40/USIN0/PIOD2
P41/USOUT0/PIOD3
DST2/PD0
DSIO/PD1
DCLK/PD2
P00/TOUTA0/CAPA0/FOUT
P01/TOUTB0/CAPB0/#PIOWR
VSS
TEST P13 P12 P11 P10 IREF_M VOSC VM1 VM2 OSC2 OSC1 OSC4 OSC3 VDD #RESET
VSS
TEST P13/RFIN0/PIOA7 P12/REF0/PIOA6 P11/SENA0/PIOA5 P10/SENB0/PIOA4 IREF_M VOSC VM1 VM2 OSC2 OSC1 OSC4 OSC3 VDD #RESET
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Pin name
P14
P15
P16
P17
VSS
P20
P21
P22
P23
VDD
P24
P25
P26
P27
P30
VSS
Port function or signal assignment
P14/SENB1/PIOD0
P15/SENA1/PIOD1
P16/REF1/PIOD2
P17/RFIN1/PIOD3
VSS
P20/SDO1/PIOD4
P21/SDI1/PIOD5
P22/SPICLK1/PIOD6
P23/#SPISS1/PIOD7
VDD
P24/#SPISS2
P25/SPICLK2
P26/SDI2
P27/SDO2
P30/EXCL1/RFCLKO0
VSS
VSS
VD1
P07
P06
P05
P04
P03
P02
VPP
C2P
C2N
C1H
C1P
C1N
VDD
VSS
VSS
VD1
P07/SDO0/PIOA3
P06/SDI0/PIOA2
P05/SPICLK0/PIOA1
P04/#SPISS0/PIOA0
P03/EXOSC/#PIOCE
P02/EXCL0/#PIORD
VPP
C2P
C2N
C1H
C1P
C1N
VDD
VSS
3.1.1 S1C17F13 Pin Configuration Diagram (TQFP13-64pin)Figure 1.

1 OVERVIEW
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation 1-5
(Rev. 1.0)
Pad Configuration Diagram (Chip)1.3.2
Die No. CJF13Dxxx
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
Pad
name
P14
P15
P16
P17
VSS
VSS
N.C.
P20
P21
P22
P23
VDD
P24
P25
P26
P27
N.C.
P30
N.C.
VSS
VSS
Port function or
signal assignment
P14/SENB1/PIOD0
P15/SENA1/PIOD1
P16/REF1/PIOD2
P17/RFIN1/PIOD3
VSS
VSS
–
P20/SDO1/PIOD4
P21/SDI1/PIOD5
P22/SPICLK1/PIOD6
P23/#SPISS1/PIOD7
VDD
P24/#SPISS2
P25/SPICLK2
P26/SDI2
P27/SDO2
–
P30/EXCL1/RFCLKO0
–
VSS
VSS
P31 P32 P33
VDD
VSS
P34 P35 P36
N.C.
P37 P40 P41
PD0 PD1
N.C.
PD2
N.C. N.C. N.C.
P00 P01
P31/REGMON/RFCLKO1/EXSVD
P32/TOUTB1/CAPB1/PIOA0 P33/TOUTA1/CAPA1/PIOA1
VDD
VSS
P34/USIN0/PIOA2
P35/USOUT0/PIOA3
P36/SCL0/PIOD0
–
P37/SDA0/PIOD1
P40/USIN0/PIOD2
P41/USOUT0/PIOD3
DST2/PD0
DSIO/PD1
–
DCLK/PD2
– – –
P00/TOUTA0/CAPA0/FOUT
P01/TOUTB0/CAPB0/#PIOWR
VSS
VD1
N.C.
P07
P06
P05
P04
P03
P02
VPP
C2P
C2N
C1H
C1P
C1N
VDD
VSS
VSS
VD1
–
P07/SDO0/PIOA3
P06/SDI0/PIOA2
P05/SPICLK0/PIOA1
P04/#SPISS0/PIOA0
P03/EXOSC/#PIOCE
P02/EXCL0/#PIORD
VPP
C2P
C2N
C1H
C1P
C1N
VDD
VSS
VSS TEST N.C. P13 P12 P11 P10 IREF_M VOSC VM1 VM2 OSC2 OSC1 VSS OSC4 OSC3 N.C. VDD #RESET
VSS
TEST – P13/RFIN0/PIOA7 P12/REF0/PIOA6 P11/SENA0/PIOA5 P10/SENB0/PIOA4 IREF_M VOSC VM1 VM2 OSC2 OSC1 VSS OSC4 OSC3 – VDD #RESET
Y
X
(0, 0)
3.279 mm
3.339 mm
3.2.1 S1C17F13 Pad Configuration Diagram (Chip)Figure 1.
Pad opening No. 1–21, 39–57: X = 76 µm, Y = 90 µm
No. 22–29: X = 85 µm, Y = 122 µm
No. 30–38, 58–78: X = 90 µm, Y = 76 µm
Chip thickness 400 µm

1 OVERVIEW
1-6 Seiko Epson Corporation S1C17F13 TECHNICAL MANUAL
(Rev. 1.0)
3.2.1 Pad CoordinatesTable 1.
No. X [µm] Y [µm] No. X [µm] Y [µm] No. X [µm] Y [µm] No. X [µm] Y [µm]
1 -1275.0 -1548.6 22 1581.1 -1126.7 39 1201.3 1548.6 58 -1578.6 1070.0
2 -690.0 -1548.6 23 1581.1 -986.7 40 1101.3 1548.6 59 -1578.6 970.0
3 -600.0 -1548.6 24 1581.1 -846.7 41 1006.3 1548.6 60 -1578.6 870.0
4 -510.0 -1548.6 25 1581.1 -706.7 42 826.3 1548.6 61 -1578.6 770.0
5 -420.0 -1548.6 26 1581.1 -566.7 43 736.3 1548.6 62 -1578.6 680.0
6 -330.0 -1548.6 27 1581.1 -426.7 44 646.3 1548.6 63 -1578.6 590.0
7 -240.0 -1548.6 28 1581.1 -286.7 45 556.3 1548.6 64 -1578.6 500.0
8 -150.0 -1548.6 29 1581.1 -146.7 46 466.3 1548.6 65 -1578.6 410.0
9 -60.0 -1548.6 30 1578.6 75.0 47 376.3 1548.6 66 -1578.6 320.0
10 30.0 -1548.6 31 1578.6 165.0 48 286.3 1548.6 67 -1578.6 230.0
11 120.0 -1548.6 32 1578.6 255.0 49 196.3 1548.6 68 -1578.6 140.0
12 210.0 -1548.6 33 1578.6 345.0 50 106.3 1548.6 69 -1578.6 50.0
13 300.0 -1548.6 34 1578.6 435.0 51 -630.0 1548.6 70 -1578.6 -130.0
14 480.0 -1548.6 35 1578.6 525.0 52 -730.0 1548.6 71 -1578.6 -220.0
15 660.0 -1548.6 36 1578.6 615.0 53 -830.0 1548.6 72 -1578.6 -310.0
16 750.0 -1548.6 37 1578.6 1071.3 54 -930.0 1548.6 73 -1578.6 -400.0
17 840.0 -1548.6 38 1578.6 1171.3 55 -1020.0 1548.6 74 -1578.6 -580.0
18 930.0 -1548.6 – – – 56 -1110.0 1548.6 75 -1578.6 -670.0
19 1020.0 -1548.6 – – – 57 -1290.0 1548.6 76 -1578.6 -760.0
20 1110.0 -1548.6 – – – – – – 77 -1578.6 -850.0
21 1200.0 -1548.6 – – – – – – 78 -1578.6 -940.0
Pin Descriptions1.3.3
Symbol meanings
Assigned signal: The signal listed at the top of each pin is assigned in the initial state. The pin function must be
switched via software to assign another signal (see the “I/O Ports” chapter).
I/O: I = Input
O = Output
I/O = Input/output
P = Power supply
A = Analog signal
Hi-Z = High impedance state
Initial state: I (Pull-up) = Input with pulled up
I (Pull-down) = Input with pulled down
Hi-Z = High impedance state
O (H) = High level output
O (L) = Low level output
3.3.1 Pin descriptionTable 1.
Pin/pad
name Assigned signal I/O Initial state
Tolerant
fail-safe
structure
Function
VDD VDD P – – Power supply (+)
VSS VSS P – – GND
VD1 VD1 A – –
Embedded regulator output (internal circuit operating voltage)
VOSC VOSC A – – Embedded regulator output (oscillator circuit operating voltage)
VPP VPP P – – Flash programming power supply
(Leave the pin open during normal operation.)
C1N C1N A – – Capacitor connect pin for Flash voltage booster
C1P C1P A – – Capacitor connect pin for Flash voltage booster
C1H C1H A – – Capacitor connect pin for Flash voltage booster
C2N C2N A – – Capacitor connect pin for Flash voltage booster
C2P C2P A – – Capacitor connect pin for Flash voltage booster
IREF_M IREF_M A – – IREF constant current monitor pin
(Leave the pin open during normal operation.)
VM1 VM1 A – – Temperature sensor voltage monitor pin
(Leave the pin open during normal operation.)
VM2 VM2 A – – Temperature sensor voltage monitor pin
(Leave the pin open during normal operation.)
OSC1 OSC1 A – – OSC1A oscillator circuit input

1 OVERVIEW
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation 1-7
(Rev. 1.0)
Pin/pad
name Assigned signal I/O Initial state
Tolerant
fail-safe
structure
Function
OSC2 OSC2 A – – OSC1A oscillator circuit output
OSC3 OSC3 A – – OSC3A oscillator circuit input
OSC4 OSC4 A – – OSC3A oscillator circuit output
#RESET #RESET I I (Pull-up) – Reset input
TEST TEST I I (Pull-down) – Test input
(Connect to VSS during normal operation.)
P00 P00 I/O Hi-Z
(TBD)
✓General-purpose I/O port
TOUTA0/CAPA0 I/O
16-bit PWM timer Ch.0 TOUTA signal output/capture A trigger
signal input
FOUT O Clock generator clock output
P01 P01 I/O Hi-Z
(TBD)
✓General-purpose I/O port
TOUTB0/CAPB0 I/O
16-bit PWM timer Ch.0 TOUTB signal output/capture B trigger
signal input
#PIOWR O Parallel interface write signal output
P02 P02 I/O Hi-Z
(TBD)
✓General-purpose I/O port
EXCL0 I 16-bit PWM timer Ch.0 external clock input
#PIORD O Parallel interface read signal output
P03 P03 I/O Hi-Z
(TBD)
✓General-purpose I/O port
EXOSC I Clock generator external clock input
#PIOCE O Parallel interface chip enable signal output
P04 P04 I/O Hi-Z
(TBD)
✓General-purpose I/O port
#SPISS0 I Synchronous serial interface Ch.0 slave select input
PIOA0 O Parallel interface address output
P05 P05 I/O Hi-Z ✓General-purpose I/O port
SPICLK0 I/O Synchronous serial interface Ch.0 clock input/output
PIOA1 O Parallel interface address output
P06 P06 I/O Hi-Z ✓General-purpose I/O port
SDI0 I Synchronous serial interface Ch.0 data input
PIOA2 O Parallel interface address output
P07 P07 I/O Hi-Z ✓General-purpose I/O port
SDO0 O Synchronous serial interface Ch.0 data output
PIOA3 O Parallel interface address output
P10 P10 I/O Hi-Z –General-purpose I/O port
SENB0 A R/F converter Ch.0 sensor B oscillation control
PIOA4 O Parallel interface address output
P11 P11 I/O Hi-Z –General-purpose I/O port
SENA0 A R/F converter Ch.0 sensor A oscillation control
PIOA5 O Parallel interface address output
P12 P12 I/O Hi-Z –General-purpose I/O port
REF0 A R/F converter Ch.0 reference oscillation control
PIOA6 O Parallel interface address output
P13 P13 I/O Hi-Z –General-purpose I/O port
RFIN0 A R/F converter Ch.0 oscillation input
PIOA7 O Parallel interface address output
P14 P14 I/O Hi-Z –General-purpose I/O port
SENB1 A R/F converter Ch.1 sensor B oscillation control
PIOD0 I/O Parallel interface data input/output
P15 P15 I/O Hi-Z –General-purpose I/O port
SENA1 A R/F converter Ch.1 sensor A oscillation control
PIOD1 I/O Parallel interface data input/output
P16 P16 I/O Hi-Z –General-purpose I/O port
REF1 A R/F converter Ch.1 reference oscillation control
PIOD2 I/O Parallel interface data input/output
P17 P17 I/O Hi-Z –General-purpose I/O port
RFIN1 A R/F converter Ch.1 oscillation input
PIOD3 I/O Parallel interface data input/output
P20 P20 I/O Hi-Z ✓General-purpose I/O port
SDO1 O Synchronous serial interface Ch.1 data output
PIOD4 I/O Parallel interface data input/output