Atmel AVR ATtiny10 Series User manual

1
Features
•Utilizes the AVR®RISC Architecture
•High-performance and Low-power 8-bit RISC Architecture
– 90 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 8 MIPS Throughput at 8 MHz
•Nonvolatile Program and Data Memory
–1K Byte of Flash Program Memory
QuickFlash™One-time Programmable (ATtiny10)
In-System Programmable (ATtiny12)
Endurance: 1,000 Write/Erase Cycles (ATtiny11/12)
–64 Bytes of In-System Programmable EEPROM Data Memory (ATtiny12)
Endurance: 100,000 Write/Erase Cycles
–Programming Lock for Flash Program and EEPROM Data Security
•Peripheral Features
–Interrupt and Wake-up on Pin Change
–One 8-bit Timer/Counter with Separate Prescaler
–On-chip Analog Comparator
–Programmable Watchdog Timer with On-chip Oscillator
•Special Microcontroller Features
–Low-power Idle and Power-down Modes
–External and Internal Interrupt Sources
–In-System Programmable via SPI Port (ATtiny12)
–Enhanced Power-on Reset Circuit (ATtiny12)
–Internal Calibrated RC Oscillator (ATtiny12)
•Specification
–Low-power, High-speed CMOS Process Technology
–Fully Static Operation
•Power Consumption at 4 MHz, 3V, 25°C
–Active: 2.2 mA
–Idle Mode: 0.5 mA
–Power-down Mode: <1 µA
•Packages
–8-pin PDIP and SOIC
•ATtiny10 is the QuickFlash OTP Version of ATtiny11
•Operating Voltages
–1.8 - 5.5V (ATtiny12V-1)
–2.7 - 5.5V (ATtiny11L-2 and ATtiny12L-4)
–4.0 - 5.5V (ATtiny11-6 and ATtiny12-8)
•Speed Grades
–0 - 1 MHz (ATtiny12V-1)
–0 - 2 MHz (ATtiny11L-2)
–0 - 4 MHz (ATtiny12L-4)
–0 - 6 MHz (ATtiny11-6)
–0 - 8 MHz (ATtiny12-8)
Rev. 1006B–10/99
8-bit
Microcontroller
with 1K Bytes
Flash
ATtiny10
ATtiny11
ATtiny12
Preliminary
Pin Configuration
1
2
3
4
8
7
6
5
(RESET) PB5
(XTAL1) PB3
(XTAL2) PB4
GND
VCC
PB2 (T0)
PB1 (INT0/AIN1)
PB0 (AIN0)
ATtiny10/11
PDIP/SOIC
1
2
3
4
8
7
6
5
(RESET) PB5
(XTAL1) PB3
(XTAL2) PB4
GND
VCC
PB2 (SCK/T0)
PB1 (MISO/INT0/AIN1)
PB0 (MOSI/AIN0)
ATtiny12
PDIP/SOIC

ATtiny10/11/12
2
Description
The ATtiny10/11/12 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing power-
ful instructions in a single clock cycle, the ATtiny10/11/12 achieves throughputs approaching 1 MIPS per MHz, allowing the
system designer to optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general-purpose working registers. All the 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times
faster than conventional CISC microcontrollers.
ATtiny10/11 Block Diagram
The ATtiny10/11 provides the following features: 1K bytes of Flash, up to five general-purpose I/O lines, one input line,
32 general-purpose working registers, an 8-bit timer/counter, internal and external interrupts, programmable Watchdog
Timer with internal oscillator, and two software-selectable power-saving modes. The Idle Mode stops the CPU while allow-
ing the timer/counters and interrupt system to continue functioning. The Power-down Mode saves the register contents but
freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. The wake-up or interrupt
on pin change features enable the ATtiny10/11 to be highly responsive to external events, still featuring the lowest power
consumption while in the power-down modes.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. By combining an RISC 8-bit CPU
with Flash on a monolithic chip, the Atmel ATtiny10/11 is a powerful microcontroller that provides a highly-flexible and cost-
effective solution to many embedded control applications.
The ATtiny10/11 AVR is supported with a full suite of program and system development tools including: macro assemblers,
program debugger/simulators, in-circuit emulators, and evaluation kits.
Table 1. Parts Description
Device Flash EEPROM Register Voltage Range Frequency
ATtiny10/11L 1K - 32 2.7 - 5.5V 0-2 MHz
ATtiny10/11 1K - 32 4.0 - 5.5V 0-6 MHz
ATtiny12V 1K 64 B 32 1.8 - 5.5V 0-1 MHz
ATtiny12L 1K 64 B 32 2.7 - 5.5V 0-4 MHz
ATtiny12 1K 64 B 32 4.0 - 5.5V 0-8 MHz

ATtiny10/11/12
3
Figure 1. The ATtiny10/11 Block Diagram
PROGRAM
COUNTER
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
STACK
POINTER
PROGRAM
FLASH HARDWARE STACK MCU CONTROL
REGISTER
GENERAL-
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
TIMER/
COUNTER
INSTRUCTION
DECODER
DATA DIR.
REG. PORTB
DATA REGISTER
PORTB
PROGRAMMING
LOGIC OSCILLATORS
TIMING AND
CONTROL
INTERRUPT
UNIT
MCU STATUS
REGISTER
STATUS
REGISTER
ALU
PORTB DRIVERS
PB0-PB5
VCC
GND
CONTROL
LINES
+
-
ANALOG
COMPARATOR
8-BIT DATA BUS
Z

ATtiny10/11/12
4
ATtiny12 Block Diagram
Figure 2. The ATtiny12 Block Diagram
The ATtiny12 provides the following features: 1K bytes of Flash, 64 bytes EEPROM, up to six general-purpose I/O lines,
32 general-purpose working registers, an 8-bit timer/counter, internal and external interrupts, programmable Watchdog
Timer with internal oscillator, and two software-selectable power-saving modes. The Idle Mode stops the CPU while allow-
ing the timer/counters and interrupt system to continue functioning. The Power-down Mode saves the register contents but
freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. The wake-up or interrupt
on pin change features enable the ATtiny12 to be highly responsive to external events, still featuring the lowest power
consumption while in the power-down modes.
PROGRAM
COUNTER
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
STACK
POINTER
PROGRAM
FLASH HARDWARE STACK MCU CONTROL
REGISTER
GENERAL-
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
TIMER/
COUNTER
INSTRUCTION
DECODER
DATA DIR.
REG. PORTB
DATA REGISTER
PORTB
PROGRAMMING
LOGIC OSCILLATORS
TIMING AND
CONTROL
INTERRUPT
UNIT
MCU STATUS
REGISTER
STATUS
REGISTER
ALU
PORTB DRIVERS
PB0-PB5
VCC
GND
CONTROL
LINES
+
-
ANALOG
COMPARATOR
Z
8-BIT DATA BUS
EEPROM
SPI
INTERNAL
OSCILLATOR
CALIBRATED

ATtiny10/11/12
5
The device is manufactured using Atmel’s high-density nonvolatile memory technology. By combining an RISC 8-bit CPU
with Flash on a monolithic chip, the Atmel ATtiny12 is a powerful microcontroller that provides a highly-flexible and cost-
effective solution to many embedded control applications.
The ATtiny12 AVR is supported with a full suite of program and system development tools including: macro assemblers,
program debugger/simulators, in-circuit emulators, and evaluation kits.
Pin Descriptions
VCC
Supply voltage pin.
GND
Ground pin.
Port B (PB5..PB0)
Port B is a 6-bit I/O port. PB4..0 are I/O pins that can provide internal pull-ups (selected for each bit). On ATtiny10/11, PB5
is input only. On ATtiny12, PB5 is input or open-drain output. The port pins are tri-stated when a reset condition becomes
active, even if the clock is not running. The use of pins PB5..3 as input or I/O pins is limited, depending on reset and clock
settings, as shown below.
Notes: 1. “Used”means the pin is used for reset or clock purposes.
2. “-”means the pin function is unaffected by the option.
3. Input means the pin is a port input pin.
4. On ATtiny10/11, PB5 is input only. On ATtiny12, PB5 is input or open-drain output.
5. I/O means the pin is a port input/output pin.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
RESET
Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate
a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
Table 2. PB5..PB3 Functionality vs. Device Clocking Options
Device Clocking Option PB5 PB4 PB3
External Reset Enabled Used(1) -(2) -
External Reset Disabled Input(3)/I/O(4) --
External Crystal - Used Used
External Low-frequency Crystal - Used Used
External Ceramic Resonator - Used Used
External RC Oscillator - I/O(5) Used
External Clock - I/O Used
Internal RC Oscillator - I/O I/O

ATtiny10/11/12
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Clock Options
The device has the following clock source options, selectable by Flash fuse bits as shown:
Note: “1”means unprogrammed, “0”means programmed.
The various choices for each clocking option give different start-up times as shown in Table 7 on page 18 and Table 9 on
page 19.
Internal RC Oscillator
The internal RC oscillator option is an on-chip oscillator running at a fixed frequency of 1 MHz. If selected, the device can
operate with no external components. The device is shipped with this option selected. On ATtiny10/11, the Watchdog
Oscillator is used as a clock, while ATtiny12 uses a separate calibrated oscillator.
Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an
on-chip oscillator, as shown in Figure 3. Either a quartz crystal or a ceramic resonator may be used.
Figure 3. Oscillator Connections
Note: When using the MCU Oscillator as a clock for an external device, an HC buffer should be connected as indicated in the figure.
Table 3. Device Clocking Options Select
Device Clocking Option ATtiny10/11 CKSEL2..0 ATtiny12 CKSEL3..0
External Crystal/Ceramic Resonator 111 1111 - 1010
External Low-frequency Crystal 110 1001 - 1000
External RC Oscillator 101 0111 - 0101
Internal RC Oscillator 100 0100 - 0010
External Clock 000 0001 - 0000
Reserved Other Options -
XTAL2
XTAL1
GND
C2
C1
MAX 1 HC BUFFER
HC

ATtiny10/11/12
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External Clock
To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 4.
Figure 4. External Clock Drive Configuration
External RC Oscillator
For timing insensitive applications, the external RC configuration shown in Figure 5 can be used. For details on how to
choose R and C, see Table 29 on page 53.
Figure 5. External RC Configuration
Architectural Overview
The fast-access register file concept contains 32 x 8-bit general-purpose working registers with a single-clock-cycle access
time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands
are output from the register file, the operation is executed, and the result is stored back in the register file –in one clock
cycle.
Two of the 32 registers can be used as a 16-bit pointer for indirect memory access. This pointer is called the Z-pointer, and
can address the register file and the Flash program memory.
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single-register
operations are also executed in the ALU. Figure 2 shows the ATtiny10/11/12 AVR RISC microcontroller architecture. The
AVR uses a Harvard architecture concept with separate memories and buses for program and data memories. The pro-
gram memory is accessed with a two-stage pipelining. While one instruction is being executed, the next instruction is pre-
fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program
memory is reprogrammable Flash memory.
With the relative jump and relative call instructions, the whole 512 address space is directly accessed. All AVR instructions
have a single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction.
PB4 (XTAL2)
XTAL1
GND
EXTERNAL
OSCILLATOR
SIGNAL
PB4 (XTAL2)
XTAL1
GND
C
R
VCC

ATtiny10/11/12
8
During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is a
3-level-deep hardware stack dedicated for subroutines and interrupts.
The I/O memory space contains 64 addresses for CPU peripheral functions as control registers, timer/counters, and other
I/O functions. The memory spaces in the AVR architecture are all linear and regular memory maps.
Figure 6. The ATtiny10/11/12 AVR RISC Architecture
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status
register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the
program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the
interrupt vector address, the higher the priority.
512 x 16
Program
Flash
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General-
purpose
Registers
ALU
Direct Addressing
Status
and Test Control Registers
Interrupt
Unit
8-bit
Timer/Counter
Watchdog
Timer
Analog
Comparator
6
I/O Lines
8-bit Data Bus
SPI Unit
(ATtiny12 only)
64 x 8 EEPROM
(ATtiny12 only)

ATtiny10/11/12
9
General-purpose Register File
Figure 7 shows the structure of the 32 general-purpose registers in the CPU.
Figure 7. AVR CPU General-purpose Working Registers
All the register operating instructions in the instruction set have direct- and single-cycle access to all registers. The only
exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and a
register and the LDI instruction for load-immediate constant data. These instructions apply to the second half of the regis-
ters in the register file –R16..R31. The general SBC, SUB, CP, AND, OR and all other operations between two registers or
on a single register apply to the entire register file.
Registers 30 and 31 form a 16-bit pointer (the Z-pointer) which is used for indirect Flash memory and register file access.
When the register file is accessed, the contents of R31 are discarded by the CPU.
ALU –Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general-purpose working registers. Within a
single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into
three main categories –arithmetic, logic and bit-functions. Some microcontrollers in the AVR product family feature a hard-
ware multiplier in the arithmetic part of the ALU.
Flash Program Memory
The ATtiny10/11/12 contains 1K bytes on-chip Flash memory for program storage. Since all instructions are single 16-bit
words, the Flash is organized as 512 x 16 words. The Flash memory has an endurance of at least 1000 write/erase cycles.
The ATtiny10/11/12 Program Counter is 9 bits wide, thus addressing the 512 words Flash program memory.
See page 39 for a detailed description on Flash memory programming.
Program and Data Addressing Modes
The ATtiny10/11/12 AVR RISC Microcontroller supports powerful and efficient addressing modes. This section describes
the different addressing modes supported in the ATtiny10/11/12. In the figures, OP means the operation code part of the
instruction word. To simplify, not all figures show the exact location of the addressing bits.
70
R0
R1
R2
General- …
purpose …
Working R28
Registers R29
R30 (Z-register low byte)
R31 (Z-register high byte)

ATtiny10/11/12
10
Register Direct, Single Register Rd
Figure 8. Direct Single-register Addressing
The operand is contained in register d (Rd).
Register Indirect
Figure 9. Indirect Register Addressing
The register accessed is the one pointed to by the Z-register (R31, R30).
REGISTER FILE 0
31
30
Z-register