Terasic ALTERA MAX 10 NEEK User manual

MAX 10 NEEK User
Manual
1 www.terasic.com
February 4, 2016

MAX 10 NEEK 1 www.terasic.com
February 4, 2016
CONTENTS
Chapter 1  MAX 10 NEEK Development Kit ...................................................... 3 
1.1 Package Contents .......................................................................................................................3
1.2 MAX 10 NEEK System CD.......................................................................................................4
1.3 Getting Help ...............................................................................................................................4
Chapter 2  Introduction of the MAX 10 NEEK Board.......................................... 5 
2.1 Layout and Components.............................................................................................................5
2.2 Block Diagram of the MAX 10 NEEK Board............................................................................7
Chapter 3  Using the MAX 10 NEEK Board ..................................................... 10 
3.1 Configuration of MAX 10 FPGA on MAX 10 NEEK .............................................................10
3.2 Board Status Elements..............................................................................................................16
3.3 Clock Circuitry .........................................................................................................................17
3.4 Peripherals Connected to the FPGA.........................................................................................18
Chapter 4  NEEK10 System Builder ................................................................ 43 
4.1 Introduction ..............................................................................................................................43
4.2 General Design Flow................................................................................................................43
4.3 Using NEEK10 System Builder ...............................................................................................45
Chapter 5  RTL Example Codes ...................................................................... 50 
5.1 PS/2 Mouse Demonstration......................................................................................................50
5.2 Power Monitor..........................................................................................................................53
5.3 ADC Potentiometer ..................................................................................................................55
5.4 DAC Demonstration.................................................................................................................57
5.5 ADC/MIC/LCD Demonstration ...............................................................................................60
5.6 HDMI RX Demonstration ........................................................................................................63
Chapter 6  NIOS Based Example Codes ......................................................... 67 

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6. 1Power Monitor...................................................................................................................67
6. 2UART to USB control LED...............................................................................................72
6. 3SD Card Audio Demonstration..........................................................................................75
6. 4DDR3 SDRAM Test by Nios II.........................................................................................80
6. 5Ethernet Socket server.......................................................................................................83
6. 6LCD Painter.......................................................................................................................90
6. 7Digital Accelerometer Demonstration...............................................................................94
6. 8Humidity/Temperature Sensor...........................................................................................96
6. 9LCD CAMERA Demonstration ........................................................................................99
Chapter 7  Application Selector ..................................................................... 105 
7.1 Ready to Run SD Card Demos...............................................................................................105
7.2 Application Selector Details ...................................................................................................106
7.3 Running the Application Selector...........................................................................................107
7.4 Creating Your Own Loadable Applications............................................................................107
7.5 Restoring the Factory Image ..................................................................................................110
Chapter 8 Programming the Configuration Flash Memory ............................ 112 
8.1 Internal Configuration ............................................................................................................112
8.2 Using Dual Compressed Images ............................................................................................114
8.3 Nios II Load In Single Boot Image ........................................................................................117
Chapter 9  Appendix ..................................................................................... 120 
Revision History...........................................................................................................................120
Copyright Statement.....................................................................................................................120

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February 4, 2016
Chapter 1
MAX 10 NEEK Development Kit
The MAX 10 NEEK from Terasic is a full featured embedded evaluation kit based upon the
MAX10 family of Altera FPGAs. It offers a comprehensive design environment with everything
embedded developers need to create a processing based system. The MAX 10 NEEK delivers an
integrated platform that includes hardware, design tools, intellectual property and reference designs
for developing a wide range of audio, video and many other exciting applications.
The fully integrated kit allows developers to rapidly customize their processor and IP to suit their
specific needs, rather than constraining their software around the fixed feature set of the processor.
The all-in-one embedded solution, the MAX 10 NEEK, combines a 5-point LCD touch panel and
digital image module that provides developers an ideal platform for multimedia applications,
making the best use of the parallel nature of FPGAs.
1
1. .1 1 P Pa ac ck ka ag ge e C Co on nt te en nt ts s
Figure 1-1 shows a photograph of the MAX 10 NEEK package.
Figure 1-1 The MAX 10 NEEK package contents

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February 4, 2016
The MAX 10 NEEK package includes:
The MAX 10 NEEK development board
MAX 10 NEEK Quick Start Guide
One USB cables (Type A to Mini-B) for USB control and FPGA programming and control
5V DC power adapter
Power Cable
1
1. .2 2 M MA AX X 1 10 0 N NE EE EK K S Sy ys st te em m C CD D
The MAX 10 NEEK System CD contains all the documents and supporting materials associated
with MAX 10 NEEK, including the user manual, system builder, reference designs, and device
datasheets. Users can download this system CD from the link: http://cd-max10-neek.terasic.com.
1
1. .3 3 G Ge et tt ti in ng g H He el lp p
Here are the addresses where you can get help if you encounter any problems:
Altera Corporation
101 Innovation Drive San Jose, California, 95134 USA
Email: [email protected]
Terasic Technologies
9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
Email: [email protected]
Tel.: [phone]
Website: max10-neek.terasic.com

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Chapter 2
Introduction of the MAX 10 NEEK
Board
2
2. .1 1 L La ay yo ou ut t a an nd d C Co om mp po on ne en nt ts s
Figure 2-1 shows a photograph of the board. It depicts the layout of the board and indicates the
location of the connectors and key components.
Figure 2-1 MAX 10 NEEK development board (top view)

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February 4, 2016
Figure 2-2 MAX 10 NEEK development board (bottom view)
The MAX 10 NEEK board has many features that allow users to implement a wide range of
designed circuits, from simple circuits to various multimedia projects.
The following hardware is provided on the board:
Altera MAX® 10 10M50DAF484C6G device
USB-Blaster II onboard for programming; JTAG Mode
256MB DDR3 SDRAM (64Mx16 and 128Mx8)
64MB QSPI Flash
Micro SD card socket
Five push-buttons
Ten slide switches
Ten red user LEDs
Two 7-segment displays
Three 50MHz clock sources from the clock generator
24-bit CD-quality audio CODEC with line-in, line-out jacks
On-board microphone
HDMI RX, incorporates HDM v1.4a features, including 3D video supporting
800x480 7.0 inch Color LCD with 5-point Capacitive-touch
Gigabit Ethernet PHY with RJ45 connector
UART to USB, USB Mini-B connector
8M pixel MIPI CS2 color camera input

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One ambient light sensor
One humidity and temperature sensor
One accelerometer
One external 16 bit digital-to-analog converter (DAC) device with SMA output
Potentiometer input to ADC
Two MAX 10 FPGA ADC SMA inputs
One 2x10 ADC header with 16 analog inputs connected to MAX10 ADCs
2
2. .2 2 B Bl lo oc ck k D Di ia ag gr ra am m o of f t th he e M MA AX X 1 10 0 N NE EE EK K B Bo oa ar rd d
Figure 2-3 is the block diagram of the board. All the connections are established through the MAX
10 FPGA device to provide maximum flexibility for users. Users can configure the FPGA to
implement any system design.
Figure 2-3 Block diagram of MAX 10 NEEK

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F
FP PG GA A D De ev vi ic ce e
MAX 10 10M50DAF484C6G Device
Integrated dual ADCs, each ADC supports 1 dedicated analog input and 8 dual function pins
50K programmable logic elements
1,638 Kbits embedded memory
5,888 Kbits user flash memory
4 PLLs
C
Co on nf fi ig gu ur ra at ti io on n a an nd d D De eb bu ug g
On-board USB-Blaster II (mini USB type B connector)
Optional JTAG direct via 10-pin header
One slide switch for dual boot image selection
M
Me em mo or ry y D De ev vi ic ce e
256MB DDR3 SDRAM (64Mx16 and 128Mx8)
512Mb QSPI Flash
Micro SD card socket
C
Co om mm mu un ni ic ca at ti io on n a an nd d E Ex xp pa an ns si io on n H He ea ad de er r
Gigabit Ethernet PHY with RJ45 connector
UART to USB, USB Mini-B connector
PS/2 mouse/keyboard connector
2x6 TMD (Terasic Mini Digital) Expansion Header
D
Di is sp pl la ay y
800x480 7.0 inch Color LCD with 5-point Capacitive-touch
A
Au ud di io o
24-bit CD-quality audio CODEC with line-in, line-out jacks
V
Vi id de eo o I In np pu ut t
HDMI RX, incorporates HDM v1.4a features, including 3D video supporting
8M pixel MIPI CS2 color camera input
A
An na al lo og g
Two MAX 10 FPGA ADC SMA inputs
Potentiometer input to ADC
On-Board MIC input to ADC
2x10 ADC header with 16 analog inputs connected to MAX10 ADCs
One DAC SMA output

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February 4, 2016
S
Sw wi it tc ch he es s, , B Bu ut tt to on ns s, , a an nd d I In nd di ic ca at to or rs s
Five push-buttons
Ten slide switches
Ten red user LEDs
Two 7-segment displays
S
Se en ns so or rs s
Ambient light sensor
Humidity and temperature sensor
Accelerometer
Power monitor
P
Po ow we er r
5V/3A DC input

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February 4, 2016
Chapter 3
Using the MAX 10 NEEK Board
This chapter provides an instruction to use the board and describes the peripherals.
3
3. .1 1 C Co on nf fi ig gu ur ra at ti io on n o of f M MA AX X 1 10 0 F FP PG GA A o on n M MA AX X 1 10 0 N NE EE EK K
There are two types of configuration method supported by MAX 10 NEEK:
1. JTAG configuration: configuration using JTAG ports.
JTAG configuration scheme allows you to directly configure the device core through JTAG pins -
TDI, TDO, TMS, and TCK pins. The Quartus II software automatically generates .sof that are used
for JTAG configuration with a download cable in the Quartus II software programmer..
2. Internal configuration: configuration using internal flash.
Before internal configuration, you need to program the configuration data into the configuration
flash memory (CFM) which provides non-volatile storage for the bit stream. The information is
retained within CFM even if the MAX 10 NEEK board is turned off. When the board is powered on,
the configuration data in the CFM is automatically loaded into the MAX 10 FPGA.
JTAG Chain on MAX 10 NEEK Board
The FPGA device can be configured through JTAG interface on MAX 10 NEEK board, but the
JTAG chain must form a closed loop, which allows Quartus II programmer to the detect FPGA
device. Figure 3-1 illustrates the JTAG chain on MAX 10 NEEK board

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February 4, 2016
Figure 3-1 Path of the JTAG chain
Configure the FPGAin JTAG Mode
The following shows how the FPGA is programmed in JTAG mode step by step.
1. Open the Quartus II programmer and click “Auto Detect”, as circled in Figure 3-2
Figure 3-2 Detect FPGA device in JTAG mode
2. Select detected device associated with the board, as circled in Figure 3-3.

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February 4, 2016
Figure 3-3 Select 10M50DAES device
3. FPGA is detected, as shown in Figure 3-4.
Figure 3-4 FPGA detected in Quartus programmer
4. Right click on the FPGA device and open the .sof file to be programmed, as highlighted in
Figure 3-5

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Figure 3-5 Open the .sof file to be programmed into the FPGA device
5. Select the .sof file to be programmed, as shown in Figure 3-6.

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February 4, 2016
Figure 3-6 Select the .sof file to be programmed into the FPGA device
6. Click “Program/Configure” check box and then click “Start” button to download the .sof file
into the FPGA device, as shown in Figure 3-7.

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February 4, 2016
Figure 3-7 Program .sof file into the FPGA device
Internal Configuration
The configuration data to be written to CFM will be part of the programmer object file (.pof).
This configuration data is automatically loaded from the CFM into the MAX 10 devices when
the board is powered up.
Please refer to Chapter 8: Programming the Configuration Flash Memory (CFM) for the basic
programming instruction on the configuration flash memory (CFM).
Figure 3-8 High-Level Overview of Internal Configuration for MAX 10 Devices

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February 4, 2016
3
3. .2 2 B Bo oa ar rd d S St ta at tu us s E El le em me en nt ts s
In addition to the 10 LEDs that FPGA device can control, there are 4 indicators which can indicate
the board status (See Figure 3-9), please refer the details in Table 3-1
Figure 3-9 LED Indicators on MAX 10 NEEK
Table 3-1 LED Indicators
Board Reference LED Name Description
D13 5V Power Illuminate when 5V power is active.
D14 2.5V Power Illuminate when 2.5V power is active.
D16 1.2V Power Illuminate when 1.2V power is active.
D6 CONF_DONE Illuminate when configuration data is loaded into MAX 10
device without error.
D7 JTAG_RX Illuminate during data is uploaded from MAX 10 device to PC
through UB2.
D8 JTAG_TX Illuminate during configuration data is loaded into MAX 10
device from UB2.
TXD TXD Illuminate during transmitting data via USB.
RXD RXD Illuminate during receiving data via USB.

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3
3. .3 3 C Cl lo oc ck k C Ci ir rc cu ui it tr ry y
Figure 3-10 shows the default frequency of all external clocks to the MAX 10 FPGA. A clock
generator is used to distribute clock signals with low jitter. The three 50MHz clock signals
connected to the FPGA are used as clock sources for user logic. One 25MHz clock signal is
connected to the clock input of Gigabit Ethernet Transceiver. One 24MHz clock signal is connected
to the clock inputs of USB microcontroller of USB Blaster II. One 28.63636MHz clock signal is
connected to the clock input of HDMI Receiver chip. The other 50MHz clock signal is connected to
MAX CPLD of USB Blaster II. One 10MHz clock signal is connected to the PLL1 and PLL3 of
FPGA, the outputs of these two PLLs can drive ADC clock. The associated pin assignment for
clock inputs to FPGA I/O pins is listed in Table 3-2.
Figure 3-10 Block diagram of the clock distribution on MAX 10 NEEK

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Table 3-2 Pin Assignment of Clock Inputs
Signal Name FPGA Pin No. Description I/O Standard
MAX10_CLK1_50 PIN_N5 50 MHz clock input 2.5V
MAX10_CLK2_50 PIN_V9 50 MHz clock input 3.3V
MAX10_CLK3_50 PIN_N14 50 MHz clock input 1.5V
ADC_CLK_10 PIN_M9 10 MHz clock input 3.3V
3
3. .4 4 P Pe er ri ip ph he er ra al ls s C Co on nn ne ec ct te ed d t to o t th he e F FP PG GA A
This section describes the interfaces connected to the FPGA. User can control or monitor different
interfaces with user logic from the FPGA.
3
3. .4 4. .1 1 U Us se er r P Pu us sh h- -b bu ut tt to on ns s, , S Sw wi it tc ch he es s, , L LE ED Ds s
The board has five push-buttons connected to the FPGA, as shown in Figure 3-11. MAX 10 devices
support Schmitt trigger input on all I/O pins. A Schmitt trigger feature introduces hysteresis to the
input signal for improved noise immunity, especially for signal with slow edge rate and act as
switch debounce in Figure 3-12 for the push-buttons connected.
Figure 3-11 Connections between the push-buttons and the MAX 10 FPGA

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Figure 3-12 Switch debouncing
There are two ten switches connected to the FPGA, as shown in Figure 3-13. These switches are
used as level-sensitive data inputs to a circuit. Each switch is connected directly and individually to
the FPGA. When the switch is set to the DOWN position (towards the edge of the board), it
generates a low logic level to the FPGA. When the switch is set to the UP position, a high logic
level is generated to the FPGA.
Figure 3-13 Connections between the slide switches and the MAX 10 FPGA
There are also ten user-controllable LEDs connected to the FPGA. Each LED is driven directly and
individually by the MAX 10 FPGA; driving its associated pin to a high logic level or low level to
turn the LED on or off, respectively. Figure 3-14 shows the connections between LEDs and MAX
10 FPGA. Table 3-3, Figure 3-14 and Table 3-9 list the pin assignment of user push-buttons,
switches, and LEDs.
Pushbutton releasedPushbutton depressed
Before
Debouncing
Schmitt Trigger
Debounced