Terasic C5P User manual

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Contents
Chapter 1 C5P Development Kit................................................................................... 4
1.1 Package Contents ....................................................................................... 4
1.2 C5P System CD .......................................................................................... 5
1.3 Getting Help ................................................................................................ 5
Chapter 2 Introduction of the C5P board.....................................................................6
2.1 Layout and Components.............................................................................. 6
2.2 Block Diagram of the C5P Board ................................................................. 7
Chapter 3 Using the C5P Board ................................................................................. 10
3.1 Configuring the Cyclone V FPGA .............................................................. 10
3.2 Board Status Elements .............................................................................. 14
3.3 Clock Circuitry ........................................................................................... 15
3.4 Peripherals Connected to the FPGA.......................................................... 16
Chapter 4 C5P System Builder................................................................................... 35
4.1 Introduction................................................................................................ 35
4.2 General Design Flow ................................................................................. 35
4.3 Using C5P System Builder......................................................................... 36
Chapter 5 Examples of Advanced Demonstrations .................................................. 41
5.1 C5P Factory Default Configuration ............................................................ 41
5.2 Nios II SDRAM Test ................................................................................... 42
5.3 Verilog SDRAM Test .................................................................................. 44
5.4 DDR3 SDRAM Test ................................................................................... 46
5.5 DDR3 SDRAM Test by Nios II.................................................................... 48
5.6 UART Control ............................................................................................ 51
5.7 ADC Reading............................................................................................. 56
Chapter 6 Programming the EPCQ ............................................................................ 61
6.1 Convert .sof File to .jic File ........................................................................ 61
6.2 Write.jic File to EPCQ ................................................................................ 65

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6.3 Erase the EPCQ device............................................................................. 66
Chapter 7 PCIe Reference Design for Windows........................................................ 68
7.1 PCIe System Infrastructure........................................................................ 68
7.2 PC PCIe Software SDK ............................................................................. 69
7.3 PCIe Software Stack ................................................................................. 69
7.4 PCIe Library API........................................................................................ 74
7.5 PCIe Reference Design - Fundamental ..................................................... 79
7.6 PCIe Reference Design – DDR3............................................................... 85
Chapter 8 PCIe Reference Design for Linux.............................................................. 91
8.1 PCIe System Infrastructure........................................................................ 91
8.2 PC PCIe Software SDK ............................................................................. 92
8.3 PCIe Software Stack ................................................................................. 92
8.4 PCIe Library API........................................................................................ 95
8.5 PCIe Reference Design - Fundamental ..................................................... 95
8.6 PCIe Reference Design - DDR3 .............................................................. 101
Chapter 9 Appendix .................................................................................................. 107
9.1 Revision History....................................................................................... 107
9.2 Copyright Statement................................................................................ 107

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Chapter 1
C5P Development Kit
The C5P Development Kit presents a robust hardware design platform built around the
Intel Cyclone V FPGA, it also provides a powerful platform of reconfigurable power with
high performance and low power processing system. The C5P Development Kit is
equipped with PCIe Gen1x4, high-speed DDR3 memory, GPIO, Arduino and much more
that promises many exciting applications.
The C5P Development Board is equipped with PCIe Gen1X4 interface, it is low
development cost, and can support users who develop mainstream applications and
OpenCL applications based on PCIe, as well as a wide range of high-speed connectivity
applications.
The C5P Development Board contains all the tools needed to use the board in conjunction
with a computer that runs the Microsoft Windows 7 or later.
1.1 Package Contents
Figure 1-1 C5P package contents

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C5P package includes
1. C5P Development Board
2. C5P Quick Start Guide
3. PCIe Bracket (Installed)
4. Fan (Installed)
5. Screw and Silicon Footstands Package
6. AC Power Cord
7. Power Adapter
8. USB to mini-USB Cable
1.2 C5P System CD
The C5P System CD contains all the documents and supporting materials associated with
C5P, including the user manual, system builder, reference designs, and device datasheets.
Users can download this system CD from the link c5p.terasic.com.
1.3 Getting Help
Here are the addresses where you can get help if you encounter any problems:
Terasic Inc.
9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
Email：[e-mail]
Tel.：[phone]
Website：c5p.terasic.com

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Chapter 2
Introduction of the C5P board
This chapter provides an introduction to the features and design characteristics of the C5P
board.
2.1 Layout and Components
Figure 2‑1 and Figure 2-2 shows a photograph of the board. It depicts the layout of the
board and indicates the location of the connectors and key components.
Figure 2-1 C5P development board (top view)
Figure 2-2 C5P development board (bottom view)

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The C5P board has many features that allow users to implement a wide range of designed
circuits, from simple circuits to various multimedia projects:
Intel FPGA Cyclone® V GX 5CGXFC9D6F27C7N device
Serial configuration device– EPCQ256
USB-Blaster II onboard for programming; JTAG Mode
UART to USB (USB Mini-B connector)
PCIe Gen1x4
1GB DDR3 SDRAM (32-bit data bus)
64MB SDRAM (16-bit data bus)
4 push-buttons
4 slide switches
4 green LED
Two 7-segment displays
Four 50MHz clock sources from the clock generator
One Arduino header
Two 40 pin GPIO header
2.2 Block Diagram of the C5P Board
Figure 2-3 is the block diagram of the board. All the connections are established through
the Cyclone V FPGA device to provide maximum flexibility for users. Users can configure
the FPGA to implement any system design.
Figure 2-3 Block diagram of C5P board

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Detailed information about Figure 2-3 are listed below.
FPGA Device
Cyclone V 5CGXFC9D6F27C7N device
301K programmable logic elements
13,917 Kbit/s embedded memory
8 fractional PLLs
2 hard memory controllers
Nine 3.125G Transceivers
Configuration and Debug
Quad Serial Configuration device – EPCQ256
Onboard USB-Blaster II (Mini-B USB connector)
Memory Device
64MB (32Mx16) SDRAM
1GB (2x256Mx16) DDR3 SDRAM
Communication
UART to USB（USB Mini-B connector）
PCIe Gen1x4
Connectors
Two 40 Pin GPIO header，features of each GPIO connector
36 General GPIO Pins
Support to configureas 8 LVDS TX and LVDS RX
With diode protection
Configurable I/O standards (voltage levels: 3.3/2.5/1.8/1.5V)
One Arduino Uno Revision 3 header
Analog ADC
Interface: SPI
Fast through put rate：500Ksps
Channel number: 8
Resolution: 12-bit
Analog input range：0 ~ 4.096 V
Digital IO
With diode protection

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SMA IN/OUT 3.3V Single-end input and output
Switches/ Buttons/ Indicators
5 user Keys (4 general keys, 1 CPU_RESET_n)
4 user switches
4 LED
Two 7-segment displays
Power
12V DC Input
PCIe 12V Input
Cooling System
12V Fan with 5000 Rotational Speed

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Chapter 3
Using the C5P Board
This chapter provides how to instructions to use the board and describes the peripherals.
3.1 Configuring the Cyclone V FPGA
There are two types of programming method supported by C5P:
1. JTAG programming：It is named after the IEEE standards Joint Test Action Group.
The configuration bitstream is downloaded directly into the Cyclone V FPGA. The
FPGA will retain its current status as long as power is applied to the board; the
configuration information will be lost when the power is off.
2. AS programming：The other programming method is Active Serial configuration. The
configuration bitstream is downloaded into the Intel FPGA EPCQ256 device, which
provides non-volatile storage for the bit stream. The information is retained within
EPCQ256 even if the C5P board is turned off. When the board is powered on, the
configuration data in the EPCQ256 device is automatically loaded into the Cyclone V
FPGA.
JTAG Chain on C5P Board
The FPGA device can be configured through JTAG interface on the C5P board, but the
JTAG chain must form a closed loop, which allows a Quartus II programmer to the detect
FPGA device.
Figure 3‑1 illustrates the JTAG chain on C5P board.
Figure 3‑1 Path of the JTAG chain

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Configure the FPGA in JTAG Mode
There is one FPGA device on the JTAG chain. The following shows how the FPGA is
programmed in JTAG mode step by step.
1. Open the Quartus II programmer under Quartus Prime Tools and click “Auto Detect”,
as circled in Figure 3‑2.
Figure 3‑2 Detect FPGA device in JTAG mode
2. Select detected device associated with the board, as circled in Figure 3‑3.

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Figure 3‑3 Select 5CGXFC9D6
3. The FPGA is detected, as shown in Figure 3‑4.
Figure 3‑4 FPGA detected in Quartus programmer
4. Right click on the FPGA device and select Change File to open the .sof file to be
programmed, as highlighted in Figure 3‑5.
Figure 3‑5 Open the .sof file to be programmed into the FPGA device
5. Select the .sof file to be programmed, as shown in Figure 3‑6.

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Figure 3‑6 Select the .sof file to be programmed into the FPGA device
6. Click “Program/Configure” check box and then click “Start” button to download the .sof
file into the FPGA device, as shown in Figure 3‑7.
Figure 3‑7 Program .sof file into the FPGA device
Configure the FPGA in AS Mode
The C5P board uses the EPCSQ256 device to store configuration data for the
Cyclone V FPGA. This configuration data is automatically loaded from the quad
serial configuration device chip into the FPGA when the board is powered up

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Users need to use Serial Flash Loader (SFL) to program the EPCQ256 device
via JTAG interface.
The FPGA-based SFL is a soft intellectual property (IP) core within the FPGA
that bridges the JTAG and Flash interfaces. The SFL Megafunction is available
in Quartus Prime. Figure 3 ‑8 shows the programming method when
adopting SFL solution.
Please refer to Chapter 6 Program the EPCQ for the basic programming
instructions on the serial configuration device.
Figure 3‑8 Programming a quad serial configuration device with SFL solution
3.2 Board Status Elements
In addition to the 4 LEDs that the FPGA device can control, there are 4 indicators which
can indicate the board status, as shown in Figure 3‑9, please refer the details in Table 3
‑1.
Figure 3‑9 LED Indicators on C5P

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Table 3‑1 LED Indicators
LED Name
Signal Name
Description
D3
12V Power
Illuminates when 12V power is active
D43
JTAG_RX
Illuminates when USB Blaster II receives data
D44
JTAG_TX
Illuminates when USB Blaster II transmits data
D42
CONF_DONE
Illuminates when FPGA is configured successfully
3.3 Clock Circuitry
Figure 3-10 shows the default frequency of all external clocks to the Cyclone V FPGA.
The 50MHz is generated by a crystal oscillator. The 50MHz clock signals connected to the
FPGA are used as clock sources for user logic. The board also includes two SMA
connectors which can be used to connect an external clock source to the board or to drive
a clock signal in/out through the SMA connector. All these clock inputs are connected to
the phase locked loops (PLL) clock input pins of the FPGA to allow users to use these
clocks as a source clock for the PLL circuit.
The associated pin assignment for clock inputs to FPGA I/O pins is listed in Table 3‑2.
Figure 3-10 Block diagram of the clock distribution on C5P
Table 3‑2 Pin Assignment of Clock Inputs
Signal Name
FPGA Pin
No.
Direction
Description
I/O Standard
CLOCK_50_B3B
PIN_T13
Input
50MHz clock input (Bank 3B)
1.5 V
CLOCK_50_B4A
PIN_U12
Input
50MHz clock input (Bank 4A)
1.5 V
CLOCK_50_B5B
PIN_R20
Input
50MHz clock input (Bank 5B)
3.3-V LVTTL
CLOCK_50_B6A
PIN_N20
Input
50MHz clock input (Bank 6A)
3.3-V LVTTL
CLOCK_50_B7A
PIN_H12
Input
50MHz clock input (Bank 7A)
3.3-V LVTTL

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CLOCK_50_B8A
PIN_N9
Input
50MHz clock input (Bank 8A)
3.3-V LVTTL
SMA_CLKIN
PIN_T21
Input
Externa（SMA) clock input
3.3-V LVTTL
SMA_CLKOUT
PIN_Y25
Output
Externa (SMA) clock output
3.3-V LVTTL
3.4 Peripherals Connected to the FPGA
This section describes the interfaces connected to the FPGA. Users can control or monitor
different interfaces with user logic from the FPGA.
3.4.1 User Push-buttons, Switches and LEDs
The board has four push-buttons connected to the FPGA, as shown in Figure 3-11.
Schmitt trigger circuit is implemented and acts as a switch debounce in Figure 3-12 for
the push-buttons connector. The four push-buttons are named KEY0, KEY1, KEY2, and
KEY3; they are coming out of the Schmitt trigger device and are connected directly to the
Cyclone V FPGA. The push-button generates a high logic level when it is not pressed and
provides a low logic level when pressed. Since the push-buttons are debounced, they can
be used as reset inputs in a circuit.
Figure 3-11 Connections between the push-buttons and the Cyclone V FPGA
Figure 3-12 Switch debouncing
Pushbutton releasedPushbutton depressed
Before
Debouncing
Schmitt Trigger
Debounced

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There are four slide switches connected to the FPGA, as shown in Figure 3-13. These
switches are not debounced and are to be used as level-sensitive data inputs to a circuit.
Each switch is connected directly and individually to the FPGA. When the switch is set to
the DOWN position (towards the edge of the board), it generates a low logic level to the
FPGA. When the switch is set to the UP position, a high logic level is generated to the
FPGA.
.
Figure 3-13 Connections between the slide switches and Cyclone V FPGA
There are also four user-controllable LEDs connected to the FPGA. Each LED is driven
directly and individually by the Cyclone V FPGA; driving its associated pin to a high logic
level or low level to turn the LED on or off, respectively. Figure 3-14 shows the connections
between LEDs and Cyclone V FPGA. Table 3‑3、Table 3‑4 and Table 3‑5 list the pin
assignment of user push-buttons, switches, and LEDs.

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Figure 3-14 Connections between the LEDs and the Cyclone V FPGA
Table 3‑3 Pin Assignment of Slide Switches
Switch Name
FPGA Pin No.
Direction
Description
I/O Standard
SW[0]
PIN_G20
Input
Slide Switch [0]
3.3-V LVTTL
SW[1]
PIN_F21
Input
Slide Switch [1]
3.3-V LVTTL
SW[2]
PIN_E21
Input
Slide Switch [2]
3.3-V LVTTL
SW[3]
PIN_H19
Input
Slide Switch [3]
3.3-V LVTTL
Table 3‑4 Pin Assignment of Push-buttons
Key Name
FPGA Pin No.
Direction
Description
I/O
Standard
CPU_RESET_n
PIN_AB24
Input
Generate a high logic level when
it is not pressed
3.3-V
LVTTL
KEY[0]
PIN_M21
Input
Generate a high logic level when
it is not pressed. Four push-
buttons (KEY0, KEY1, KEY2 and
KEY3) are debounced.
3.3-V
LVTTL
KEY[1]
PIN_K25
Input
3.3-V
LVTTL
KEY[2]
PIN_K26
Input
3.3-V
LVTTL
KEY[3]
PIN_G26
Input
3.3-V
LVTTL

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Table 3‑5 LED Pin Assignment of LEDs
LED
Name
FPGA Pin No.
Direction
Description
I/O
Standard
LED[0]
PIN_U20
Output
Drive high logic 1 to I/O pin to
turn the LED on.
Drive lowh logic 0 to I/O pin to
turn the LED off.
3.3-V
LVTTL
LED[1]
PIN_T19
Output
3.3-V
LVTTL
LED[2]
PIN_Y24
Output
3.3-V
LVTTL
LED[3]
PIN_Y23
Output
3.3-V
LVTTL
3.4.2 7-Segment Displays
C5P board has two 7-segment displays. Figure 3-15 shows the connection of seven
segments (common anode) to pins on Cyclone V FPGA。The segment can be turned on
or off by applying a low logic level or high logic level from the FPGA, respectively. Each
segment in a display is indexed from 0 to 6, with corresponding positions given in Figure
3-15. Table 3‑6 shows the pin assignment of FPGA to the 7-segment displays.
Figure 3-15 Connections between the 7-segment displays and Cyclone V FPGA
Table 3‑6 Pin Assignment of 7-segment Displays
HEX Name
FPGA Pin
No.
Direction
Description
I/O
Standard
HEX0_DP
PIN_AA6
Input
Seven Segment Digit 0 DP
3.3-V
LVTTL
HEX0[0]
PIN_T8
Input
Seven Segment Digit 0[0]
3.3-V
LVTTL
HEX0[1]
PIN_P26
Input
Seven Segment Digit 0[1]
3.3-V