Terasic ALTERA TR5-F40W User manual

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CONTENTS
CHAPTER 1 OVERVIEW ..........................................................................................................................................4
1.1 GENERAL DESCRIPTION ............................................................................................................................................4
1.2 KEY FEATURES..........................................................................................................................................................4
1.3 BLOCK DIAGRAM......................................................................................................................................................6
CHAPTER 2 BOARD COMPONENTS ....................................................................................................................9
2.1 BOARD OVERVIEW....................................................................................................................................................9
2.2 CONFIGURATION,STATUS AND SETUP .....................................................................................................................10
2.3 GENERAL USER INPUT/OUTPUT ..............................................................................................................................15
2.4 TEMPERATURE SENSOR AND FAN CONTROL............................................................................................................17
2.5 CLOCK CIRCUIT ......................................................................................................................................................18
2.6 RS422 SERIAL PORT ...............................................................................................................................................20
2.7 FLASH MEMORY ...................................................................................................................................................21
2.8 SSRAM..................................................................................................................................................................24
2.9 SPF+ PORTS............................................................................................................................................................26
2.10 PCI EXPRESS.........................................................................................................................................................29
2.11 SATA....................................................................................................................................................................31
2.12 HSMC: HIGH-SPEED MEZZANINE CARD ..............................................................................................................34
CHAPTER 3 SYSTEM BUILDER ...........................................................................................................................42
3.1 INTRODUCTION .......................................................................................................................................................42
3.2 GENERAL DESIGN FLOW.........................................................................................................................................43
3.3 USING SYSTEM BUILDER ........................................................................................................................................44
CHAPTER 4 FLASH PROGRAMMING .................................................................................................................51
4.1 CFI FLASH MEMORY MAP ......................................................................................................................................51
4.2 FPGACONFIGURE OPERATION ...............................................................................................................................52
4.3 FLASH PROGRAMMING WITH USERS DESIGN ..........................................................................................................52
4.4 RESTORE FACTORY SETTINGS .................................................................................................................................54
CHAPTER 5 PROGRAMMABLE OSCILLATOR .................................................................................................56
5.1 OVERVIEW ..............................................................................................................................................................56
5.2 SI570 EXAMPLE (RTL) ...........................................................................................................................................60

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5.3 SI570AND CDCM PROGRAMMING (NIOS II)..........................................................................................................68
ADDITIONAL INFORMATION .....................................................................................................................................73

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Chapter 1
Overview
This chapter provides an overview of the TR5-F40W Development Board and installation guide.
1
1. .1 1 G Ge en ne er ra al l D De es sc cr ri ip pt ti io on n
The Terasic TR5-F40W Stratix V GX FPGA Development Kit provides the ideal hardware platform
for developing high-performance and high-bandwidth application. With a standard-height,
half-length form-factor package, the TR5-F40W is designed for the most demanding high-end
applications, empowered with the top-of-the-line Altera Stratix V GX, delivering the best
system-level integration and flexibility in the industry.
The Stratix® V GX FPGA features 340K logic elements and integrated transceivers that transfer at
a maximum of 12.5 Gbps, allowing the TR5-F40W to be fully compliant with version 3.0 of SATA,
version 3.0 of the PCI Express standard, as well as allowing an ultra low-latency, straight
connections to four external 10G SFP+ modules. Not relying on an external PHY will accelerate
mainstream development of network applications enabling customers to deploy designs for a broad
range of high-speed connectivity applications. An HSMC expansion port also allows users to
connect custom daughter cards such as those found on cards.terasic.com. The feature-set of the
TR5-F40W fully supports all high-intensity applications such as low-latency trading, cloud
computing, high-performance computing, data acquisition, network processing, and signal
processing.
1
1. .2 2 K Ke ey y F Fe ea at tu ur re es s
The following hardware is implemented on the TR5-F40W board:
FPGA
oAltera Stratix® V GX FPGA (5SGXEA3K2F40C3)

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FPGA Configuration
oOn-Board USB Blaster II or JTAG header for FPGA programming
oFast passive parallel (FPPx32) configuration via MAX II CPLD and flash memory
General user input/output:
o10 LEDs
o4 push-buttons
o4 slide switches
On-Board Clock
o50MHz Oscillator
oProgrammable oscillators Si570 and CDCM61004
oSMA connector for external clock input / output
Memory
oSSRAM
oFLASH
Communication Ports
oFour SFP+ connectors
oOne SATA host port
oOne SATA device port
oPCI Express (PCIe) x8 edge connector
oOne RS422 transceiver with RJ45 connector
oOne HSMC Connector
System Monitor and Control
oTemperature sensor
oFan control
Power
oPCI Express 6-pin power connector, 12V DC Input
oPCI Express edge connector power
Mechanical Specification

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oPCI Express standard-height and half-length
1
1. .3 3 B Bl lo oc ck k D Di ia ag gr ra am m
Figure 1-1 shows the block diagram of the TR5-F40W board. To provide maximum flexibility for
the users, all key components are connected with the Stratix V GX FPGA device. Thus, users can
configure the FPGA to implement any system design.
Figure 1-1 Block diagram of the TR5-F40W board
Stratix V GX FPGA
5SGXEA3K2F40C3
340,000 logic elements (LEs)
19-Mbits embedded memory
36 transceivers (12.5Gbps)
512 18-bit x 18-bit multipliers
256 27-bit x 27-bit DSP blocks
2 PCI Express hard IP blocks

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696 user I/Os
174 full-duplex LVDS channels
24 phase locked loops (PLLs)
JTAG Header and FPGA Configuration
On-board USB Blaster II or JTAG header for use with the Quartus II Programmer
MAXII CPLD EPM2210 System Controller and Fast Passive Parallel (FPP) configuration
Memory devices
2MB SSRAM
256MB FLASH
General user I/O
10 user controllable LEDs
4 user push buttons
4 user slide switches
On-Board Clock
50MHz oscillator
Programmable oscillators providing clock for 10G SFP+ transceiver
Programmable oscillators providing clock for SATA, HSMC and 1G SFP+ transceiver
1 SMA connector for external clock output
1 SMA connector for external clock input
HSMC Connector
Total of 8 pairs transceivers at data rate up to 12.5Gbps
Total of 18 LVDS channels (also can be configured as single-end signals)
Input and output clock

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JTAG Signals
Adjustable I/O voltage 1.5V / 1.8V / 2.5V
Two Serial ATA ports
SATA 3.0 standard at 6Gbps signaling rate
Four SFP+ ports
Four SFP+ connector (10 Gbps+)
PCI Express x8 edge connector
Support for PCIe Gen1/2/3
Edge connector for PC motherboard with x8 or x16 PCI Express slot
Power Source
PCI Express 6-pin DC 12V power
PCI Express edge connector power

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Chapter 2
Board Components
This chapter introduces all the important components on the TR5-F40W.
2
2. .1 1 B Bo oa ar rd d O Ov ve er rv vi ie ew w
Figure 2-1 is the top and bottom view of the TR5-F40W development board. It depicts the layout of
the board and indicates the location of the connectors and key components. Users can refer to this
figure for relative location of the connectors and key components.
Figure 2-1 The FPGA Board (Top)

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Figure 2-2 The FPGA Board (Bottom)
2
2. .2 2 C Co on nf fi ig gu ur ra at ti io on n, , S St ta at tu us s a an nd d S Se et tu up p
Configure
The FPGA board supports two configuration methods for the Stratix V FPGA:
Configure the FPGA using the on-board USB-Blaster II.
Flash memory configuration of the FPGA using stored images from the flash memory on
power-up.
For programming via on-board USB-Blaster II, the following procedures show how to download a
configuration bit stream into the Stratix V GX FPGA:
Make sure that power is provided to the FPGA board
Connect your PC to the FPGA board using a mini-USB cable and make sure the USB-Blaster II
driver is installed on your PC.
Launch Quartus II programmer and make sure the USB-Blaster II is detected.
In Quartus II Programmer, add the configuration bit stream file (.sof), check the associated

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“Program/Configure”item, and click “Start”to start FPGA programming.
Status LED
The FPGA Board development board includes board-specific status LEDs to indicate board status.
Please refer to Table 2-1 for the description of the LED indicator.
Table 2-1 Status LED
Board
Reference
LED Name
Description
D7
12-V Power
Illuminates when 12-V power is active.
D6
3.3-V Power
Illuminates when 3.3-V power is active.
D25
HSMC Power
1.5-V : no Illuminates
1.8-V : Illuminates Green
2.5-V : Illuminates Red (Default)
D19
CONF DONE
Illuminates when the FPGA is successfully configured.
Driven by the MAX II CPLD EPM2210 System Controller.
D15
Loading
Illuminates when the MAX II CPLD EPM2210 System
Controller is actively configuring the FPGA. Driven by the
MAX II CPLD EPM2210 System Controller with the Embedded
Blaster CPLD.
D17
Error
Illuminates when the MAX II CPLD EPM2210 System
Controller fails to configure the FPGA. Driven by the MAX II
CPLD EPM2210 System Controller.
D18
PAGE
Illuminates when FPGA is configured by the factory
configuration bit stream.
Setup HSMC I/O voltage
The FPGA I/O standards of the HSMC ports can be adjusted by configuring the header position (J3).
Each port can be individually adjusted to 1.5V, 1.8V, 2.5V via jumpers on the top-right. Figure 2-3
depicts the position of the jumpers and their associated I/O standards. Users can use 2-pin jumpers
to configure the I/O standard by choosing the associated positions on the header. Please refer to
Table 2-2 for more details. Note: removing or mounting all of the jumpers will force an output of
1.5V, and will incur the risk of damaging your FPGA.

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Figure 2-3 HSMC I/O Configuration Header
Table 2-2 HSMC IO Standard Select
Board
Reference
Signal Name
Description
Default
J3.1 –J3.2
HSMC VCCIO 1.5V
Short : Select VCCIO = 1.5V output
Open
J3.3 –J3.4
HSMC VCCIO 1.8V
Short : Select VCCIO = 1.8V output
Open
J3.5 –J3.6
HSMC VCCIO 2.5V
Short : Select VCCIO = 2.5V output
Short
J3.7 –J3.8
HSMC VCCIO 1.5V
Short : Select VCCIO = 1.5V output
Open
Setup PCI Express Control DIPswitch
The PCI Express Control DIP switch (SW8) is provided to enable or disable different
configurations of the PCIe Connector. Table 2-3 lists the switch controls and description.
Table 2-3 SW8 PCIe Control DIPSwitch
Board
Reference
Signal Name
Description
Default
SW8.1
PCIE_PRSNT2n_x1
On : Enable x1 presence detect
Off : Disable x1 presence detect
Off
SW8.2
PCIE_PRSNT2n_x4
On : Enable x4 presence detect
Off : Disable x4 presence detect
Off
SW8.3
PCIE_PRSNT2n_x8
On : Enable x8 presence detect
Off : Disable x8 presence detect
On

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Setup Configure Mode Control DIP switch
The Configure Mode Control DIP switch (SW7) is provided to specify the configuration mode of
the FPGA. Because currently only one mode is supported, please set all positions as shown in
Figure 2-4.
Figure 2-4 6-Position DIP switch for Configure Mode
Select Flash Image for Configuration
The Image Select DIP switch (SW5) is provided to specify the image for configuration of the FPGA.
Setting SW5 to the top specifies the default factory image to be loaded, as shown in Figure 2-5.
Setting SW5 to low specifies the TR5-F40W to load a user-defined image, as shown in Figure 2-6.
Figure 2-5 DIP switch for Image Select –Factory Image Load

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Figure 2-6 DIP switch for Image Select –User Image Load
Select JTAG Chain DIP Switch
Table 2-4 explains the configuration for SW6. SW6.1 enables/disables the USB Blaster. SW6.3
selects the JTAG chain. A more detailed explanation can be found in Chapter 2-12 JTAG Chain on
HSMC.
Table 2-4 SW6 JTAG Chain DIP Switch
Board
Reference
Signal Name
Description
Default
SW6.1
On-Board USB Blaster
On : Disable On-Board USB Blaster
Off : Enable On-Board USB Blaster
Off
SW6.2
N/A
N/A
On
SW6.3
HSMC JTAG
On : Disable HSMC JTAG chain
Off : Enable HSMC JTAG chain
On
SW6.4
N/A
N/A
On

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Figure 2-7 SW6 4-Position JTAG Chain DIP Switch Settings
2
2. .3 3 G Ge en ne er ra al l U Us se er r I In np pu ut t/ /O Ou ut tp pu ut t
This section describes the user I/O interface to the FPGA.
User Defined Push-buttons
The FPGA board includes four user defined push-buttons that allow users to interact with the Stratix
V GX device. Each push-button provides a high logic level or a low logic level when it is not
pressed or pressed, respectively. Table 2-5 lists the board references, signal names and their
corresponding Stratix V GX device pin numbers.
Table 2-5 Push-button Pin Assignments, Schematic Signal Names, and Functions
Board
Reference
Schematic
Signal Name
Description
I/O
Standard
Stratix V GX
Pin Number
PB0
BUTTON0
High Logic Level when the button is
not pressed
2.5-V
PIN_C18
PB1
BUTTON1
2.5-V
PIN_B19
PB2
BUTTON2
2.5-V
PIN_B17
PB3
BUTTON3
2.5-V
PIN_A17
User-Defined Slide Switch
There are four slide switches on the FPGA board to provide additional FPGA input control. When a

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slide switch is in the DOWN position or the UPPER position, it provides a low logic level or a high
logic level to the Stratix V GX FPGA, respectively, as shown in Figure 2-8.
Figure 2-8 4-Position Slide switches
Table 2-6 lists the signal names and their corresponding Stratix V GX device pin numbers.
Table 2-6 Slide Switch Pin Assignments, Schematic Signal Names, and Functions
Board
Reference
Schematic
Signal Name
Description
I/O
Standard
Stratix V GX
Pin Number
SW0
SW0
High logic level when SW in the UPPER
position.
2.5-V
PIN_F17
SW1
SW1
2.5-V
PIN_G17
SW2
SW2
2.5-V
PIN_G19
SW3
SW3
2.5-V
PIN_G16
User-Defined LEDs
The FPGA board consists of 10 user-controllable LEDs to allow status and debugging signals to be
driven to the LEDs from the designs loaded into the Stratix V GX device. Each LED is driven
directly by the Stratix V GX FPGA. The LED is turned on or off when the associated pins are

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driven to a low or high logic level, respectively. A list of the pin names on the FPGA that are
connected to the LEDs is given in Table 2-7.
Table 2-7 User LEDs Pin Assignments, Schematic Signal Names, and Functions
Board
Reference
Schematic
Signal Name
Description
I/O
Standard
Stratix V GX
Pin Number
D0
LED0
Driving a logic low on the I/O port turns the
LED ON.
Driving a logic high on the I/O port turns
the LED OFF.
2.5-V
PIN_C16
D1
LED1
2.5-V
PIN_D18
D2
LED2
2.5-V
PIN_B16
D3
LED3
2.5-V
PIN_A16
D5-1
LED_BRACKET0
2.5-V
PIN_E18
D5-3
LED_BRACKET1
2.5-V
PIN_E17
D5-5
LED_BRACKET2
2.5-V
PIN_E19
D5-7
LED_BRACKET3
2.5-V
PIN_D16
J6-10
LED_RJ45_L
2.5-V
PIN_M15
J6-12
LED_RJ45_R
2.5-V
PIN_N15
2
2. .4 4 T Te em mp pe er ra at tu ur re e S Se en ns so or r a an nd d F Fa an n C Co on nt tr ro ol l
The FPGA board is equipped with a temperature sensor, MAX1619, which provides temperature
sensing and over-temperature alert. These functions are accomplished by connecting the
temperature sensor to the internal temperature sensing diode of the Stratix V GX device. The
temperature status and alarm threshold registers of the temperature sensor can be programmed by a
two-wire SMBus, which is connected to the Stratix V GX FPGA. In addition, the 7-bit POR slave
address for this sensor is set to ‘0011000b’.
An optional 3-pin +12V fan located on J15 of the FPGA board is intended to reduce the temperature
of the FPGA. Users can control the fan to turn on/off depending on the measured system
temperature. The FAN is turned on when the FAN_CTRL pin is driven to a high logic level or
tri-state.
The pin assignments for the associated interface are listed in Table 2-8.
Table 2-8 Temperature Sensor Pin Assignments, Schematic Signal Names, and Functions
Schematic
Signal Name
Description
I/O Standard
Stratix V GX Pin
Number
TEMPDIODEp
Positive pin of temperature diode in
Stratix V
2.5-V
PIN_R6

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TEMPDIODEn
Negative pin of temperature diode in
Stratix V
2.5-V
PIN_P5
TEMP_CLK
SMBus clock
2.5-V
PIN_AM17
TEMP_DATAT
SMBus data
2.5-V
PIN_AN17
TEMP_OVERT_n
SMBus alert (interrupt)
2.5-V
PIN_AR17
TEMP_INT_n
SMBus alert (interrupt)
2.5-V
PIN_AT17
FAN_CTRL
Fan control
2.5-V
PIN_AW16
2
2. .5 5 C Cl lo oc ck k C Ci ir rc cu ui it t
The development board includes one 50 MHz and two programmable oscillators.Figure 2-9 shows
the default frequencies of on-board all external clocks going to the Stratix V GX FPGA. The figures
also show an off-board external clock from PCI Express Host to the FPGA. Lastly, there is an SMA
connector for clock input, and an SMAconnector for clock output.
Figure 2-9 Clock Circuit of the FPGA Board
A clock buffer is used to duplicate the 50 MHz oscillator, so each bank of FPGA I/O bank 3/4/7/8
has two clock inputs. The two programming oscillators are low-jitter oscillators which are used to
provide special and high quality clock signals for high-speed transceivers. Figure 2-10 shows the

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control circuits of programmable oscillators. The CDCM61004 oscillator can be programmed to
generate a desired reference clock for the 1G Ethernet SFP+ transceiver, SATA Host/Device
transceiver and eight transceivers in the HSMC connector. The Si570 programmable oscillator is
programmed via an I2C serial interface to generate the reference clock for 10G Ethernet SFP+
transceiver.
Figure 2-10 Control Circuits of Programmable Oscillators
Table 2-9 lists the clock source, signal names, default frequency and their corresponding Stratix V
GX device pin numbers.
Table 2-9 Clock Source, Signal Name, Default Frequency, PinAssignments and Functions
Source
Schematic
Signal Name
Default
Frequency
I/O Standard
Stratix V GX
Pin Number
Application
Y3
OSC_50_B3B
50.0 MHz
2.5-V
PIN_AV29
OSC_50_B3D
2.5-V
PIN_AK23
OSC_50_B4A
2.5-V
PIN_AL7
OSC_50_B4D
2.5-V
PIN_AF17
OSC_50_B7A
2.5-V
PIN_G7
OSC_50_B7D
2.5-V
PIN_P16
OSC_50_B8A
1.5-V/1.8-V/2.5-V
PIN_E34
OSC_50_B8D
1.5-V/1.8-V/2.5-V
PIN_J23

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U10
SFP_REFCLK_p
100.0 MHz
HCSL
PIN_AF6
10G SFP+
U27
SFP1G_REFCLK_p
125.0 MHz
HCSL
PIN_AB6
1G SFP+
U27
SATA_REFCLK_p
125.0 MHz
HCSL
PIN_V6
SATA
U27
HSMC_REFCLK_p
125.0 MHz
HCSL
PIN_V34
HSMC XCVR
J15
PCIE_REFCLK_p
From Host
HCSL
PIN_AF34
PCI Express
J12
SMA_CLKIN
User input
2.5-V
PIN_U15
J14
SMA_CLKOUT
User output
2.5-V
PIN_AD30
Table 2-10 lists the programmable oscillator control pins, signal names, I/O standard and their
corresponding Stratix V GX device pin numbers.
Table 2-10 Programmable oscillator control pin, Signal Name, I/O standard, Pin Assignments
and Descriptions
Programmable
Oscillator
Schematic
Signal Name
I/O Standard
Stratix V GX Pin
Number
Description
Si570
(U10)
CLOCK_SCL
2.5-V
PIN_AD15
I2C bus, direct connected
with Si570
CLOCK_SDA
2.5-V
PIN_AD16
CDCM61004
(U27)
CLK_RST_n
2.5-V
PIN_AC15
Device reset (active low)
CLK_CE
2.5-V
PIN_AH15
Chip enable
CLK_PR0
2.5-V
PIN_AB16
Output divider control
CLK_PR1
2.5-V
PIN_AJ15
Output divider control
CLK_OS0
2.5-V
PIN_AG14
Output type select
CLK_OS1
2.5-V
PIN_AG15
Output type select
CLK_OD0
2.5-V
PIN_AB15
Output divider control
CLK_OD1
2.5-V
PIN_AA15
Output divider control
CLK_OD2
2.5-V
PIN_AA14
Output divider control
2
2. .6 6 R RS S4 42 22 2 S Se er ri ia al l P Po or rt t
The RS422 is designed to perform communication between boards, allowing a transmission speed
of up to 20 Mbps. Figure 2-11 shows the RS422 block diagram of the development board. The
full-duplex LTC2855 is used to translate the RS422 signal, and the RJ45 is used as an external
connector for the RS422 signal.