Terasic DE5-Net User manual

DE5-Net User Manual
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August 4, 2017
1

DE5-Net User Manual
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August 4, 2017
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CONTENTS
CHAPTER 1 OVERVIEW ........................................................................................................................................4
1.1 GENERAL DESCRIPTION ............................................................................................................................................4
1.2 KEY FEATURES..........................................................................................................................................................5
1.3 BLOCK DIAGRAM......................................................................................................................................................6
CHAPTER 2 BOARD COMPONENTS ..................................................................................................................10
2.1 BOARD OVERVIEW..................................................................................................................................................10
2.2 CONFIGURATION,STATUS AND SETUP .....................................................................................................................11
2.3 GENERAL USER INPUT/OUTPUT ..............................................................................................................................14
2.4 TEMPERATURE SENSOR AND FAN CONTROL............................................................................................................17
2.5 CLOCK CIRCUIT ......................................................................................................................................................18
2.6 RS-422 SERIAL PORT..............................................................................................................................................21
2.7 FLASH MEMORY ...................................................................................................................................................22
2.8 DDR3 SO-DIMM...................................................................................................................................................25
2.9 QDRII+ SRAM ......................................................................................................................................................32
2.10 SPF+ PORTS..........................................................................................................................................................39
2.11 PCI EXPRESS.........................................................................................................................................................42
2.12 SATA....................................................................................................................................................................44
CHAPTER 3 SYSTEM BUILDER .........................................................................................................................48
3.1 INTRODUCTION .......................................................................................................................................................48
3.2 GENERAL DESIGN FLOW.........................................................................................................................................49
3.3 USING SYSTEM BUILDER ........................................................................................................................................50
CHAPTER 4 FLASH PROGRAMMING .................................................................................................................57
4.1 CFI FLASH MEMORY MAP ......................................................................................................................................57
4.2 FPGACONFIGURE OPERATION ...............................................................................................................................58
4.3 FLASH PROGRAMMING WITH USERS DESIGN ..........................................................................................................58
4.4 RESTORE FACTORY SETTINGS .................................................................................................................................60
CHAPTER 5 PROGRAMMABLE OSCILLATOR .................................................................................................62
5.1 OVERVIEW ..............................................................................................................................................................62
5.2 SI570 EXAMPLE BY RTL.........................................................................................................................................66

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5.3 SI570AND CDCM PROGRAMMING BY NIOS II........................................................................................................73
CHAPTER 6 MEMORY REFERENCE DESIGN ..................................................................................................78
6.1 QDRII+ SRAM TEST .............................................................................................................................................78
6.2 DDR3 SDRAM TEST .............................................................................................................................................81
6.3 DDR3 SDRAM TEST BY NIOS II............................................................................................................................83
CHAPTER 7 PCI EXPRESS REFERENCE DESIGN .......................................................................................87
7.1 PCI EXPRESS SYSTEM INFRASTRUCTURE................................................................................................................87
7.2 FPGAPCI EXPRESS SYSTEM DESIGN.....................................................................................................................88
7.3 PC PCI EXPRESS SYSTEM DESIGN ..........................................................................................................................93
7.4 FUNDAMENTAL COMMUNICATION.........................................................................................................................105
7.5 EXAMPLE 2: IMAGE PROCESS APPLICATION..........................................................................................................110
CHAPTER 8 TRANSCEIVER VERIFICATION .................................................................................................. 115
8.1 TEST CODE............................................................................................................................................................ 115
8.2 LOOPBACK FIXTURE .............................................................................................................................................115
8.3 TESTING................................................................................................................................................................ 117
ADDITIONAL INFORMATION ................................................................................................................................... 119

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Chapter 1
Overview
This chapter provides an overview of the DE5-Net Development Board and installation guide.
1
1. .1 1 G Ge en ne er ra al l D De es sc cr ri ip pt ti io on n
The Terasic DE5-Net Stratix V GX FPGA Development Kit provides the ideal hardware solution
for designs that demand high capacity and bandwidth memory interfacing, ultra-low latency
communication, and power efficiency. With a full-height, 3/4-length form-factor package, the
DE5-Net is designed for the most demanding high-end applications, empowered with the
top-of-the-line Altera Stratix V GX, delivering the best system-level integration and flexibility in
the industry.
The Stratix® V GX FPGA features integrated transceivers that transfer at a maximum of 12.5 Gbps,
allowing the DE5-Net to be fully compliant with version 3.0 of the PCI Express standard, as well as
allowing an ultra low-latency, straight connections to four external 10G SFP+ modules. Not relying
on an external PHY will accelerate mainstream development of network applications enabling
customers to deploy designs for a broad range of high-speed connectivity applications. For designs
that demand high capacity and high speed for memory and storage, the DE5-Net delivers with two
independent banks of DDR3 SO-DIMM RAM, four independent banks of QDRII+ SRAM,
high-speed parallel flash memory, and four SATA ports. The feature-set of the DE5-Net fully
supports all high-intensity applications such as low-latency trading, cloud computing,
high-performance computing, data acquisition, network processing, and signal processing.

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1
1. .2 2 K Ke ey y F Fe ea at tu ur re es s
The following hardware is implemented on the DE5-Net board:
FPGA
Altera Stratix® V GX FPGA (5SGXEA7N2F45C2)
FPGA Configuration
On-Board USB Blaster II or JTAG header for FPGA programming
Fast passive parallel (FPPx32) configuration via MAX II CPLD and flash memory
General user input/output:
10 LEDs
4 push-buttons
4 slide switches
2 seven-segment displays
Clock System
50MHz Oscillator
Programmable oscillators Si570, CDCM61001 and CDCM61004
One SMA connector for external clock input
One SMA connector for clock output
Memory
DDR3 SO-DIMM SDRAM
QDRII+ SRAM
FLASH
Communication Ports
Four SFP+ connectors
Two Serial ATA host ports
Two Serial ATA device ports
PCI Express (PCIe) x8 edge connector
One RS422 transceiver with RJ45 connector

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System Monitor and Control
Temperature sensor
Fan control
Power
PCI Express 6-pin power connector, 12V DC Input
PCI Express edge connector power
Mechanical Specification
PCI Express full-height and 3/4-length
1
1. .3 3 B Bl lo oc ck k D Di ia ag gr ra am m
94H94HFigure 1-1 shows the block diagram of the DE5-Net board. To provide maximum flexibility for the
users, all key components are connected with the Stratix V GX FPGA device. Thus, users can
configure the FPGA to implement any system design.

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Figure 1-1 Block diagram of the DE5-Net board
Below is more detailed information regarding the blocks in Figure 1-1.
Stratix V GX FPGA
5SGXEA7N2F45C2
622,000 logic elements (LEs)
50-Mbits embedded memory
48 transceivers (12.5Gbps)
512 18-bit x 18-bit multipliers
256 27-bit x 27-bit DSP blocks

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2 PCI Express hard IP blocks
840 user I/Os
210 full-duplex LVDS channels
28 phase locked loops (PLLs)
JTAG Header and FPGA Configuration
On-board USB Blaster II or JTAG header for use with the Quartus II Programmer
MAXII CPLD EPM2210 System Controller and Fast Passive Parallel (FPP) configuration
Memory devices
32MB QDRII+ SRAM
Up to 8GB DDR3 SO-DIMM SDRAM
256MB FLASH
General user I/O
10 user controllable LEDs
4 user push buttons
4 user slide switches
2 seven-segment displays
On-Board Clock
50MHz oscillator
Programming PLL providing clock for 10G SFP+ transceiver
Programming PLL providing clock for SATA or 1G SFP+ transceiver
Four Serial ATA ports
SATA 3.0 standard at 6Gbps signaling rate

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Four SFP+ ports
Four SFP+ connector (10 Gbps+)
PCI Express x8 edge connector
Support for PCIe Gen1/2/3
Edge connector for PC motherboard with x8 or x16 PCI Express slot
Power Source
PCI Express 6-pin DC 12V power
PCI Express edge connector power

10
Chapter 2
Board Components
This chapter introduces all the important components on the DE5-Net.
2
2. .1 1 B Bo oa ar rd d O Ov ve er rv vi ie ew w
Figure 2-1 is the top and bottom view of the DE5-Net development board. It depicts the layout of
the board and indicates the location of the connectors and key components. Users can refer to this
figure for relative location of the connectors and key components.
Figure 2-1 FPGA Board (Top)

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Figure 2-2 FPGA Board (Bottom)
2
2. .2 2 C Co on nf fi ig gu ur ra at ti io on n, , S St ta at tu us s a an nd d S Se et tu up p
Configure
The FPGA board supports two configuration methods for the Stratix V FPGA:
Configure the FPGA using the on-board USB-Blaster II.
Flash memory configuration of the FPGA using stored images from the flash memory on
power-up.
For programming by on-board USB-Blaster II, the following procedures show how to download a
configuration bit stream into the Stratix V GX FPGA:
Make sure that power is provided to the FPGA board
Connect your PC to the FPGA board using a mini-USB cable and make sure the USB-Blaster
II driver is installed on PC.
Launch Quartus II programmer and make sure the USB-Blaster II is detected.
In Quartus II Programmer, add the configuration bit stream file (.sof), check the associated
“Program/Configure”item, and click “Start”to start FPGA programming.

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Status LED
The FPGA Board development board includes board-specific status LEDs to indicate board status.
Please refer to Table 2-1 for the description of the LED indicator.
Table 2-1 Status LED
Board
Reference
LED Name
Description
D2
12-V Power
Illuminates when 12-V power is active.
D1
3.3-V Power
Illuminates when 3.3-V power is active.
D15
CONF DONE
Illuminates when the FPGA is successfully configured.
Driven by the MAX II CPLD EPM2210 System Controller.
D16
Loading
Illuminates when the MAX II CPLD EPM2210 System
Controller is actively configuring the FPGA. Driven by the
MAX II CPLD EPM2210 System Controller with the
Embedded Blaster CPLD.
D17
Error
Illuminates when the MAX II CPLD EPM2210 System
Controller fails to configure the FPGA. Driven by the MAX II
CPLD EPM2210 System Controller.
D18
PAGE
Illuminates when FPGA is configured by the factory
configuration bit stream.
Setup PCI Express Control DIPswitch
The PCI Express Control DIP switch (SW7) is provided to enable or disable different
configurations of the PCIe Connector. Table 2-2 lists the switch controls and description.
Table 2-2 SW3 PCIe Control DIPSwitch
Board
Reference
Signal Name
Description
Default
SW7.1
PCIE_PRSNT2n_x1
On : Enable x1 presence detect
Off: Disable x1 presence detect
Off
SW7.2
PCIE_PRSNT2n_x4
On : Enable x4 presence detect
Off: Disable x4 presence detect
Off
SW7.3
PCIE_PRSNT2n_x8
On : Enable x8 presence detect
Off: Disable x8 presence detect
On

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Setup Configure Mode Control DIP switch
The Configure Mode Control DIP switch (SW6) is provided to specify the configuration mode of
the FPGA. As currently only one mode is supported, please set all positions as shown in 9Figure 2-3.
Figure 2-3 6-Position DIP switch for Configure Mode
Select Flash Image for Configuration
The Image Select DIP switch (SW5) is provided to specify the image for configuration of the FPGA.
Setting Position 2 of SW5 to high (right) specifies the default factory image to be loaded, as shown
in Figure 2-4. Setting Position 2 of SW5 to low (left) specifies the DE5-Net to load a user-defined
image, as shown in 1Figure 2-5.
Figure 2-4 2-position DIP switch for Image Select –Factory Image Load

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Figure 2-5 2-position DIP switch for Image Select –User Image Load
2
2. .3 3 G Ge en ne er ra al l U Us se er r I In np pu ut t/ /O Ou ut tp pu ut t
This section describes the user I/O interface to the FPGA.
User Defined Push-buttons
The FPGA board includes four user defined push-buttons that allow users to interact with the Stratix
V GX device. Each push-button provides a high logic level or a low logic level when it is not
pressed or pressed, respectively. Table 2-3 lists the board references, signal names and their
corresponding Stratix V GX device pin numbers.
Table 2-3 Push-button Pin Assignments, Schematic Signal Names, and Functions
Board
Reference
Schematic
Signal Name
Description
I/O
Standard
Stratix V GX
Pin Number
PB6
BUTTON0
High Logic Level when the button is
not pressed
2.5-V
PIN_AK15
PB5
BUTTON1
2.5-V
PIN_AK14
PB4
BUTTON2
2.5-V
PIN_AL14
PB3
BUTTON3
2.5-V
PIN_AL15
User-Defined Slide Switch
There are four slide switches on the FPGA board to provide additional FPGA input control. When a
slide switch is in the DOWN position or the UPPER position, it provides a low logic level or a high
logic level to the Stratix V GX FPGA, respectively, as shown in 0Figure 2-6.

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Figure 2-6 4 Slide switches
Table 2-4 lists the signal names and their corresponding Stratix V GX device pin numbers.
Table 2-4 Slide Switch Pin Assignments, Schematic Signal Names, and Functions
Board
Reference
Schematic
Signal Name
Description
I/O
Standard
Stratix V GX
Pin Number
SW0
SW0
High logic level when SW in the UPPER
position.
1.8-V
PIN_B25
SW1
SW1
1.8-V
PIN_A25
SW2
SW2
1.8-V
PIN_B23
SW3
SW3
1.8-V
PIN_A23
User-Defined LEDs
The FPGA board consists of 10 user-controllable LEDs to allow status and debugging signals to be
driven to the LEDs from the designs loaded into the Stratix V GX device. Each LED is driven
directly by the Stratix V GX FPGA. The LED is turned on or off when the associated pins are
driven to a low or high logic level, respectively. A list of the pin names on the FPGA that are
connected to the LEDs is given in Table 2-5.
Table 2-5 User LEDs PinAssignments, Schematic Signal Names, and Functions
Board
Reference
Schematic
Signal Name
Description
I/O
Standard
Stratix V GX
Pin Number

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D8
LED0
Driving a logic 0 on the I/O port turns the LED
ON.
Driving a logic 1 on the I/O port turns the LED
OFF.
2.5-V
PIN_AW37
D9
LED1
2.5-V
PIN_AV37
D10
LED2
2.5-V
PIN_BB36
D11
LED3
2.5-V
PIN_BB39
D7-1
LED_BRACKET0
2.5-V
PIN_AH15
D7-3
LED_BRACKET1
2.5-V
PIN_AH13
D7-5
LED_BRACKET2
2.5-V
PIN_AJ13
D7-7
LED_BRACKET3
2.5-V
PIN_AJ14
J8-10
LED_RJ45_L
2.5-V
PIN_AG15
J8-12
LED_RJ45_R
2.5-V
PIN_AG16
7-Segment Displays
The FPGA board has two 7-segment displays. As indicated in the schematic in Figure 2-7,the
seven segments are connected to pins of the Stratix V GX FPGA. Applying a low or high logic level
to a segment will turn it on or turn it off, respectively.
Each segment in a display is identified by an index listed from 0 to 6 with the positions given in
Figure 2-8. In addition, the decimal point is identified as DP. Table 2-6 shows the mapping of the
FPGA pin assignments to the 7-segment displays.
Figure 2-7 Connection between 7-segment displays and Stratix V GX FPGA

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Figure 2-8 Position and index of each segment in a 7-segment display
Table 2-6 User LEDs PinAssignments, Schematic Signal Names, and Functions
Board
Reference
Schematic
Signal
Name
Description
I/O
Standard
Stratix V GX
Pin Number
HEX1
HEX1_D0
User-Defined 7-Segment Display. Driving logic 0 on
the I/O port turns the 7-segment signal ON. Driving
logic 1 on the I/O port turns the 7-segment signal
OFF.
1.5-V
PIN_H18
HEX1
HEX1_D1
1.5-V
PIN_G16
HEX1
HEX1_D2
1.5-V
PIN_F16
HEX1
HEX1_D3
1.5-V
PIN_A7
HEX1
HEX1_D4
1.5-V
PIN_B7
HEX1
HEX1_D5
1.5-V
PIN_C9
HEX1
HEX1_D6
1.5-V
PIN_D10
HEX1
HEX1_DP
1.5-V
PIN_E9
HEX0
HEX0_D0
1.5-V
PIN_G8
HEX0
HEX0_D1
1.5-V
PIN_H8
HEX0
HEX0_D2
1.5-V
PIN_J9
HEX0
HEX0_D3
1.5-V
PIN_K10
HEX0
HEX0_D4
1.5-V
PIN_K8
HEX0
HEX0_D5
1.5-V
PIN_K9
HEX0
HEX0_D6
1.5-V
PIN_N8
HEX0
HEX0_DP
1.5-V
PIN_P8
2
2. .4 4 T Te em mp pe er ra at tu ur re e S Se en ns so or r a an nd d F Fa an n C Co on nt tr ro ol l
The FPGA board is equipped with a temperature sensor, MAX1619, which provides temperature
sensing and over-temperature alert. These functions are accomplished by connecting the
temperature sensor to the internal temperature sensing diode of the Stratix V GX device. The
temperature status and alarm threshold registers of the temperature sensor can be programmed by a

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two-wire SMBus, which is connected to the Stratix V GX FPGA. In addition, the 7-bit POR slave
address for this sensor is set to ‘0011000b’.
An optional 3-pin +12V fan located on J15 of the FPGA board is intended to reduce the temperature
of the FPGA. Users can control the fan to turn on/off depending on the measured system
temperature. The FAN is turned on when the FAN_CTRL pin is driven to a high logic level.
The pin assignments for the associated interface are listed in Table 2-7.
Table 2-7 Temperature Sensor Pin Assignments, Schematic Signal Names, and Functions
Schematic
Signal Name
Description
I/O Standard
Stratix V GX Pin
Number
TEMPDIODEp
Positive pin of temperature diode in
Stratix V
1.8-V
PIN_P6
TEMPDIODEn
Negative pin of temperature diode in
Stratix V
1.8-V
PIN_P7
TEMP_CLK
SMBus clock
2.5-V
PIN_D21
TEMP_DATAT
SMBus data
2.5-V
PIN_D20
TEMP_OVERT_n
SMBus alert (interrupt)
2.5-V
PIN_C22
TEMP_INT_n
SMBus alert (interrupt)
2.5-V
PIN_C21
FAN_CTRL
Fan control
2.5-V
PIN_AR32
2
2. .5 5 C Cl lo oc ck k C Ci ir rc cu ui it t
The development board includes one 50 MHz and three programmable oscillators. Figure 2-9
shows the default frequencies of on-board all external clocks going to the Stratix V GX FPGA. The
figures also show an off-board external clock from PCI Express Host to the FPGA.

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Figure 2-9 Clock circuit of the FPGA Board
A clock buffer is used to duplicate the 50 MHz oscillator, so each bank of FPGA I/O bank 3/4/7/8
has two clock inputs. The three programming oscillators are low-jitter oscillators which are used to
provide special and high quality clock signals for high-speed transceivers. Figure 2-10 shows the
control circuits of programmable oscillators. The clock generator controller in the MAX II CPLD
can be used to program the CDCM61001 and CDCM61004 to generate 1G Ethernet SFP+ and
SATA reference clocks respectively. The Si570 programmable clock generator is programmed via
an I2C serial interface to generate the 10G Ethernet SFP+ reference clock. Two SMA connectors
provide external clock input and clock output respectively.

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Figure 2-10 Control circuits of Programmable Oscillators
1Table 2-8 lists the clock source, signal names, default frequency and their corresponding Stratix V
GX device pin numbers.
Table 2-8 Clock Source, Signal Name, Default Frequency, PinAssignments and Functions
Source
Schematic
Signal Name
Default
Frequency
I/O Standard
Stratix V GX Pin
Number
Application
Y4
OSC_50_B3B
50.0 MHz
2.5-V
PIN_AW35
OSC_50_B3D
1.8-V
PIN_BC28
OSC_50_B4A
1.8-V
PIN_AP10
OSC_50_B4D
1.8-V
PIN_AY18
OSC_50_B7A
1.5-V
PIN_M8
OSC_50_B7D
1.5-V
PIN_J18
OSC_50_B8A
1.5-V
PIN_R36
OSC_50_B8D
1.8-V
PIN_R25
J13
SMA_CLKIN
User
Defined
2.5V
PIN_BB33
External Clock
Input
J14
SMA_CLKOUT
User
Defined
2.5V
PIN_AV34
Clock Output
U49
SFP_REFCLK _p
100.0 MHz
LVDS
PIN_AK7
10G SFP+
U53
SFP1G_REFCLK_p
125.0 MHz
LVDS
PIN_AH6
1G SFP+
U28
SATA_HOST_REFCLK_p
125.0 MHz
LVDS
PIN_V6
SATA HOST
U28
SATA_DEVICE_REFCLK_p
125.0 MHz
LVDS
PIN_V39
SATA DEVICE
J17
PCIE_REFCLK_p
From Host
LVDS
PIN_AK38
PCI Express