Terasic DE1-SOC User manual

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CONTENTS
CHAPTER 1 DE1-SOC DEVELOPMENT KIT ........................................................................................................3
1.1 PACKAGE CONTENTS.................................................................................................................................................3
1.2 DE1-SOCSYSTEM CD..............................................................................................................................................4
1.3 GETTING HELP..........................................................................................................................................................4
CHAPTER 2 INTRODUCTION OF THE DE1-SOC BOARD .................................................................................5
2.1 LAYOUTAND COMPONENTS......................................................................................................................................5
2.2 BLOCK DIAGRAM OF THE DE1-SOCBOARD.............................................................................................................7
CHAPTER 3 USING THE DE1-SOC BOARD........................................................................................................10
3.1 BOARD SETUP.........................................................................................................................................................10
3.1.1 FPGACONFIGURATION MODE SETTING ..............................................................................................................10
3.1.2 HPS BOOTSELAND CLKSELSETTING ............................................................................................................. 11
3.2 CONFIGURING THE CYCLONE VSOCFPGA ...........................................................................................................13
3.3 BOARD STATUS ELEMENTS .....................................................................................................................................18
3.4 BOARD RESET ELEMENTS.......................................................................................................................................19
3.5 CLOCK CIRCUITRY ..................................................................................................................................................20
3.6 INTERFACE ON FPGA..............................................................................................................................................21
3.6.1 USER PUSH-BUTTONS,SWITCHES AND LEDS ON FPGA ......................................................................................22
3.6.2 USING THE 7-SEGMENT DISPLAYS ........................................................................................................................25
3.6.3 USING THE 2X20 GPIO EXPANSION HEADERS .....................................................................................................27
3.6.4 USING THE 24-BIT AUDIO CODEC.......................................................................................................................29
3.6.5 I2C MULTIPLEXER ...............................................................................................................................................30
3.6.6 VGA....................................................................................................................................................................31
3.6.7 TVDECODER.......................................................................................................................................................34
3.6.8 IR RECEIVER........................................................................................................................................................36
3.6.9 IR EMITTER LED.................................................................................................................................................36
3.6.10 SDRAM MEMORY ON FPGA.............................................................................................................................37
3.6.11 PS/2 SERIAL PORT..............................................................................................................................................39
3.6.12 A/D CONVERTER AND 2X5HEADER...................................................................................................................41
3.7 INTERFACE ON HARD PROCESSOR SYSTEM (HPS) ..................................................................................................42
3.7.1 USER PUSH-BUTTON AND LED ON HPS...............................................................................................................42
3.7.2 GIGABIT ETHERNET .............................................................................................................................................43
3.7.3 UART..................................................................................................................................................................44
3.7.4 DDR3 MEMORY ON HPS .....................................................................................................................................45
3.7.5 QSPI FLASH.........................................................................................................................................................47

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3.7.6 MICRO SD............................................................................................................................................................48
3.7.7 2-PORT USB HOST ...............................................................................................................................................49
3.7.8 G-SENSOR............................................................................................................................................................50
3.7.9 LTC CONNECTOR.................................................................................................................................................51
CHAPTER 4 DE1-SOC SYSTEM BUILDER..........................................................................................................53
4.1 INTRODUCTION .......................................................................................................................................................53
4.2 GENERAL DESIGN FLOW.........................................................................................................................................53
4.3 USING DE1-SOCSYSTEM BUILDER........................................................................................................................54
CHAPTER 5 EXAMPLES FOR FPGA....................................................................................................................60
5.1 DE1-SOCFACTORY CONFIGURATION .....................................................................................................................60
5.2AUDIO RECORDING AND PLAYING...........................................................................................................................61
5.3AKARAOKE MACHINE............................................................................................................................................64
5.4 SDRAM TEST BY NIOS II .......................................................................................................................................66
5.5 SDRAM RTLTEST.................................................................................................................................................69
5.6 TVBOX DEMONSTRATION......................................................................................................................................71
5.7 PS/2 MOUSE DEMONSTRATION ...............................................................................................................................74
5.8 IR EMITTER LEDAND RECEIVER DEMONSTRATION ...............................................................................................76
5.9ADC READING........................................................................................................................................................82
CHAPTER 6 EXAMPLES FOR HPS SOC..............................................................................................................85
6.1 HELLO PROGRAM....................................................................................................................................................85
6.2 USERS LEDAND KEY............................................................................................................................................87
6.3 I2C INTERFACED G-SENSOR....................................................................................................................................93
6.4 I2C MUX TEST.......................................................................................................................................................96
CHAPTER 7 EXAMPLES FOR USING BOTH HPS SOC AND FGPA..............................................................99
7.1 HPS CONTROL LEDAND HEX...............................................................................................................................99
CHAPTER 8 STEPS OF PROGRAMMING THE QUAD SERIAL CONFIGURATION DEVICE ...................103
8.1 BEFORE YOU BEGIN ..............................................................................................................................................103
8.2 CONVERT.SOF FILE TO .JIC FILE .......................................................................................................................103
8.3 WRITE JIC FILE INTO QUAD SERIAL CONFIGURATION DEVICE .............................................................................108
8.4 ERASE THE QUAD SERIAL CONFIGURATION DEVICE ............................................................................................. 110
CHAPTER 9 APPENDIX ....................................................................................................................................... 112
9.1 REVISION HISTORY ...............................................................................................................................................112
9.2 COPYRIGHT STATEMENT .......................................................................................................................................112

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Chapter 1
DE1-SoC
Development Kit
The DE1-SoC Development Kit presents a robust hardware design platform built around the Altera
System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded cores
with industry-leading programmable logic for ultimate design flexibility. Users can now leverage
the power of tremendous re-configurability paired with a high-performance, low-power processor
system. Altera’s SoC integrates an ARM-based hard processor system (HPS) consisting of processor,
peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth
interconnect backbone. The DE1-SoC development board includes hardware such as high-speed
DDR3 memory, video and audio capabilities, Ethernet networking, and much more.
The DE1-SoC Development Kit contains all components needed to use the board in conjunction
with a computer that runs the Microsoft Windows XP or later.
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1. .1 1 P Pa ac ck ka ag ge e C Co on nt te en nt ts s
Figure 1-1 shows a photograph of the DE1-SoC package.
Figure 1-1 The DE1-SoC package contents

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The DE1-SoC package includes:
The DE1-SoC development board
DE1-SoC Quick Start Guide
USB Cable (Type A to B) for FPGA programming and control
USB Cable (Type A to Mini-B) for UART control
DE1-SoC System CD-ROM
12V DC power adapter
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1. .2 2 D DE E1 1- -S So oC C S Sy ys st te em m C CD D
The DE1-SoC System CD containing the DE1-SoC documentation and supporting materials,
including the User Manual, System Builder, reference designs and device datasheets. User can
download this System CD form the link : http://de1-soc.terasic.com.
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1. .3 3 G Ge et tt ti in ng g H He el lp p
Here are the addresses where you can get help if you encounter any problem:
Altera Corporation
101 Innovation Drive San Jose, California, 95134 USA
Email: [email protected]
Terasic Technologies
9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
Email: [email protected]
Tel.: [phone]
Web: de1-soc.terasic.com

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Chapter 2
Introduction of the
DE1-SoC Board
This chapter presents the features and design characteristics of the board.
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2. .1 1 L La ay yo ou ut t a an nd d C Co om mp po on ne en nt ts s
A photograph of the board is shown in Figure 2-1. It depicts the layout of the board and indicates
the location of the connectors and key components.
Figure 2-1 Development Board (top view)

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Figure 2-2 Development Board (bottom view)
The DE1-SoC board has many features that allow users to implement a wide range of designed
circuits, from simple circuits to various multimedia projects.
The following hardware is provided on the board:
FPGA
Altera Cyclone® V SE 5CSEMA5F31C6N device
Altera Serial Configuration device –EPCQ256
USB Blaster II(on board) for programming; JTAG Mode
64MB SDRAM (16-bit data bus)
4 Push-buttons
10 Slide switches
10 Red user LEDs
Six 7-segment displays
Four 50MHz clock sources from clock generator
24-bit CD-quality audio CODEC with line-in, line-out, and microphone-in jacks
VGA DAC (8-bit high-speed triple DACs) with VGA-out connector
TV Decoder (NTSC/PAL/SECAM) and TV-in connector
PS/2 mouse/keyboard connector
IR receiver and IR emitter
Two 40-pin Expansion Header with diode protection
A/D Converter, 4-pin SPI interface with FPGA

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HPS (Hard Processor System)
800MHz Dual-core ARM Cortex-A9 MPCore processor
1GB DDR3 SDRAM (32-bit data bus)
1 Gigabit Ethernet PHY with RJ45 connector
2-port USB Host, Normal Type-A USB connector
Micro SD card socket
Accelerometer (I2C interface + interrupt)
UART to USB, USB Mini-B connector
Warm reset button and cold reset button
One user button and one user LED
LTC 2x7 expansion header
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2. .2 2 B Bl lo oc ck k D Di ia ag gr ra am m o of f t th he e D DE E1 1- -S So oC C B Bo oa ar rd d
Figure 2-3 gives the block diagram of the board. To provide maximum flexibility for the user, all
connections are made through the Cyclone V SoC FPGA device. Thus, the user can configure the
FPGA to implement any system design.
Figure 2-3 Board Block Diagram

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Following is more detailed information about the blocks in Figure 2-3:
F
FP PG GA A D De ev vi ic ce e
Cyclone V SoC 5CSEMA5F31 Device
Dual-coreARM Cortex-A9 (HPS)
85K Programmable Logic Elements
4,450 Kbits embedded memory
6 Fractional PLLs
2 Hard Memory Controllers
C
Co on nf fi ig gu ur ra at ti io on n a an nd d D De eb bu ug g
Quad Serial Configuration device –EPCQ256 on FPGA
On-Board USB Blaster II (Normal type B USB connector)
M
Me em mo or ry y D De ev vi ic ce e
64MB (32Mx16) SDRAM on FPGA
1GB (2x256Mx16) DDR3 SDRAM on HPS
128MB QSPI Flash on HPS
Micro SD Card Socket on HPS
C
Co om mm mu un ni ic ca at ti io on n
Two Port USB 2.0 Host (ULPI interface with USB typeA connector)
UART to USB (USB Mini-B connector)
10/100/1000 Ethernet
PS/2 mouse/keyboard
IR Emitter/Receiver
I2C Multiplexer
C
Co on nn ne ec ct to or rs s
Two 40-pin Expansion Headers
One 10-pin ADC Input Header
One LTC connector (One Serial Peripheral Interface (SPI) Master ,one I2C and one GPIO
interface )

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D
Di is sp pl la ay y
24-bit VGA DAC
A
Au ud di io o
24-bit CODEC, Line-in, line-out, and microphone-in jacks
V
Vi id de eo o I In np pu ut t
TV Decoder (NTSC/PAL/SECAM) and TV-in connector
S
Sw wi it tc ch he es s, , B Bu ut tt to on ns s a an nd d I In nd di ic ca at to or rs s
5 User Keys (FPGA x4, HPS x1)
10 User switches (FPGA x10)
11 User LEDs (FPGA x10, HPS x 1)
2 HPS Reset Buttons (HPS_RESET_n and HPS_WARM_RST_n)
Six 7-segment displays
S
Se en ns so or rs s
G-Sensor on HPS
P
Po ow we er r
12V DC input

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Chapter 3
Using the DE1-SoC
Board
This chapter gives instructions for using the board and describes each of its peripherals.
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3. .1 1 B Bo oa ar rd d S Se et tu up p
This section will explain the settings of FPGA configuration modes, HPS boot source select and
HPS flash controller clock frequency in detail.
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3. .1 1. .1 1 F FP PG GA A C Co on nf fi ig gu ur ra at ti io on n M Mo od de e S Se et tt ti in ng g
Table 3-1 gives the MSEL pins setting for each configuration scheme of Cyclone V SoC devices.
FPGA default works in ASx4 Fast mode with MSEL[4:0] = 10010.
Table 3-1 MSEL pin Settings for each Scheme of Cyclone V Device
Configuration
Scheme
Compression Feature
Design Security
Feature
POR Delay
Valid MSEL[4:0]
FPPx8
Disabled
Disabled
Fast
10100
Standard
11000
Disabled
Enabled
Fast
10101
Standard
11001
Enabled
Disabled
Fast
10110
Standard
11010
FPPx16
Disabled
Enabled
Fast
00000
Standard
00100
Disabled
Disabled
Fast
00001
Standard
00101
Enabled
Enabled
Fast
00010
Standard
00110

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PS
Enabled/ Disabled
Disabled
Fast
10000
Standard
10001
AS(X1 and X4)
Enabled/ Disabled
Enabled
Fast
10010
Standard
10011
Table 3-2 shows the switch controls and descriptions for MSEL.
Table 3-2 SW10 FPGA Configuration Mode Switch
Board Reference
Signal Name
Description
Default
SW10.1
MSEL0
Sets the Cyclone V MSEL[4:0] pins.
Use these pins to set the configuration
scheme and POR delay.
On
SW10.2
MSEL1
Off
SW10.3
MSEL2
On
SW10.4
MSEL3
On
SW10.5
MSEL4
Off
SW10.6
N/A
N/A
N/A
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3. .1 1. .2 2 H HP PS S B BO OO OT TS SE EL L a an nd d C CL LK KS SE EL L S Se et tt ti in ng g
The processor in the HPS can be boot from many sources such as the SD card, QSPI Flash or FPGA.
Selecting the boot source for the HPS can be set using the BOOTSEL signal. Figure 3-1 lists the
settings for selecting a suitable boot source. The default boot source for the HPS is from SD card
with fixing BOOTSEL[2:0] = 101. HPS flash controller clock frequency can be set using
CLOCKSEL signal. Table 3-3 lists the setting for SD/MMC controller CLOCKSEL pins. The
default CLOCKSEL setting is CLOCKSEL[1:0] = 00.
If users need to change BOOTSEL[2:0] and CLOCKSEL[1:0] setting, since we make our
schematic/layout flexible, users can change BOOTSEL[2:0] and CLOCKSEL[1:0] by :
Change the BOOTSEL and CLOCKSEL resistors on the board
By soldering or removing the resistors (R97~R100, R106~R111) will change the value of
BOOTSEL and CLOCKSEL.
Add a x6 dip switch (SW16) on the board
Solder SW16, R97, R98, R107 and remove R99, R100, R110, will let MSEL[4:0] value to be
changed by switching SW16. Table 3-4 shows the switch controls and descriptions for MSEL
Table 3-3 BOOTSEL[2:0] Setting Values and Flash Device Selection
BOOTSEL[2:0] Setting Value
Flash Device
000
Reserved
001
FPGA (HPS-to-FPGA bridge)

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010
1.8 V NAND Flash memory (*1)
011
3.0 V NAND Flash memory(*1)
100
1.8 V SD/MMC Flash memory(*1)
101
3.0 V SD/MMC Flash memory
110
1.8 V SPI or quad SPI Flash memory(*1)
111
3.0 V SPI or quad SPI Flash memory
(*1) : Not supported on DE1-SoC board
Table 3-4 SD/MMC Controller CSEL Pin Settings
Setting
CSEL Pin
0
1
2
3
Osc1_clk (EOSC1 pin) range
10-50MHz
10-12.5MHz
12.5-25MHz
25-50MHz
ID mode
sdmmc_cclk_out device
clock
Osc1_clk/128,
391 KHz max
Osc1_clk/32,
391 KHz max
Osc1_clk/64,
391 KHz max
Osc1_clk/128,
391 KHz max
Controller baud rate divisor
32
32
32
32
Data
transfer
mode
sdmmc_cclk_out device
clock
Osc1_clk/4, 391
12.5MHz max
Osc1_clk*1,
12.5MHz max
Osc1_clk/2,
12.5MHz max
Osc1_clk/4,
12.5MHz max
Controller baud rate divisor
(even numbers only)
1 (bypass)
1 (bypass
1 (bypass
1 (bypass
sdmmc_clk controller clock:
Osc1_clk,
50MHz max
Osc1_clk,
50MHz max
Osc1_clk,
50MHz max
Osc1_clk*2,
50MHz max
mpu_clk
Osc1_clk,
50MHz max
Osc1_clk*32,
400MHz max
Osc1_clk*16,
400MHz max
Osc1_clk*8,
400MHz max
PLL modes
Bypassed
Locked
Locked
Locked
Table 3-5 SW16 HPS BOOTSELand CLKSELSetting
Board Reference
Signal Name
Description
Default
SW16.1
BOOTSEL0
Sets the Cyclone V BOOTSEL[2:0] and
CLOCKSEL[1:0] pins.
Off
SW16.2
BOOTSEL1
On
SW16.3
BOOTSEL2
Off
SW16.4
CLOCKSEL0
On
SW16.5
CLOCKSEL1
On
SW16.6
N/A
N/A
N/A

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3. .2 2 C Co on nf fi ig gu ur ri in ng g t th he e C Cy yc cl lo on ne e V V S So oC C F FP PG GA A
The DE1-SoC board contains a serial configuration device that stores configuration data for the
Cyclone V SoC FPGA. This configuration data is automatically loaded from the configuration
device into the FPGA every time while power is applied to the board. Using the Quartus II software,
it is possible to reconfigure the FPGAat any time, and it is also possible to change the non-volatile
data that is stored in the serial configuration device. Both types of programming methods are
described below.
1. JTAG programming: In this method of programming, named after the IEEE standards Joint Test
Action Group, the configuration bit stream is downloaded directly into the Cyclone V SoC FPGA.
The FPGA will retain this configuration as long as power is applied to the board; the configuration
information will be lost when the power is turned off.
2. AS programming: In this method, called Active Serial programming, the configuration bit
stream is downloaded into the quad serial configuration device (EPCQ256). It provides non-volatile
storage of the bit stream, so that the information is retained even when the power supply to the
DE1-SoC board is turned off. When the board’s power is turned on, the configuration data in the
EPCQ256 device is automatically loaded into the Cyclone V SoC FPGA.
JTAG Chain on DE1-SoC Board
To use JTAG interface for configuring FPGA device, the JTAG chain on DE1-SoC must form a
close loop that allows Quartus II programmer to detect FPGA device. Figure 3-1 illustrates the
JTAG chain on DE1-SoC board.
Figure 3-1 The JTAG chain on the board

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Configuring the FPGA in JTAG Mode
There are two devices (FPGA and HPS) on the JTAG Chain, the configure flow is different from
DE1. The following shows the programming flow with JTAG mode step by step.
Open Programmer and click “Auto Detect “ as Figure 3-2
Select detected device as Figure 3-3 (Please select device as same as which shows on the board)
Figure 3-2 FPGA JTAG Programming Steps 1
Figure 3-3 FPGA JTAG Programming Steps 2

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Both FPGA and HPS will be detected as Figure 3-4
Click the FPGAdevice, right click mouse to popup the manual, and then select .sof file for
FPGA as Figure 3-5
Figure 3-4 FPGA JTAG Programming Steps 3

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Select .sof file for FPGA as Figure 3-6
Figure 3-5 FPGA JTAG Programming Steps 4
Figure 3-6 FPGA JTAG Programming Steps 5

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Click “Program/Configure” check box, and then click “Start” button to download .sof file into
FPGA as Figure 3-7
Configuring the FPGA in AS Mode (from EPCQ256)
The board contains a quad serial configuration device (EPCQ256) that stores configuration data
for the Cyclone V SoC FPGA. This configuration data is automatically loaded from the quad
serial configuration device chip into the FPGA when the board is powered up.
To program the configuration device, users will need to use a Serial Flash Loader (SFL)
function to program the quad serial configuration device via the JTAG interface. The
Figure 3-7 FPGA JTAG Programming Steps 6

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FPGA-based SFL is a soft intellectual property (IP) core within the FPGA that bridges the JTAG
and flash interfaces. The SFL mega-function is available from Quartus II software. Figure 3-8
shows the programming method when adopting a SFL solution
Please refer to Chapter 9: Steps of Programming the Quad Serial Configuration Device for the
basic programming instruction on the serial configuration device
Figure 3-8 Programming a Quad Serial Configuration Device with the SFL Solution
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3. .3 3 B Bo oa ar rd d S St ta at tu us s E El le em me en nt ts s
The board includes status LEDs. Please refer toTable 3-6 for the status of the LED indicator.
Table 3-6 LED Indicators
Board Reference
LED Name
Description
D14
12-V Power
Illuminates when 12-V power is active.
TXD
UART TXD
Illuminates when data from FT232R to USB Host.
RXD
UART RXD
Illuminates when data from USB Host to FT232R.
D5
JTAG_RX
Reserved
D4
JTAG_TX

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3. .4 4 B Bo oa ar rd d R Re es se et t E El le em me en nt ts s
The board equips two HPS reset circuits (See Figure 3-9). Table 3-7 shows the buttons references
and its descriptions. Figure 3-10 shows the reset tree on the board.
Figure 3-9 Board Reset Elements
Table 3-7 Reset Elements
Board Reference
Signal Name
Description
KEY5
HPS_RESET_N
Cold reset to the HPS , Ethernet PHY and USB host device .
Active low input that will reset all HPS logics that can be reset.
Places the HPS in a default state sufficient for software to
boot.
KEY7
HPS_WARM_RST_N
Warm reset to the HPS block. Active low input affects the
system reset domains which allows debugging to operate.