Terasic DE0-Nano-SoC User manual

DE0-Nano-SoC
User Manual
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August 31, 2017

DE0-Nano-SoC
User Manual
1
www.terasic.com
August 31, 2017
CONTENTS
Chapter 1 DE0-Nano-SoC Development Kit ...................................................4
1.1 Package Contents .......................................................................................................................5
1.2 DE0-Nano-SoC System CD.......................................................................................................5
1.3 Getting Help...............................................................................................................................6
Chapter 2 Introduction of the DE0-Nano-SoC Board ......................................7
2.1 Layout and Components.............................................................................................................7
2.2 Block Diagram of the DE0-Nano-SoC Board............................................................................9
Chapter 3 Using the DE0-Nano-SoC Board..................................................12
3.1 Settings of FPGA Configuration Mode....................................................................................12
3.2 Configuration of Cyclone V SoC FPGA on DE0-Nano-SoC...................................................14
3.3 Board Status Elements .............................................................................................................19
3.4 Board Reset Elements ..............................................................................................................20
3.5 Clock Circuitry.........................................................................................................................21
3.6 Peripherals Connected to the FPGA.........................................................................................22
3.6.1 User Push-buttons, Switches and LEDs............................................................................23
3.6.2 2x20 GPIO Expansion Headers.........................................................................................26
3.6.3 Arduino Uno R3 Expansion Header..................................................................................29
3.6.4 A/D Converter and Analog Input ......................................................................................31
3.7 Peripherals Connected to Hard Processor System (HPS).........................................................33
3.7.1 User Push-buttons and LEDs ............................................................................................33
3.7.2 Gigabit Ethernet ................................................................................................................33
3.7.3 UART................................................................................................................................35
3.7.4 DDR3 Memory..................................................................................................................36

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3.7.5 Micro SD Card Socket ......................................................................................................38
3.7.6 USB 2.0 OTG PHY...........................................................................................................39
3.7.7 G-sensor ............................................................................................................................40
3.7.8 LTC Connector..................................................................................................................40
Chapter 4 DE0-Nano-SoC System Builder ...................................................42
4.1 Introduction..............................................................................................................................42
4.2 Design Flow .............................................................................................................................42
4.3 Using DE0-Nano-SoC System Builder....................................................................................43
Chapter 5 Examples For FPGA ....................................................................49
5.1 DE0-Nano-SoC Factory Configuration....................................................................................49
5.2 ADC Reading ...........................................................................................................................50
Chapter 6 Examples for HPS SoC .................................................................53
6.1 Hello Program..........................................................................................................................53
6.2 Users LED and KEY................................................................................................................55
6.3 I2C Interfaced G-sensor ...........................................................................................................61
Chapter 7 Examples for using both HPS SoC and FGPA ...............................65
7.1 HPS Control FPGA LED..........................................................................................................65
Chapter 8 Programming the EPCS Device.....................................................69
8.1 Before Programming Begins....................................................................................................69
8.2 Convert .SOF File to .JIC File..................................................................................................70
8.3 Write JIC File into the EPCS Device .......................................................................................74
8.4 Erase the EPCS Device ............................................................................................................75
8.5 EPCS Programming via nios-2-flash-programmer ..................................................................76
8.6 Nios II Boot from EPCS Device in Quartus II v13.1 or later ...........................................77
Chapter 9 Appendix A ....................................................................................78

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9.1 What's different between the DE0-Nano-SoC kit and the Atlas-SoC kit?................................78
Chapter 10 Appendix B ....................................................................................79
10.1 Revision History.....................................................................................................................79
10.2 Copyright Statement...............................................................................................................79

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Chapter 1
DE0-Nano-SoC
Development Kit
The DE0-Nano-SoC Development Kit presents a robust hardware design platform built around the
Altera System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded
cores with industry-leading programmable logic for ultimate design flexibility. Users can now
leverage the power of tremendous re-configurability paired with a high-performance, low-power
processor system. Altera’s SoC integrates an ARM-based hard processor system (HPS) consisting of
processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a
high-bandwidth interconnect backbone. The DE0-Nano-SoC development board is equipped with
high-speed DDR3 memory, analog to digital capabilities, Ethernet networking, and much more that
promise many exciting applications.
The DE0-Nano-SoC Development Kit contains all the tools needed to use the board in conjunction
with a computer that runs the Microsoft Windows XP or later.
In addition, DE0-Nano-SoC Kit is also called Atlas-SoC Kit in Altera's Rockboard.org Linux
community (http://www.rocketboards.org/atlas-soc). The hardware of DE0-Nano-SoC Kit and
Atlas-SoC Kit are exactly the same, however, this community provides different development
resource from DE0-Nano-SoC Kit. The details of kit contents can be found in the Appendix chapter.

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1.1
P
Pa ac ck ka ag ge e C Co on nt te en nt ts s
Figure 1-1 shows a photograph of the DE0-Nano-SoC package.
Figure 1-1 The DE0-Nano-SoC package contents
The DE0-Nano-SoC package includes:
The DE0-Nano-SoC development board
DE0-Nano-SoC Quick Start Guide
USB cable Type A to Mini-B for FPGA programming or UART control
USB cable Type A to Micro-B for USB OTG connect to PC
5V/2A DC power adapter
4GB microSD Card (Installed)
1.2
D
DE E0 0- -N Na an no o- -S So oC C S Sy ys st te em m C CD D
The DE0-Nano-SoC System CD contains all the documents and supporting materials associated
with DE0-Nano-SoC, including the user manual, system builder, reference designs, and device
datasheets. Users can download this system CD from the link: http://cd-de0-nano-soc.terasic.com.

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1.3
G
Ge et tt ti in ng g H He el lp p
Here are the addresses where you can get help if you encounter any problems:
Altera Corporation
101 Innovation Drive San Jose, California, 95134 USA
Email: [email protected]
Terasic Technologies
9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
Email: [email protected]
Tel.: [phone]
Website: de0-nano-soc.terasic.com

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Chapter 2
Introduction of the
DE0-Nano-SoC Board
This chapter provides an introduction to the features and design characteristics of the board.
2.1
L
La ay yo ou ut t a an nd d C Co om mp po on ne en nt ts s
Figure 2-1 and Figure 2-2 shows a photograph of the board. It depicts the layout of the board and
indicates the location of the connectors and key components.
Figure 2-1 DE0-Nano-SoC development board (top view)

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Figure 2-2 DE0-Nano-SoC development board (bottom view)
The DE0-Nano-SoC board has many features that allow users to implement a wide range of
designed circuits, from simple circuits to various multimedia projects.
The following hardware is provided on the board:
FPGA
Altera Cyclone® V SE 5CSEMA4U23C6N device
Serial configuration device –EPCS
USB-Blaster II onboard for programming; JTAG Mode
2 push-buttons
4 slide switches
8 green user LEDs
Three 50MHz clock sources from the clock generator
Two 40-pin expansion header
One Arduino expansion header (Uno R3 compatibility), can connect with Arduino shields.
One 10-pin Analog input expansion header. (shared with Arduino Analog input)
A/D converter, 4-wire SPI interface with FPGA

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HPS (Hard Processor System)
925MHz Dual-core ARM Cortex-A9 processor
1GB DDR3 SDRAM (32-bit data bus)
1 Gigabit Ethernet PHY with RJ45 connector
port USB OTG, USB Micro-AB connector
Micro SD card socket
Accelerometer (I2C interface + interrupt)
UART to USB, USB Mini-B connector
Warm reset button and cold reset button
One user button and one user LED
LTC 2x7 expansion header
2.2
B
Bl lo oc ck k D Di ia ag gr ra am m o of f t th he e D DE E0 0- -N Na an no o- -S So oC C B Bo oa ar rd d
Figure 2-3 is the block diagram of the board. All the connections are established through the
Cyclone V SoC FPGA device to provide maximum flexibility for users. Users can configure the
FPGA to implement any system design.

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Figure 2-3 Block diagram of DE0-Nano-SoC
Detailed information about Figure 2-3 are listed below.
F
FP PG GA A D De ev vi ic ce e
Cyclone V SoC 5CSEMA4U23C6N Device
Dual-core ARM Cortex-A9 (HPS)
40K programmable logic elements
2,460 Kbits embedded memory
5 fractional PLLs
2 hard memory controllers
C
Co on nf fi ig gu ur ra at ti io on n a an nd d D De eb bu ug g
Serial configuration device –EPCS on FPGA
Onboard USB-Blaster II (Mini-B USB connector)

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M
Me em mo or ry y D De ev vi ic ce e
1GB (2x256Mx16) DDR3 SDRAM on HPS
Micro SD card socket on HPS
C
Co om mm mu un ni ic ca at ti io on n
One USB 2.0 OTG (ULPI interface with USB Micro-AB connector)
UART to USB (USB Mini-B connector)
10/100/1000 Ethernet
C
Co on nn ne ec ct to or rs s
Two 40-pin expansion headers
Arduino expansion header
One 10-pin ADC input header
One LTC connector (one Serial Peripheral Interface (SPI) Master ,one I2C and one GPIO
interface )
A
AD DC C
12-Bit Resolution, 500Ksps Sampling Rate. SPI Interface.
8-Channel Analog Input. Input Range : 0V ~ 4.096V.
S
Sw wi it tc ch he es s, , B Bu ut tt to on ns s, , a an nd d I In nd di ic ca at to or rs s
3 user Keys (FPGA x2, HPS x1)
4 user switches (FPGA x4)
9 user LEDs (FPGA x8, HPS x 1)
2 HPS reset buttons (HPS_RESET_n and HPS_WARM_RST_n)
S
Se en ns so or rs s
G-Sensor on HPS
P
Po ow we er r
5V DC input

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Chapter 3
Using the
DE0-Nano-SoC Board
This chapter provides an instruction to use the board and describes the peripherals.
3.1
S Se et tt ti in ng gs s o of f F FP PG GA A C Co on nf fi ig gu ur ra at ti io on n M Mo od de e
When the DE0-Nano-SoC board is powered on, the FPGA can be configured from EPCS or HPS.
The MSEL[4:0] pins are used to select the configuration scheme. It is implemented as a 6-pin DIP
switch SW10 on the DE0-Nano-SoC board, as shown in Figure 3-1.
Figure 3-1 DIP switch (SW10) setting of FPP x32 mode

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Table 3-1 shows the relation between MSEL[4:0] and DIP switch (SW10).
Table 3-1 FPGAConfiguration Mode Switch (SW10)
Board Reference
Signal Name
Description
Default
SW10.1
MSEL0
Use these pins to set the FPGA
Configuration scheme
ON (“0”)
SW10.2
MSEL1
OFF (“1”)
SW10.3
MSEL2
ON (“0”)
SW10.4
MSEL3
OFF (“1”)
SW10.5
MSEL4
ON (“0”)
SW10.6
N/A
N/A
N/A
Table 3-2 shows MSEL[4:0] setting for FPGA configure, and default setting is FPPx32 mode on
DE0-Nano-SoC.
When the board is powered on and MSEL[4:0] set to “10010”, the FPGA is configured from
EPCS, which is pre-programmed with the default code. If developers wish to configure FPGA from
an application software running on Linux, the MSEL[4:0] needs to be set to “01010”before the
programming process begins. If developers using the "Linux Console with frame buffer" or "Linux
LXDE Desktop" SD Card image, the MSEL[4:0] needs to be set to “00000” before the board is
powered on.
Table 3-2 MSELPin Settings for FPGAConfigure of DE0-Nano-SoC
Configuration
SW10.1
MSEL0
SW10.2
MSEL1
SW10.3
MSEL2
SW10.4
MSEL3
SW10.5
MSEL4
SW10.6
Description
AS
ON
OFF
ON
ON
OFF
N/A
FPGA configured from EPCS
FPPx32 (Default)
ON
OFF
ON
OFF
ON
N/A
FPGA configured from HPS
software: Linux (default)
FPPx16
ON
ON
ON
ON
ON
N/A
FPGA configured from HPS
software: U-Boot, with image
stored on the SD card, like
LXDE Desktop or console
Linux with frame buffer
edition.

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3.2
C
Co on nf fi ig gu ur ra at ti io on n o of f C Cy yc cl lo on ne e V V S So oC C F FP PG GA A o on n D DE E0 0- -N Na an no o- -S So oC C
There are two types of programming method supported by DE0-Nano-SoC:
1. JTAG programming: It is named after the IEEE standards Joint TestAction Group.
The configuration bit stream is downloaded directly into the Cyclone V SoC FPGA. The FPGAwill
retain its current status as long as the power keeps applying to the board; the configuration
information will be lost when the power is off.
2. AS programming: The other programming method is Active Serial configuration.
The configuration bit stream is downloaded into the serial configuration device (EPCS), which
provides non-volatile storage for the bit stream. The information is retained within EPCS even if the
DE0-Nano-SoC board is turned off. When the board is powered on, the configuration data in the
EPCS device is automatically loaded into the Cyclone V SoC FPGA.
JTAG Chain on DE0-Nano-SoC Board
The FPGA device can be configured through JTAG interface on DE0-Nano-SoC board, but the
JTAG chain must form a closed loop, which allows Quartus II programmer to the detect FPGA
device. Figure 3-2 illustrates the JTAG chain on DE0-Nano-SoC board.
Figure 3-2 Path of the JTAG chain
Configure the FPGA in JTAG Mode
There are two devices (FPGA and HPS) on the JTAG chain. The following shows how the FPGA is
programmed in JTAG mode step by step.

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Open the Quartus II programmer and click “Auto Detect”, as circled in Figure 3-3
Figure 3-3 Detect FPGA device in JTAG mode
Select detected device associated with the board, as circled in Figure 3-4.
Figure 3-4 Select 5CSEMA4 device

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Both FPGA and HPS are detected, as shown in Figure 3-5.
Figure 3-5 FPGA and HPS detected in Quartus programmer
Right click on the FPGA device and open the .sof file to be programmed, as highlighted in Figure
3-6.
Figure 3-6 Open the .sof file to be programmed into the FPGA device

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Select the .sof file to be programmed, as shown in Figure 3-7.
Figure 3-7 Select the .sof file to be programmed into the FPGA device
Click “Program/Configure” check box and then click “Start” button to download the .sof file into
the FPGA device, as shown in Figure 3-8.
Figure 3-8 Program .sof file into the FPGA device

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Configure the FPGA in AS Mode
The DE0-Nano-SoC board uses a serial configuration device (EPCS) to store configuration data for
the Cyclone V SoC FPGA. This configuration data is automatically loaded from the serial
configuration device chip into the FPGA when the board is powered up.
Users need to use Serial Flash Loader (SFL) to program the serial configuration device via JTAG
interface. The FPGA-based SFL is a soft intellectual property (IP) core within the FPGA that bridge
the JTAG and Flash interfaces. The SFL Megafunction is available in Quartus II. Figure 3-9 shows
the programming method when adopting SFL solution.
Please refer to Chapter 8: Steps of Programming the Serial Configuration Device for the basic
programming instruction on the serial configuration device.
Figure 3-9 Programming a serial configuration device with SFL solution

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3.3
B
Bo oa ar rd d S St ta at tu us s E El le em me en nt ts s
In addition to the 9 LEDs that FPGA/HPS device can control, there are 6 indicators which can
indicate the board status (See Figure 3-10), please refer the details in Table 3-3
Figure 3-10 LED Indicators on DE0-Nano-SoC
Table 3-3 LED Indicators
Board Reference
LED Name
Description
LED9
3.3-V Power
Illuminate when 3.3V power is active.
LED10
CONF_DONE
Illuminates when the FPGA is successfully configured.
LED11
JTAG_TX
Illuminate when data is transferred from JTAG to USB Host.
LED12
JTAG_RX
Illuminate when data is transferred from USB Host to JTAG.
TXD
UART TXD
Illuminate when data is transferred from FT232R to USB Host.
RXD
UART RXD
Illuminate when data is transferred from USB Host to FT232R.