NXP Semiconductors MKL27Z128VFM4 User manual

KL27 Sub-Family Reference Manual
Supports: MKL27Z128VFM4, MKL27Z256VFM4, MKL27Z128VFT4,
MKL27Z256VFT4, MKL27Z128VMP4, MKL27Z256VMP4,
MKL27Z128VLH4, MKL27Z256VLH4
Document Number: KL27P64M48SF6RM
Rev. 5, 01/2016

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Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................37
1.1.1 Purpose...........................................................................................................................................................37
1.1.2 Audience........................................................................................................................................................ 37
1.2 Conventions.................................................................................................................................................................. 37
1.2.1 Numbering systems........................................................................................................................................37
1.2.2 Typographic notation..................................................................................................................................... 38
1.2.3 Special terms..................................................................................................................................................38
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................39
2.1.1 Sub-family introduction................................................................................................................................. 39
2.2 Module functional categories........................................................................................................................................40
2.2.1 ARM Cortex-M0+ core modules................................................................................................................... 41
2.2.2 System modules............................................................................................................................................. 41
2.2.3 Memories and memory interfaces..................................................................................................................42
2.2.4 Clocks.............................................................................................................................................................42
2.2.5 Security and integrity modules...................................................................................................................... 43
2.2.6 Analog modules............................................................................................................................................. 43
2.2.7 Timer modules............................................................................................................................................... 43
2.2.8 Communication interfaces............................................................................................................................. 44
2.2.9 Human-machine interfaces............................................................................................................................ 45
2.3 Module to module interconnects...................................................................................................................................45
2.3.1 Interconnection overview...............................................................................................................................45
2.3.2 Analog reference options............................................................................................................................... 47
Chapter 3
Core Overview
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3.1 ARM Cortex-M0+ core introduction............................................................................................................................49
3.1.1 Buses, interconnects, and interfaces.............................................................................................................. 49
3.1.2 System tick timer........................................................................................................................................... 49
3.1.3 Debug facilities.............................................................................................................................................. 49
3.1.4 Core privilege levels...................................................................................................................................... 50
3.2 Nested vectored interrupt controller (NVIC) ...............................................................................................................50
3.2.1 Interrupt priority levels.................................................................................................................................. 50
3.2.2 Non-maskable interrupt..................................................................................................................................50
3.2.3 Interrupt channel assignments........................................................................................................................50
3.3 AWIC introduction....................................................................................................................................................... 53
3.3.1 Wake-up sources............................................................................................................................................53
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................55
4.2 Flash memory............................................................................................................................................................... 55
4.2.1 Flash memory map.........................................................................................................................................55
4.2.2 Flash security................................................................................................................................................. 56
4.2.3 Flash modes....................................................................................................................................................56
4.2.4 Erase all flash contents...................................................................................................................................56
4.2.5 FTFA_FOPT register..................................................................................................................................... 57
4.3 SRAM........................................................................................................................................................................... 57
4.3.1 SRAM sizes....................................................................................................................................................57
4.3.2 SRAM ranges.................................................................................................................................................57
4.3.3 SRAM retention in low power modes............................................................................................................58
4.4 System Register file......................................................................................................................................................58
4.5 System memory map.....................................................................................................................................................59
4.6 Bit Manipulation Engine...............................................................................................................................................60
4.7 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................60
4.7.1 Read-after-write sequence and required serialization of memory operations................................................60
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Section number Title Page
4.7.2 Peripheral bridge (AIPS-Lite) memory map..................................................................................................61
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................65
5.2 Programming model......................................................................................................................................................65
5.3 High-level device clocking diagram............................................................................................................................. 65
5.4 Clock definitions...........................................................................................................................................................66
5.4.1 Device clock summary...................................................................................................................................67
5.5 Internal clocking requirements..................................................................................................................................... 69
5.5.1 Clock divider values after reset......................................................................................................................70
5.5.2 VLPR mode clocking.....................................................................................................................................70
5.6 Clock gating..................................................................................................................................................................71
5.7 Module clocks...............................................................................................................................................................71
5.7.1 PMC 1-kHz LPO clock..................................................................................................................................72
5.7.2 COP clocking................................................................................................................................................. 72
5.7.3 RTC clocking................................................................................................................................................. 73
5.7.4 RTC_CLKOUT and CLKOUT32K clocking................................................................................................73
5.7.5 LPTMR clocking............................................................................................................................................74
5.7.6 TPM clocking.................................................................................................................................................75
5.7.7 USB FS device only controller clocking........................................................................................................75
5.7.8 LPUART clocking......................................................................................................................................... 76
5.7.9 FlexIO clocking..............................................................................................................................................77
5.7.10 I2S/SAI clocking............................................................................................................................................78
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................79
6.2 Reset..............................................................................................................................................................................79
6.2.1 Power-on reset (POR).................................................................................................................................... 80
6.2.2 System reset sources...................................................................................................................................... 80
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Section number Title Page
6.2.3 MCU resets.................................................................................................................................................... 83
6.2.4 RESET pin .................................................................................................................................................... 84
6.3 Boot...............................................................................................................................................................................84
6.3.1 Boot sources...................................................................................................................................................85
6.3.2 FOPT boot options.........................................................................................................................................85
6.3.3 Boot sequence................................................................................................................................................ 87
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................89
7.2 Clocking modes............................................................................................................................................................ 89
7.2.1 Partial Stop.....................................................................................................................................................89
7.2.2 DMA Wakeup................................................................................................................................................90
7.2.3 Compute Operation........................................................................................................................................91
7.2.4 Peripheral Doze..............................................................................................................................................92
7.2.5 Clock gating................................................................................................................................................... 93
7.3 Power modes.................................................................................................................................................................93
7.4 Entering and exiting power modes............................................................................................................................... 95
7.5 Module operation in low-power modes........................................................................................................................ 96
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................101
8.1.1 Flash security................................................................................................................................................. 101
8.1.2 Security interactions with other modules.......................................................................................................101
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................103
9.2 Debug port pin descriptions..........................................................................................................................................103
9.3 SWD status and control registers..................................................................................................................................104
9.3.1 MDM-AP Control Register............................................................................................................................105
9.3.2 MDM-AP Status Register.............................................................................................................................. 106
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9.4 Debug resets..................................................................................................................................................................108
9.5 Micro Trace Buffer (MTB)...........................................................................................................................................108
9.6 Debug in low-power modes..........................................................................................................................................109
9.7 Debug and security....................................................................................................................................................... 110
Chapter 10
Pinouts and Packaging
10.1 Introduction...................................................................................................................................................................111
10.2 Signal multiplexing integration.................................................................................................................................... 111
10.2.1 Clock gating................................................................................................................................................... 112
10.2.2 Signal multiplexing constraints......................................................................................................................112
10.3 KL27 Signal Multiplexing and Pin Assignments......................................................................................................... 112
10.4 KL27 Family Pinouts....................................................................................................................................................115
10.5 Module Signal Description Tables................................................................................................................................118
10.5.1 Core modules................................................................................................................................................. 118
10.5.2 System modules............................................................................................................................................. 118
10.5.3 Clock modules................................................................................................................................................119
10.5.4 Analog............................................................................................................................................................119
10.5.5 Timer Modules...............................................................................................................................................120
10.5.6 Communication interfaces............................................................................................................................. 121
10.5.7 Human-machine interfaces (HMI).................................................................................................................124
Chapter 11
Port Control and Interrupts (PORT)
11.1 Chip-specific PORT information..................................................................................................................................125
11.2 Port control and interrupt summary.............................................................................................................................. 126
11.3 Introduction...................................................................................................................................................................127
11.4 Overview.......................................................................................................................................................................127
11.4.1 Features.......................................................................................................................................................... 127
11.4.2 Modes of operation........................................................................................................................................ 128
11.5 External signal description............................................................................................................................................129
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11.6 Detailed signal description............................................................................................................................................129
11.7 Memory map and register definition.............................................................................................................................129
11.7.1 Pin Control Register n (PORTx_PCRn).........................................................................................................135
11.7.2 Global Pin Control Low Register (PORTx_GPCLR)....................................................................................138
11.7.3 Global Pin Control High Register (PORTx_GPCHR)...................................................................................138
11.7.4 Interrupt Status Flag Register (PORTx_ISFR).............................................................................................. 139
11.8 Functional description...................................................................................................................................................139
11.8.1 Pin control......................................................................................................................................................139
11.8.2 Global pin control.......................................................................................................................................... 140
11.8.3 External interrupts..........................................................................................................................................140
Chapter 12
System Integration Module (SIM)
12.1 Chip-specific SIM information.....................................................................................................................................143
12.1.1 COP clocks.....................................................................................................................................................143
12.2 Introduction...................................................................................................................................................................143
12.2.1 Features.......................................................................................................................................................... 143
12.3 Memory map and register definition.............................................................................................................................144
12.3.1 System Options Register 1 (SIM_SOPT1).................................................................................................... 145
12.3.2 SOPT1 Configuration Register (SIM_SOPT1CFG)......................................................................................146
12.3.3 System Options Register 2 (SIM_SOPT2).................................................................................................... 148
12.3.4 System Options Register 4 (SIM_SOPT4).................................................................................................... 150
12.3.5 System Options Register 5 (SIM_SOPT5).................................................................................................... 151
12.3.6 System Options Register 7 (SIM_SOPT7).................................................................................................... 153
12.3.7 System Device Identification Register (SIM_SDID).....................................................................................154
12.3.8 System Clock Gating Control Register 4 (SIM_SCGC4)..............................................................................156
12.3.9 System Clock Gating Control Register 5 (SIM_SCGC5)..............................................................................158
12.3.10 System Clock Gating Control Register 6 (SIM_SCGC6)..............................................................................160
12.3.11 System Clock Gating Control Register 7 (SIM_SCGC7)..............................................................................162
12.3.12 System Clock Divider Register 1 (SIM_CLKDIV1).....................................................................................162
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12.3.13 Flash Configuration Register 1 (SIM_FCFG1)............................................................................................. 164
12.3.14 Flash Configuration Register 2 (SIM_FCFG2)............................................................................................. 165
12.3.15 Unique Identification Register Mid-High (SIM_UIDMH)............................................................................166
12.3.16 Unique Identification Register Mid Low (SIM_UIDML)............................................................................. 167
12.3.17 Unique Identification Register Low (SIM_UIDL)........................................................................................ 167
12.3.18 COP Control Register (SIM_COPC)............................................................................................................. 168
12.3.19 Service COP (SIM_SRVCOP).......................................................................................................................169
12.4 Functional description...................................................................................................................................................169
12.4.1 COP watchdog operation............................................................................................................................... 170
Chapter 13
Kinetis ROM Bootloader
13.1 Chip-Specific Information............................................................................................................................................ 173
13.2 Introduction...................................................................................................................................................................173
13.3 Functional Description..................................................................................................................................................175
13.3.1 Memory Maps................................................................................................................................................175
13.3.2 The Kinetis Bootloader Configuration Area (BCA)......................................................................................176
13.3.3 Start-up Process..............................................................................................................................................177
13.3.4 Clock Configuration.......................................................................................................................................179
13.3.5 Bootloader Entry Point...................................................................................................................................180
13.3.6 Bootloader Protocol....................................................................................................................................... 181
13.3.7 Bootloader Packet Types............................................................................................................................... 186
13.3.8 Bootloader Command API.............................................................................................................................193
13.3.9 Bootloader Exit state......................................................................................................................................208
13.4 Peripherals Supported................................................................................................................................................... 209
13.4.1 I2C Peripheral................................................................................................................................................ 209
13.4.2 SPI Peripheral................................................................................................................................................ 211
13.4.3 USB peripheral...............................................................................................................................................213
13.5 Get/SetProperty Command Properties..........................................................................................................................217
13.5.1 Property Definitions.......................................................................................................................................218
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13.6 Kinetis Bootloader Status Error Codes.........................................................................................................................220
13.7 Bootloader errata...........................................................................................................................................................221
Chapter 14
System Mode Controller (SMC)
14.1 Chip-specific SMC information....................................................................................................................................223
14.2 Introduction...................................................................................................................................................................223
14.3 Modes of operation....................................................................................................................................................... 223
14.4 Memory map and register descriptions.........................................................................................................................225
14.4.1 Power Mode Protection register (SMC_PMPROT).......................................................................................226
14.4.2 Power Mode Control register (SMC_PMCTRL)...........................................................................................227
14.4.3 Stop Control Register (SMC_STOPCTRL)...................................................................................................228
14.4.4 Power Mode Status register (SMC_PMSTAT)............................................................................................. 230
14.5 Functional description...................................................................................................................................................230
14.5.1 Power mode transitions..................................................................................................................................230
14.5.2 Power mode entry/exit sequencing................................................................................................................ 233
14.5.3 Run modes......................................................................................................................................................234
14.5.4 Wait modes.................................................................................................................................................... 236
14.5.5 Stop modes.....................................................................................................................................................237
14.5.6 Debug in low power modes........................................................................................................................... 240
Chapter 15
Power Management Controller (PMC)
15.1 Introduction...................................................................................................................................................................241
15.2 Features.........................................................................................................................................................................241
15.3 Low-voltage detect (LVD) system................................................................................................................................241
15.3.1 LVD reset operation.......................................................................................................................................242
15.3.2 LVD interrupt operation.................................................................................................................................242
15.3.3 Low-voltage warning (LVW) interrupt operation......................................................................................... 242
15.4 I/O retention..................................................................................................................................................................243
15.5 Memory map and register descriptions.........................................................................................................................243
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