Toshiba TX79 Series User manual

TX System RISC
TX79 Family
TMPR7901
(Symmetric 2-way superscalar
64-bit CPU)

The information contained herein is subject to change without notice.
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implication or otherwise under any patent or patent rights of TOSHIBA or others.
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Nevertheless, semiconductor devices in general can malfunction or fail due to their
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It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with
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situations in which a malfunction or failure of such TOSHIBA products could cause loss
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specified operating ranges as set forth in the most recent TOSHIBA products
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Also, please keep in mind the precautions and conditions set forth in the “Handling
Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
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equipment, industrial robotics, domestic appliances, etc.).
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© 2001 TOSHIBA CORPORATION
All Rights Reserved

Table Of Contents
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001) i
TABLE OF CONTENTS
CHAPTER 1. INTRODUCTION........................................................................................................1-1
1.1 OVERVIEW................................................................................................................................1-1
1.2 TERMINOLOGY .........................................................................................................................1-1
1.2.1 Abbreviations used...............................................................................................................1-1
1.2.2 Other Terminology............................................................................................................... 1-3
1.3 CONVENTIONS..........................................................................................................................1-3
CHAPTER 2. FEATURES...................................................................................................................2-1
CHAPTER 3. CONFIGURATION.....................................................................................................3-1
3.1 RESET CONFIGURATION ...........................................................................................................3-4
CHAPTER 4. ADDRESS MAPS......................................................................................................... 4-1
4.1 MEMORY MAP..........................................................................................................................4-1
4.2 REGISTER MAP......................................................................................................................... 4-2
CHAPTER 5. C790 PROCESSOR CORE.........................................................................................5-1
5.1 FEATURES................................................................................................................................. 5-1
5.2 BLOCK DIAGRAM AND FUNCTIONAL BLOCK DESCRIPTIONS .................................................... 5-2
5.3 C790 REGISTERS......................................................................................................................5-4
5.4 FPU REGISTERS ....................................................................................................................... 5-4
5.5 MEMORY MANAGEMENT.......................................................................................................... 5-4
5.6 CACHE MEMORY......................................................................................................................5-4
5.7 FLOATING POINT UNIT ............................................................................................................. 5-5
5.8 PERFORMANCE MONITOR......................................................................................................... 5-5
5.9 DEBUG FUNCTIONS................................................................................................................... 5-6
CHAPTER 6. SDRAM MEMORY CONTROLLER........................................................................6-1
6.1 OVERVIEW................................................................................................................................6-1
6.2 FEATURES................................................................................................................................. 6-1
6.3 ADDRESS SPACE DECODING..................................................................................................... 6-1
6.4 TWO-STAGE DECODING PROCESS ............................................................................................6-1
6.4.1 Default Memory Map...........................................................................................................6-6
6.4.2 Example connection of DIMMs ........................................................................................... 6-6
6.5 REGISTERS................................................................................................................................6-7
6.5.1 Parameters register .............................................................................................................6-9
6.5.2 Operation Mode Register (0x1E00_0040) R/W.................................................................6-12
6.5.3 ECC Mode Register (0x1E00_0050) R/W..........................................................................6-15
6.5.4 ECC Error Status Register (read only) (0x1E00_0060)....................................................6-16
6.5.5 ECC Error Address Register (read only) (0x1E00_0070).................................................6-17
6.5.6 Refresh Register (0x1E00_0090) R/W ............................................................................... 6-17
6.5.7 SDRAM Interface Output Drive-Strength Control Register (0x1E00_00A0) R/W.............6-18
6.5.8 DIMM 0 LOW Address Decode (0x1E00_0100) ............................................................... 6-18
6.5.9 DIMM 0 HIGH Address Decode (0x1E00_0110).............................................................. 6-19
6.5.10 DIMM 1 LOW Address Decode (0x1E00_0120) ...............................................................6-19
6.5.11 DIMM1 HIGH Address Decode (0x1E00_0130)............................................................... 6-19
6.5.12 DIMM 2 LOW Address Decode (0x1E00_0140) ...............................................................6-20
6.5.13 DIMM 2 HIGH Address Decode (0x1E00_0150).............................................................. 6-21
6.5.14 DIMM 3 LOW Address Decode (0x1E00_0160) ...............................................................6-21
6.5.15 DIMM 3 HIGH Address Decode (0x1E00_0170).............................................................. 6-21
6.6 ADDRESS MAPPING ................................................................................................................ 6-22
6.7 DATA ECC GENERATION ....................................................................................................... 6-23

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TX7901 User’s Manual (Rev. 6.30T – Nov, 2001) ii
6.8 SDRAM INITIALIZATION .......................................................................................................6-25
CHAPTER 7. C790 BUS / G-BUS BRIDGE ......................................................................................7-1
7.1 INTRODUCTION......................................................................................................................... 7-1
7.2 ADDRESS SPACE DECODE AND TRANSLATION..........................................................................7-2
7.3 BUS TRANSACTIONS.................................................................................................................7-2
7.4 ENDIANNESS.............................................................................................................................7-3
7.5 BUS ERRORS............................................................................................................................. 7-4
7.6 REGISTERS................................................................................................................................7-5
7.6.1 System Configuration Register ............................................................................................ 7-6
7.6.2 C790 Bus Control Register..................................................................................................7-6
7.6.3 C790 Bus Status Register.....................................................................................................7-8
7.6.4 C790 Bus Bad Address Register..........................................................................................7-9
7.6.5 CG Upper Internal Register Address (UIRA)...................................................................... 7-9
7.6.6 CG Lower Internal Register Address (LIRA).....................................................................7-10
7.6.7 CG Upper ROM Address Register (UROMA) ...................................................................7-10
7.6.8 CG Lower ROM Address Register (LROMA).................................................................... 7-11
7.6.9 CG Upper PCI Address Register (CGUPA0, CGUPA1, CGUPA2, CGUPA3).................7-11
7.6.10 CG Lower PCI Address Register (CGLPA0, CGLPA1, CGLPA2, CGLPA3) ................... 7-12
7.6.11 GC Upper Internal Register Address Register (GCUIRA) ................................................7-12
7.6.12 GC Lower Internal Register Address Register (GCLIRA).................................................7-13
7.6.13 GC Upper Memory Address Register (GCUMAx).............................................................7-13
7.6.14 GC Lower Memory Address Register (GCLMAx) .............................................................7-14
7.6.15 Interrupt Status Register (IRSTAT).................................................................................... 7-14
7.6.16 Interrupt Mask Register (IRMSK)...................................................................................... 7-16
7.6.17 C790 Bus Latency Timer (LT)............................................................................................7-16
7.6.18 NMI Status Register (NRSTAT)..........................................................................................7-17
7.6.19 G-Bus Master Latency Timer.............................................................................................7-17
7.6.20 G- Bus Broken Master Latency Timer ............................................................................... 7-18
7.6.21 G- Bus Slave Latency Timer ..............................................................................................7-18
7.6.22 G-Bus Retry Timer.............................................................................................................7-19
7.6.23 GC Control Register.........................................................................................................7-20
7.6.24 G-Bus Status Register........................................................................................................7-21
7.6.25 G-Bus Bad Address Register..............................................................................................7-22
7.6.26 G-Bus Arbiter Request Status Register..............................................................................7-22
7.6.27 G-Bus Arbiter Granted Status Register .............................................................................7-23
7.6.28 G-Bus Arbiter Master Status Register ..............................................................................7-24
7.6.29 G-Bus Arbiter Control Register......................................................................................... 7-24
CHAPTER 8. PCI/G-BUS BRIDGE...................................................................................................8-1
8.1 PCI/G-BUS BRIDGE (“PGB”)................................................................................................... 8-1
8.1.1 Overview.............................................................................................................................. 8-1
8.1.2 PCI / G-Bus Bridge Interface Signals..................................................................................8-4
8.2 THEORY OF OPERATION............................................................................................................ 8-5
8.2.1 G-Bus Write to PCI (Bridge Master Write).........................................................................8-5
8.2.2 G-Bus Master Reading from PCI (Bridge Master Read)..................................................... 8-6
8.2.3 PCI Master Writing to G-Bus Slave (Bridge Target Write)................................................. 8-9
8.2.4 PCI Master Reading from G-Bus Slave (Bridge Target Read).......................................... 8-10
8.2.5 Doorbell Feature...............................................................................................................8-11
8.2.6 PCI Transaction Commands Supported. ...........................................................................8-11
8.2.7 Lower Address Bits............................................................................................................ 8-12
8.2.8 G-Bus to PCI Address Mapping, Addition method............................................................8-12
8.2.9 PCI to G-Bus Address Mapping ........................................................................................8-13
8.2.10 Bus Error Handling Policies .............................................................................................8-13
8.2.11 PCI Bus Arbiter .................................................................................................................8-15

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TX7901 User’s Manual (Rev. 6.30T – Nov, 2001) iii
8.2.12 Reset...................................................................................................................................8-16
8.2.13 Retry requests ....................................................................................................................8-17
8.3 PGB MEMORY MAP ............................................................................................................... 8-18
8.3.1 PCI Configuration Registers..............................................................................................8-18
8.3.2 PGB G-Bus Registers.........................................................................................................8-20
8.4 REGISTER DUAL-PORTING...................................................................................................... 8-30
8.4.1 pgbCSR[1] Dual Porting...................................................................................................8-30
8.4.2 p2gBase[3] Dual Porting ..................................................................................................8-30
8.4.3 Protection Strategy............................................................................................................ 8-30
8.5 PCI CORE............................................................................................................................... 8-31
8.5.1 Overview............................................................................................................................ 8-31
8.5.2 Features.............................................................................................................................8-31
8.6 ARCHITECTURE ......................................................................................................................8-32
8.6.1 Major Internal Modules.....................................................................................................8-32
8.6.2 I/O Signals for PCI Core...................................................................................................8-34
8.6.3 TRDY_TIMEOUT .............................................................................................................. 8-36
8.6.4 RETRY_TIMEOUT ............................................................................................................8-36
8.6.5 PCI Target Delayed Read Handling.................................................................................. 8-36
8.7 CONFIGURATION REGISTER DESCRIPTIONS ............................................................................8-37
8.7.1 PCI Vendor ID Register.....................................................................................................8-37
8.7.2 PCI Device ID Register .....................................................................................................8-37
8.7.3 PCI Command Register..................................................................................................... 8-37
8.7.4 PCI Status Register............................................................................................................8-38
8.7.5 Device Revision Identification Register............................................................................. 8-38
8.7.6 Class Code Register...........................................................................................................8-39
8.7.7 Cache-Line Size Register...................................................................................................8-39
8.7.8 Master Latency Timer Register..........................................................................................8-40
8.7.9 Header Type.......................................................................................................................8-40
8.7.10 Subsystem Vendor ID.........................................................................................................8-40
8.7.11 Subsystem ID Register.......................................................................................................8-41
8.7.12 Interrupt Line Register.......................................................................................................8-41
8.7.13 Interrupt Pin Register........................................................................................................8-41
8.7.14 MIN_GNT Register............................................................................................................8-42
8.7.15 MAX_LAT Register............................................................................................................8-42
8.7.16 TRDY Timeout Value.........................................................................................................8-42
8.7.17 Retry Timeout Value .......................................................................................................... 8-43
CHAPTER 9. DMA CONTROLLER.................................................................................................9-1
9.1 MODES OF OPERATION............................................................................................................. 9-2
9.1.1 DMA Channel Priority.........................................................................................................9-2
9.1.2 Source and Destination........................................................................................................ 9-3
9.1.3 Block Transfers....................................................................................................................9-3
9.1.4 Slice Transfers .....................................................................................................................9-4
9.1.5 C790 Cycle Stealing ............................................................................................................9-4
9.1.6 Chain Mode .........................................................................................................................9-6
9.1.7 Appending to The End of a Chain........................................................................................ 9-6
9.1.8 Bus Error............................................................................................................................. 9-6
9.1.9 32-/64-bit G-Bus I/O............................................................................................................ 9-7
9.1.10 Memory Byte Alignment Support.........................................................................................9-7
9.1.11 Restarting a Disabled Channel............................................................................................9-8
9.1.12 Reprogramming an Active Channel..................................................................................... 9-8
9.1.13 Restrictions..........................................................................................................................9-8
9.2 REGISTERS................................................................................................................................9-9
9.2.1 Channel Control Registers (CCR0 - CCR7)......................................................................9-10
9.2.2 Channel Status Register (CSR0 – CSR7)...........................................................................9-13

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TX7901 User’s Manual (Rev. 6.30T – Nov, 2001) iv
9.2.3 Source Address Registers (SAR0 - SAR7)..........................................................................9-14
9.2.4 Destination Address Register (DAR0 - DAR7) .................................................................. 9-15
9.2.5 Byte Count Register (BCR0 – BCR7)................................................................................. 9-15
9.2.6 Next Record Pointer Registers (NRPR0 – NRPR7) ...........................................................9-16
9.2.7 Global Control and Status Register (GCSR) .....................................................................9-16
9.2.8 C790 Bus Error Address Register (CBEADDR)................................................................ 9-17
9.2.9 G-Bus Error Address Register (GBEADDR).....................................................................9-18
CHAPTER 10. PROGRAMMABLE TIMER/COUNTERS.............................................................10-1
10.1 FEATURES............................................................................................................................... 10-1
10.1.1 Interval Timer Mode..........................................................................................................10-1
10.1.2 Pulse Generator Mode....................................................................................................... 10-1
10.1.3 Watchdog Timer Mode.......................................................................................................10-1
10.1.4 Internal or External Clock Division ..................................................................................10-1
10.2 BLOCK DIAGRAMS.................................................................................................................. 10-2
10.3 SIGNALS .................................................................................................................................10-4
10.4 CONFIGURATION REGISTERS .................................................................................................. 10-5
10.4.1 Timer Control Registers TMTCR0, TMTCR1, TMTCR2 ................................................... 10-6
10.4.2 Interval Timer Mode Registers TMITMR0, TMITMR1, TMITMR2...................................10-7
10.4.3 Divider Registers TMCCDR0, TMCCDR1, TMCCDR2....................................................10-8
10.4.4 Pulse Generator Mode Registers TMPGMR1, TMPGMR2...............................................10-9
10.4.5 Watchdog Timer Mode Register (TMWTMR) Fields.......................................................10-10
10.4.6 Timer Interrupt Status Registers TMTISR0, TMTISR1, TMTISR2................................... 10-11
10.4.7 Fields for Timer Compare Registers A (TMCPRAx) and B (TMCPRBx)........................ 10-13
10.4.8 Timer Read Registers (TMTRR0, TMTRR1, TMTRR2).................................................... 10-14
10.5 PROGRAMMABLE TIMER/COUNTER OPERATION................................................................... 10-14
10.5.1 Interval Timer Mode Operation....................................................................................... 10-14
10.5.2 Pulse Generator Mode Operation ...................................................................................10-18
10.5.3 Watchdog Timer Mode Operation................................................................................... 10-20
10.5.4 Examples of Timer/Counter Timing................................................................................. 10-21
CHAPTER 11. INTERRUPT CONTROLLER.................................................................................11-1
11.1 INTRODUCTION....................................................................................................................... 11-1
11.2 OPERATION............................................................................................................................. 11-1
11.3 REGISTERS.............................................................................................................................. 11-2
11.3.1 Interrupt Status Register (IRSTAT)...................................................................................11-2
11.3.2 Interrupt Mask Register (IRMASK) .................................................................................. 11-3
CHAPTER 12. 10/100 IEEE802.3 MEDIA ACCESS CONTROLLER...........................................12-1
12.1 OVERVIEW.............................................................................................................................. 12-1
12.1.1 C790 and MAC DMA.........................................................................................................12-2
12.1.2 MAC and MII.....................................................................................................................12-3
12.2 MII (MEDIUM INDEPENDENT INTERFACE)..............................................................................12-4
12.3 MAC REGISTERS AND COUNTERS.......................................................................................... 12-5
12.3.1 Register Functionality and Field Descriptions..................................................................12-8
12.3.2 Counters........................................................................................................................... 12-28
12.3.3 MIIM (Media Independent Interface Management) ........................................................12-33
12.3.4 Address Filtering ............................................................................................................. 12-34
12.3.5 FIFO Addresses............................................................................................................... 12-36
12.4 MEMORY ORGANIZATION (FRAME DESCRIPTOR)................................................................. 12-37
12.4.1 Descriptor Lists and Data Buffers................................................................................... 12-37
12.4.2 Receive Descriptors......................................................................................................... 12-38
12.4.3 Transmit Descriptors....................................................................................................... 12-39
12.5 FUNCTIONAL DESCRIPTION ..................................................................................................12-42
12.5.1 DMA................................................................................................................................. 12-42

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12.5.2 FIFO Operation...............................................................................................................12-45
12.5.3 MII Interface.................................................................................................................... 12-49
12.5.4 Interrupt........................................................................................................................... 12-49
12.5.5 Reset.................................................................................................................................12-49
CHAPTER 13. REMOVED.................................................................................................................13-1
CHAPTER 14. UARTS WITH FIFOS ...............................................................................................14-1
14.1 OVERVIEW.............................................................................................................................. 14-1
14.1.1 Key Features...................................................................................................................... 14-2
14.1.2 Introduction .......................................................................................................................14-2
14.2 FUNCTIONAL DESCRIPTION ....................................................................................................14-2
14.2.1 Transmit Operation............................................................................................................14-2
14.2.2 Receive Operation .............................................................................................................14-3
14.2.3 Modem Control Lines........................................................................................................ 14-3
14.3 INTERFACE SIGNALS............................................................................................................... 14-3
14.4 UART DEVICE REGISTER DESCRIPTION................................................................................. 14-4
14.4.1 UART Device Register Addressing.................................................................................... 14-4
14.4.2 Receive Buffer Register (RBR0, RBR1).............................................................................14-6
14.4.3 Transmit Holding Registers (THR0, THR1)....................................................................... 14-6
14.4.4 Line Control Registers (LCR0, LCR1)...............................................................................14-6
14.4.5 Line Status Registers (LSR0,LSR1).................................................................................... 14-8
14.4.6 FIFO Control Registers (FCR0, FCR1) .......................................................................... 14-10
14.4.7 Interrupt Identification Registers (IIR0, IIR1)................................................................. 14-11
14.4.8 Interrupt Enable Registers (IER0, IER1).........................................................................14-13
14.4.9 Modem Control Registers (MCR0, MCR1)..................................................................... 14-13
14.4.10 Modem Status Registers (MSR0, MSR1).........................................................................14-14
14.4.11 Scratch Registers (SCR0, SCR1) .................................................................................... 14-15
14.4.12 Pre-scalar Register.........................................................................................................14-15
14.4.13 Divisor Latch LS and MS Registers (DLL, DLM)........................................................... 14-16
14.5 SPECIAL FEATURES...............................................................................................................14-17
14.5.1 Transmit Machine Timing................................................................................................ 14-17
14.5.2 THR Empty Interrupt Timing........................................................................................... 14-17
14.5.3 FIFO Reset Timing .......................................................................................................... 14-17
14.5.4 Rx Line Status Interrupt Timing....................................................................................... 14-17
14.5.5 Timeout interrupt timing..................................................................................................14-17
14.6 IMPLEMENTED RESTRICTIONS...............................................................................................14-18
14.6.1 Package pins.................................................................................................................... 14-18
CHAPTER 15. SERIAL PORT INTERFACE...................................................................................15-1
15.1 OVERVIEW.............................................................................................................................. 15-1
15.2 BOOT MEMORY SEQUENCER FOR WORD ACCESS (BM/W).................................................... 15-3
15.2.1 Boot ROM (64 KB) ............................................................................................................15-5
15.3 TSEI OVERVIEW ....................................................................................................................15-7
15.4 TSEI TRANSFERS ...................................................................................................................15-8
15.4.1 TSEI Clock Phase and Polarity Controls .......................................................................... 15-8
15.4.2 TSEI Data and Clock Timing............................................................................................. 15-8
15.5 TSEI SIGNALS AND PINS ........................................................................................................ 15-8
15.5.1 SCLK Pin...........................................................................................................................15-8
15.5.2 SDMISO and SDMOSI.......................................................................................................15-9
15.5.3 SS_N...................................................................................................................................15-9
15.6 TSEI TRANSFER FORMATS.....................................................................................................15-9
15.6.1 CPHA Equals 0 Format..................................................................................................... 15-9
15.6.2 CPHA EQUALS 1 FORMAT ........................................................................................... 15-10
15.7 MCU INTERFACE ................................................................................................................. 15-11

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TX7901 User’s Manual (Rev. 6.30T – Nov, 2001) vi
15.7.1 Read Access.....................................................................................................................15-11
15.7.2 Write Access.....................................................................................................................15-11
15.8 TSEI REGISTERS............................................................................................................... 15-12
15.8.1 Control Register (SECR).................................................................................................. 15-12
15.8.2 TSEI STATUS REGISTER (SESR)................................................................................... 15-13
15.8.3 TSEI Data Register (SEDR)............................................................................................. 15-16
15.8.4 TSEI Data Direction Register (DDCR) ...........................................................................15-16
15.9 TSEI SYSTEM ERRORS .........................................................................................................15-17
15.10 INTERRUPT GENERATION...................................................................................................... 15-17
15.10.1 Compatibility Mode........................................................................................................ 15-17
15.10.2 Toshiba Mode.................................................................................................................15-18
15.10.3 Interrupt Generation on TSIC0 ......................................................................................15-18
CHAPTER 16. CLOCKS.....................................................................................................................16-1
16.1 OVERVIEW.............................................................................................................................. 16-1
16.2 FEATURES............................................................................................................................... 16-2
16.3 OPERATION............................................................................................................................. 16-5
16.4 PERIPHERAL MODULE CLOCK ................................................................................................ 16-6
16.4.1 MAC Clock.........................................................................................................................16-6
16.4.2 UART Clock....................................................................................................................... 16-6
16.4.3 SPI Clock........................................................................................................................... 16-7
16.4.4 PCI Clock...........................................................................................................................16-7
16.4.5 Timer Clock ....................................................................................................................... 16-7
CHAPTER 17. PINS.............................................................................................................................17-1
17.1 JTAG BOUNDARY SCAN EXTERNAL TEST CHAIN CONFIGURATION......................................... 17-5

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TX7901 User’s Manual (Rev. 6.30T – Nov, 2001) i
TABLE OF FIGURES
FIGURE 3-1 TX7901 BLOCK DIAGRAM....................................................................................................... 3-1
FIGURE 3-2 A TYPICAL SYSTEM UTILIZING TX7901.................................................................................... 3-3
FIGURE 4-1 MEMORY MAP.......................................................................................................................... 4-1
FIGURE 5-1 C790 BLOCK DIAGRAM............................................................................................................. 5-2
FIGURE 6-1 TWO-STAGE DECODING............................................................................................................ 6-2
FIGURE 6-2 INITIAL SETTING AFTER RESET.................................................................................................6-3
FIGURE 6-3 EXAMPLE CONNECTION OF SINGLE-SIDED DIMMS..................................................................6-4
FIGURE 6-4 EXAMPLE CONNECTION OF DOUBLE-SIDED DIMMS................................................................6-5
FIGURE 6-5 SDRAM REGISTERS ................................................................................................................ 6-8
FIGURE 6-6 EXAMPLE TIMING PARAMETERS.............................................................................................6-10
FIGURE 6-7 CHECK MATRIX FOR DATA ECC CODE.................................................................................. 6-23
FIGURE 6-8 READ MODIFY WRITE TRANSACTION BY THE SDRAM CONTROLLER................................... 6-24
FIGURE 7-1 C790 BUS / G-BUS BRIDGE BLOCK DIAGRAM ......................................................................... 7-1
FIGURE 7-2 G-BRIDGE ADDRESS TRANSLATION .........................................................................................7-2
FIGURE 7-3 BI-ENDIAN SUPPORT ................................................................................................................7-3
FIGURE 8-1 TOP LEVEL BLOCK DIAGRAM ................................................................................................... 8-2
FIGURE 8-2 PGB SIGNALS........................................................................................................................... 8-3
FIGURE 8-3 WRITE TO PCI FROM G-BUS.....................................................................................................8-6
FIGURE 8-4 G-BUS MASTER READ FROM PCI.............................................................................................8-8
FIGURE 8-5 STATE DIAGRAM FOR G-BUS MASTER READ FROM PCI .......................................................... 8-8
FIGURE 8-6 PCI MASTER WRITING TO THE G-BUS ................................................................................... 8-10
FIGURE 8-7 PCI MASTER READING FROM G-BUS ..................................................................................... 8-11
FIGURE 8-8 G-BUS TO PCI ADDRESS MAPPING, ADDITION METHOD........................................................ 8-12
FIGURE 8-9 PCI TO G-BUS ADDRESS MAPPING ........................................................................................ 8-13
FIGURE 8-10 TRANSACTIONS WITH A G-BUS MASTER ............................................................................... 8-14
FIGURE 8-11 PCI ARBITER IMPLEMENTATION ..........................................................................................8-16
FIGURE 8-12 HIGH LEVEL ARCHITECTURE OF PCI CORE ..........................................................................8-33
FIGURE 8-13 PCI AND APPLICATION SIGNALS FOR PCI CORE................................................................... 8-34
FIGURE 9-1 ROUND-ROBIN PRIORITY SCHEME ........................................................................................... 9-3
FIGURE 9-2 DMA CHANNEL 5 ....................................................................................................................9-5
FIGURE 9-3 C790 BUS OPERATIONS WITH CYCLE STEALING ..................................................................... 9-5
FIGURE 9-4 C790 BUS OPERATIONS WITHOUT CYCLE STEALING............................................................... 9-5
FIGURE 9-5 C790 BUS UNALIGNED ADDRESS CYCLE BREAK DOWN.......................................................... 9-7
FIGURE 9-6 DMAC OPERATION.................................................................................................................. 9-8
FIGURE 10-1 TIMER MODULE CONNECTIONS INSIDE THE TX7901............................................................10-2
FIGURE 10-2 TIMER 0, TIMER 1, AND TIMER 2 CONNECTIONS.................................................................. 10-3
FIGURE 10-3 INTERVAL TIMER OPERATION USING INTERNAL CLOCK..................................................... 10-16
FIGURE 10-4 INTERVAL TIMER OPERATION USING EXTERNAL CLOCK.................................................... 10-16
FIGURE 10-5 PULSE GENERATOR MODE OPERATION.............................................................................. 10-19
FIGURE 10-6 WATCHDOG TIMER MODE OPERATION OF TIMER/COUNTER.............................................. 10-20
FIGURE 10-7 INTERVAL TIMING EXAMPLE USING INTERNAL CLOCK...................................................... 10-21
FIGURE 10-8 INTERVAL TIMING EXAMPLE USING EXTERNAL INPUT CLOCK .......................................... 10-21
FIGURE 10-9 PULSE GENERATOR MODE TIMING EXAMPLE .................................................................... 10-22
FIGURE 10-10 WATCHDOG TIMER TIMING EXAMPLE.............................................................................. 10-22
FIGURE 12-1 TX7901 10/100 MAC BLOCK DIAGRAM............................................................................. 12-1
FIGURE 12-2 MAC MEMORY SHARING WITH C790..................................................................................12-2
FIGURE 12-3 FIELDS OF MIIM CONTROL REGISTER ...............................................................................12-33
FIGURE 12-4 FIELDS OF MIIM DATA REGISTER...................................................................................... 12-34
FIGURE 12-5 IMPERFECT FILTERING OF INCOMING FRAMES.................................................................... 12-34
FIGURE 12-6 DESCRIPTOR RING AND CHAIN STRUCTURE ....................................................................... 12-37
FIGURE 12-7 RECEIVE DESCRIPTOR FORMAT.......................................................................................... 12-38
FIGURE 12-8 TRANSMIT DESCRIPTOR FORMAT.......................................................................................12-40
FIGURE 14-1 UART BLOCK DIAGRAM ..................................................................................................... 14-1

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TX7901 User’s Manual (Rev. 6.30T – Nov, 2001) ii
FIGURE 15-1 SPI MEMORY MAP............................................................................................................... 15-2
FIGURE 15-2 TSEI BLOCK DIAGRAM ........................................................................................................ 15-7
FIGURE 15-3 CPHA EQUALS 0 TRANSFER FORMAT.................................................................................. 15-9
FIGURE 15-4 CPHA EQUALS 1 TRANSFER FORMAT................................................................................ 15-10
FIGURE 15-5 MCU INTERFACE SIGNALING .............................................................................................15-11
FIGURE 15-6 TSIC0 BEHAVIOR, COMPATIBILITY MODE .........................................................................15-19
FIGURE 16-1 TX7901 CLOCK DOMAIN DIAGRAM.....................................................................................16-3
FIGURE 16-2 TX7901 CLOCK DISTRIBUTION DIAGRAM ...........................................................................16-4

Table Of Tables
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001) i
TABLE OF TABLES
TABLE 4-1 LIST OF 7901 DEVICE REGISTERS..............................................................................................4-3
TABLE 6-1 INITIAL VALUES AFTER RESET................................................................................................... 6-6
TABLE 6-2 EXAMPLE VALUES FOR FOUR DIMMS......................................................................................6-6
TABLE 6-3 LIST OF SDRAM MEMORY CONTROLLER REGISTERS............................................................... 6-7
TABLE 6-4 SDRAM MODE REGISTER SETTINGS ......................................................................................6-14
TABLE 7-1 LIST OF G-BUS BRIDGE REGISTERS (BASE ADDRESS = 0X1E00_2000) ....................................7-5
TABLE 7-2 SYSTEM CONFIGURATION REGISTER FIELDS ............................................................................. 7-6
TABLE 7-3 C790 BUS CONTROL REGISTER FIELDS ..................................................................................... 7-7
TABLE 7-4 C790 BUS STATUS REGISTER FIELDS ........................................................................................ 7-8
TABLE 7-5 C790 BUS BAD ADDRESS REGISTER FIELDS.............................................................................. 7-9
TABLE 7-6 CG UPPER I/O ADDRESS REGISTER FIELDS............................................................................... 7-9
TABLE 7-7 CG LOWER INTERNAL REGISTER ADDRESS REGISTER FIELDS ................................................ 7-10
TABLE 7-8 CG UPPER ROM ADDRESS REGISTER FIELDS.........................................................................7-10
TABLE 7-9 CG LOWER ROM ADDRESS REGISTER FIELDS........................................................................ 7-11
TABLE 7-10 CG UPPER PCI ADDRESS REGISTER FIELDS........................................................................ 7-11
TABLE 7-11 CG UPPER LOWER PCI ADDRESS REGISTER FIELDS ............................................................ 7-12
TABLE 7-12 GC UPPER INTERNAL REGISTER ADDRESS REGISTER FIELDS................................................ 7-12
TABLE 7-13 GC LOWER INTERNAL REGISTER ADDRESS REGISTER FIELDS .............................................. 7-13
TABLE 7-14 GC UPPER MEMORY ADDRESS REGISTER FIELDS ................................................................. 7-13
TABLE 7-15 GC LOWER MEMORY ADDRESS REGISTER FIELDS................................................................7-14
TABLE 7-16 C790 INTERRUPT STATUS REGISTER FIELDS ......................................................................... 7-14
TABLE 7-17 G-BUS INTERRUPT SOURCE TABLE........................................................................................ 7-15
TABLE 7-18 C790 INTERRUPT MASK REGISTER FIELDS............................................................................7-16
TABLE 7-19 C790 BUS LATENCY TIMER................................................................................................... 7-16
TABLE 7-20 NMI STATUS REGISTER.........................................................................................................7-17
TABLE 7-21 G-BUS MASTER LATENCY TIMER.......................................................................................... 7-17
TABLE 7-22 G-BUS BROKEN MASTER LATENCY TIMER ...........................................................................7-18
TABLE 7-23 G-BUS SLAVE LATENCY TIMER............................................................................................. 7-18
TABLE 7-24 G-BRIDGE RETRY TIMER FIELDS........................................................................................... 7-19
TABLE 7-25 THE GC CONTROL REGISTER FIELDS .................................................................................... 7-20
TABLE 7-26 G-BRIDGE STATUS REGISTER FIELDS.................................................................................... 7-21
TABLE 7-27 C790 BUS STATUS REGISTER FIELDS ....................................................................................7-22
TABLE 7-28 G-BUS ARBITER REQUEST STATUS REGISTER FIELDS........................................................... 7-22
TABLE 7-29 G-BUS ARBITRATION REQUEST TABLE .................................................................................7-23
TABLE 7-30 G-BUS ARBITER GRANTED REGISTER FIELDS .......................................................................7-23
TABLE 7-31 G-BUS ARBITER MASTER STATUS REGISTER FIELDS ............................................................ 7-24
TABLE 7-32 G-BUS ARBITER GRANTED REGISTER FIELDS .......................................................................7-24
TABLE 8-1 SIGNAL DESCRIPTION .................................................................................................................8-4
TABLE 8-2 G-BUS BURST SIZES .................................................................................................................. 8-9
TABLE 8-3 SUPPORTED PCI TRANSACTION TYPES..................................................................................... 8-11
TABLE 8-4 PGB PCI CONFIGURATION REGISTER MAP............................................................................. 8-18
TABLE 8-5 PCI WINDOW SIZES................................................................................................................. 8-19
TABLE 8-6 PGB REGISTER ADDRESS MAP................................................................................................ 8-20
TABLE 8-7 PGB CONTROL AND STATUS REGISTER FIELD DESCRIPTIONS.................................................8-21
TABLE 8-8 G2PUPPER ADDRESS REGISTER FIELD DEFINITIONS ................................................................8-23
TABLE 8-9 G2PLOWER ADDRESS REGISTER FIELD DESCRIPTIONS............................................................ 8-23
TABLE 8-10 G2PBASE ADDRESS REGISTER FIELD DESCRIPTIONS .............................................................8-24
TABLE 8-11 G2PCYCLETYPE REGISTER FIELD DEFINITIONS ..................................................................... 8-24
TABLE 8-12 IA ADDRESS REGISTER FIELD DEFINITIONS .......................................................................... 8-25
TABLE 8-13 P2GBASE ADDRESS REGISTER FIELD DESCRIPTIONS .............................................................8-26
TABLE 8-14 G2PSWAPCTRL REGISTER FIELD DESCRIPTIONS..................................................................... 8-27
TABLE 8-15 P2GSWAPCTRL REGISTER FIELD DESCRIPTIONS..................................................................... 8-28
TABLE 8-16 REGSWAPCTRL REGISTER FIELD DESCRIPTIONS ....................................................................8-29

Table Of Tables
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001) ii
TABLE 8-17 PROTECTION LEVELS............................................................................................................. 8-30
TABLE 8-18 ENABLES FROM PGB CORE TO I/O PADS, LISTED ALPHABETICALLY....................................8-35
TABLE 8-19 CONTROL AND DATA FROM I/O PADS TO CORE, LISTED ALPHABETICALLY .........................8-35
TABLE 8-20 CONTROL & DATA SIGNALS FROM CORE TO I/O PADS, LISTED ALPHABETICALLY ..............8-35
TABLE 8-21 CONFIGURATION PCI VENDOR ID REGISTER......................................................................... 8-37
TABLE 8-22 CONFIGURATION PCI DEVICE ID REGISTER........................................................................... 8-37
TABLE 8-23 CONFIGURATION PCI COMMAND REGISTER.......................................................................... 8-37
TABLE 8-24 CONFIGURATION PCI STATUS REGISTER............................................................................... 8-38
TABLE 8-25 CONFIGURATION DEVICE REVISION IDENTIFICATION REGISTER ...........................................8-38
TABLE 8-26 CONFIGURATION CLASS CODE REGISTER...............................................................................8-39
TABLE 8-27 CONFIGURATION CACHE-LINE SIZE REGISTER.......................................................................8-39
TABLE 8-28 CONFIGURATION MASTER LATENCY TIMER REGISTER .........................................................8-40
TABLE 8-29 HEADER TYPE REGISTER .......................................................................................................8-40
TABLE 8-30 SUBSYSTEM VENDOR ID REGISTER.......................................................................................8-40
TABLE 8-31 SUBSYSTEM ID REGISTER .....................................................................................................8-41
TABLE 8-32 INTERRUPT LINE REGISTER ................................................................................................... 8-41
TABLE 8-33 INTERRUPT PIN REGISTER...................................................................................................... 8-41
TABLE 8-34 MIN_GNT REGISTER............................................................................................................ 8-42
TABLE 8-35 MAX_LAT REGISTER...........................................................................................................8-42
TABLE 8-36 CONFIGURATION TRDY TIMEOUT VALUE............................................................................8-42
TABLE 8-37 CONFIGURATION RETRY TIMEOUT VALUE ............................................................................8-43
TABLE 9-1 BLOCK AND SLICE TRANSFER TYPES......................................................................................... 9-4
TABLE 9-2 DMAC REGISTERS.................................................................................................................... 9-9
TABLE 9-3 CHANNEL CONTROL REGISTER FIELD DESCRIPTIONS.............................................................. 9-11
TABLE 9-4 CHANNEL STATUS REGISTER FIELD DESCRIPTIONS.................................................................9-13
TABLE 9-5 SOURCE ADDRESS REGISTER FIELD DEFINITIONS.................................................................... 9-14
TABLE 9-6 DESTINATION ADDRESS REGISTER FIELD DEFINITIONS........................................................... 9-15
TABLE 9-7 CURRENT BYTE COUNT REGISTER FIELD DEFINITIONS ...........................................................9-15
TABLE 9-8 NEXT RECORD POINTER REGISTER FIELD DEFINITIONS .......................................................... 9-16
TABLE 9-9 GLOBAL CONTROL AND STATUS REGISTER FIELD DESCRIPTIONS........................................... 9-16
TABLE 9-10 C790 BUS ERROR ADDRESS REGISTER FIELD DESCRIPTIONS................................................ 9-17
TABLE 9-11 G-BUS ERROR ADDRESS REGISTER FIELD DESCRIPTIONS .....................................................9-18
TABLE 10-1 TIMER MODES AND CHANNELS .............................................................................................10-1
TABLE 10-2 TX7901 PROGRAMMABLE TIMER/COUNTER SIGNALS .......................................................... 10-4
TABLE 10-3 TIMER/COUNTER CONFIGURATION REGISTERS...................................................................... 10-5
TABLE 10-4 FIELD DESCRIPTIONS FOR TIMER CONTROL REGISTERS TMTCRX........................................10-6
TABLE 10-5 FIELDS DESCRIPTIONS OF INTERVAL TIMER MODE REGISTERS TMITMRX.......................... 10-7
TABLE 10-6 FIELD DESCRIPTIONS FOR DIVIDER REGISTERS TMCCDR0, TMCCDR1, TMCCDR2 ........10-8
TABLE 10-7 FIELD DESCRIPTIONS FOR PULSE GENERATOR MODE REGISTERS TMPGMRX..................... 10-9
TABLE 10-8 WATCHDOG TIMER MODE REGISTER (TMWTMR) FIELD DESCRIPTIONS...........................10-10
TABLE 10-9 FIELD DESCRIPTIONS FOR TIMER INTERRUPT STATUS REGISTERS TMTISRX..................... 10-11
TABLE 10-10 FIELD DESCRIPTIONS FOR TIME COMPARE REGISTERS TMCPRAX, TMCPRBX.............. 10-13
TABLE 10-11 FIELD DESCRIPTIONS OF TIMER READ REGISTERS TMTRRX............................................10-14
TABLE 10-12 INTERRUPT CONTROL WITH THE TIIE AND TZCE BITS...................................................... 10-15
TABLE 10-13 DIVIDER VALUES AND COUNTER FREQUENCIES GENERATED ............................................ 10-17
TABLE 11-1 MASKABLE INTERRUPT SOURCES.......................................................................................... 11-1
TABLE 11-2 INTERRUPT CONTROLLER REGISTERS....................................................................................11-2
TABLE 11-3 INTERRUPT STATUS REGISTER FIELD DESCRIPTION............................................................... 11-2
TABLE 11-4 INTERRUPT MASK REGISTER FIELD DESCRIPTION.................................................................11-3
TABLE 12-1 MII INTERFACE SIGNALS....................................................................................................... 12-4
TABLE 12-2 MAC CONFIGURATION REGISTERS .......................................................................................12-5
TABLE 12-3 MAC COUNTERS................................................................................................................... 12-6
TABLE 12-4 MIIM (MEDIA INDEPENDENT INTERFACE MANAGEMENT) REGISTERS ..................................12-7
TABLE 12-5 MAC “PERFECT TABLE” VALUES......................................................................................... 12-7
TABLE 12-6 MAC HASH TABLE VALUES ................................................................................................... 12-7

Table Of Tables
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001) iii
TABLE 12-7 CCREG REGISTER FIELD DESCRIPTIONS................................................................................. 12-8
TABLE 12-8 TFCREG REGISTER FIELD DESCRIPTIONS..............................................................................12-9
TABLE 12-9 RFCREG REGISTER FIELD DESCRIPTIONS ...........................................................................12-12
TABLE 12-10 RECEIVE MODES WHEN RXALL IS 1 OR 0 ........................................................................... 12-13
TABLE 12-11 TSREG REGISTER FIELD DESCRIPTIONS ............................................................................12-14
TABLE 12-12 RSREG REGISTER FIELD DESCRIPTIONS............................................................................ 12-16
TABLE 12-13 TIMREG REGISTER FIELD DESCRIPTIONS..........................................................................12-17
TABLE 12-14 TIREG REGISTER FIELD DESCRIPTIONS .............................................................................12-18
TABLE 12-15 RIMREG REGISTER FIELD DESCRIPTIONS .........................................................................12-19
TABLE 12-16 RIREG REGISTER FIELD DESCRIPTIONS............................................................................. 12-20
TABLE 12-17 STATION ADDRESS I REGISTER FIELD DESCRIPTIONS........................................................12-21
TABLE 12-18 STATION ADDRESS II REGISTER FIELD DESCRIPTIONS ......................................................12-21
TABLE 12-19 BUS ERROR ADDRESS REGISTER FIELD DESCRIPTIONS ..................................................... 12-22
TABLE 12-20 TPFTREG REGISTER FIELD DESCRIPTIONS........................................................................ 12-22
TABLE 12-21 VLAN TAG REGISTER FIELD DESCRIPTIONS..................................................................... 12-23
TABLE 12-22 TDPREG REGISTER FIELD DESCRIPTIONS .........................................................................12-23
TABLE 12-23 RDPREG REGISTER FIELD DESCRIPTIONS .........................................................................12-24
TABLE 12-24 CDPREG REGISTER FIELD DESCRIPTIONS .........................................................................12-24
TABLE 12-25 TCDREG REGISTER FIELD DESCRIPTIONS......................................................................... 12-25
TABLE 12-26 RCDREG REGISTER FIELD DESCRIPTIONS......................................................................... 12-25
TABLE 12-27 IPGREG REGISTER FIELD DESCRIPTIONS ..........................................................................12-26
TABLE 12-28 INTER PACKET GAP T VALUES FOR 100 MB / 10 MB......................................................... 12-26
TABLE 12-29 NBTBREG REGISTER FIELD DESCRIPTIONS ......................................................................12-27
TABLE 12-30 IPGT VALUES FOR 100 MB AND 10 MB............................................................................12-27
TABLE 12-31 MIIM CONTROL REGISTER FIELD DESCRIPTIONS.............................................................. 12-33
TABLE 12-32 MIIM DATA REGISTER FIELD DESCRIPTIONS.................................................................... 12-34
TABLE 12-33 PERFECT TABLE FIELD DESCRIPTIONS............................................................................... 12-35
TABLE 12-34 RECEIVE DESCRIPTOR FIELD DESCRIPTIONS......................................................................12-38
TABLE 12-35 TRANSMIT DESCRIPTOR FIELD DESCRIPTIONS................................................................... 12-40
TABLE 14-1 SERIAL I/O SIGNAL DESCRIPTIONS........................................................................................ 14-3
TABLE 14-2 DEVICE REGISTER ADDRESSING FOR UARTS 0 & 1: LITTLE ENDIAN MODE ........................14-5
TABLE 14-3 DEVICE REGISTER ADDRESSING FOR UARTS 0 & 1: BIG ENDIAN MODE ............................. 14-5
TABLE 14-4 LINE CONTROL REGISTER FIELD DESCRIPTIONS.................................................................... 14-6
TABLE 14-5 TRANSMIT AND RECEIVE CHARACTER SIZE...........................................................................14-6
TABLE 14-6 LINE STATUS REGISTER FIELDS.............................................................................................. 14-8
TABLE 14-7 FIFO CONTROL REGISTER FIELD DESCRIPTIONS................................................................. 14-10
TABLE 14-8 RECEIVE FIFO TRIGGER LEVELS.........................................................................................14-11
TABLE 14-9 FIELDS OF INTERRUPT IDENTIFICATION REGISTERS............................................................. 14-11
TABLE 14-10 INTERPRETATION OF THE FIELDS OF THE INTERRUPT IDENTIFICATION REGISTERS.............14-11
TABLE 14-11 FIELDS OF INTERRUPT ENABLE REGISTERS.........................................................................14-13
TABLE 14-12 MODEM CONTROL REGISTER FIELDS.................................................................................. 14-13
TABLE 14-13 MODEM STATUS REGISTER FIELDS.................................................................................... 14-14
TABLE 14-14 PRESCALER OUTPUT AND DIVIDE VALUES FOR VARIOUS CPU & G-BUS CLOCKS..............14-16
TABLE 14-15 CLOCK FREQUENCY AND PERCENT ERROR......................................................................... 14-16
TABLE 15-1 SPI REGISTER ADDRESSES (FOR TSEI) .................................................................................15-1
TABLE 15-2 TSEI SPECIFICATIONS ...........................................................................................................15-3
TABLE 16-1 TX7901 CLOCKS................................................................................................................... 16-1
TABLE 16-2 PLL SELECTION .................................................................................................................... 16-5
TABLE 16-3 CLOCK GEAR RATIO.............................................................................................................. 16-5
TABLE 16-4 EXAMPLE FREQUENCY RELATIONSHIP ..................................................................................16-6
TABLE 16-5 SPI CLOCK FREQUENCY........................................................................................................16-7
TABLE 17-1 TX7901 PIN FUNCTIONALITY................................................................................................. 17-1
TABLE 17-2 TX7901 PIN POSITIONS.......................................................................................................... 17-4

Handling Precautions

1 Using Toshiba Semiconductors Safely
1-1
1. Using Toshiba Semiconductors Safely
TOSHIBA are continually working to improve the quality and the reliability of their products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when
utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a
malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent products specifications. Also, please keep in mind
the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.

1 Using Toshiba Semiconductors Safely
1-2

2 Safety Precautions
2-1
2. Safety Precautions
This section lists important precautions which users of semiconductor devices (and anyone else)
should observe in order to avoid injury and damage to property, and to ensure safe and correct use
of devices.
Please be sure that you understand the meanings of the labels and the graphic symbol described
below before you move on to the detailed descriptions of the precautions.
[Explanation of labels]
[Explanation of labels][Explanation of labels]
[Explanation of labels]
Indicates an imminently hazardous situation which will result in death or
serious injury if you do not follow instructions.
Indicates a potentially hazardous situation which could result in death or
serious injury if you do not follow instructions.
Indicates a potentially hazardous situation which if not avoided, may result
in minor injury or moderate injury.
[Explanation of graphic symbol]
[Explanation of graphic symbol][Explanation of graphic symbol]
[Explanation of graphic symbol]
Graphic symbol Meaning
Indicates that caution is required (laser beam is dangerous to eyes).

2 Safety Precautions
2-2
2.1 General Precautions regarding Semiconductor Devices
Do not use devices under conditions exceeding their absolute maximum ratings (e.g. current, voltage, power dissipation or
temperature).
This may cause the device to break down, degrade its performance, or cause it to catch fire or explode resulting in injury.
Do not insert devices in the wrong orientation.
Make sure that the positive and negative terminals of power supplies are connected correctly. Otherwise the rated maximum
current or power dissipation may be exceeded and the device may break down or undergo performance degradation, causing it to
catch fire or explode and resulting in injury.
When power to a device is on, do not touch the device’s heat sink.
Heat sinks become hot, so you may burn your hand.
Do not touch the tips of device leads.
Because some types of device have leads with pointed tips, you may prick your finger.
When conducting any kind of evaluation, inspection or testing, be sure to connect the testing equipment’s electrodes or probes to
the pins of the device under test before powering it on.
Otherwise, you may receive an electric shock causing injury.
Before grounding an item of measuring equipment or a soldering iron, check that there is no electrical leakage from it.
Electrical leakage may cause the device which you are testing or soldering to break down, or could give you an electric shock.
Always wear protective glasses when cutting the leads of a device with clippers or a similar tool.
If you do not, small bits of metal flying off the cut ends may damage your eyes.

2 Safety Precautions
2-3
2.2 Precautions Specific to Each Product Group
2.2.1 Optical semiconductor devices
When a visible semiconductor laser is operating, do not look directly into the laser beam or look through the optical system.
This is highly likely to impair vision, and in the worst case may cause blindness.
If it is necessary to examine the laser apparatus, for example to inspect its optical characteristics, always wear the appropriate
type of laser protective glasses as stipulated by IEC standard IEC825-1.
Ensure that the current flowing in an LED device does not exceed the device’s maximum rated current.
This is particularly important for resin-packaged LED devices, as excessive current may cause the package resin to blow up,
scattering resin fragments and causing injury.
When testing the dielectric strength of a photocoupler, use testing equipment which can shut off the supply voltage to the
photocoupler. If you detect a leakage current of more than 100 µA, use the testing equipment to shut off the photocoupler’s
supply voltage; otherwise a large short-circuit current will flow continuously, and the device may break down or burst into flames,
resulting in fire or injury.
When incorporating a visible semiconductor laser into a design, use the device’s internal photodetector or a separate
photodetector to stabilize the laser’s radiant power so as to ensure that laser beams exceeding the laser’s rated radiant power
cannot be emitted.
If this stabilizing mechanism does not work and the rated radiant power is exceeded, the device may break down or the
excessively powerful laser beams may cause injury.
2.2.2 Power devices
Never touch a power device while it is powered on. Also, after turning off a power device, do not touch it until it has thoroughly
discharged all remaining electrical charge.
Touching a power device while it is powered on or still charged could cause a severe electric shock, resulting in death or serious
injury.
When conducting any kind of evaluation, inspection or testing, be sure to connect the testing equipment’s electrodes or probes to
the device under test before powering it on.
When you have finished, discharge any electrical charge remaining in the device.
Connecting the electrodes or probes of testing equipment to a device while it is powered on may result in electric shock, causing
injury.