Texas Instruments SLOU061A User manual

Universal Operational Amplifier
Single, Dual, Quad (SOIC)
Evaluation Module
With Shutdo n
April 2001 Mixed-Signal Products
User’s Guide
SLOU061A

IMPORTANT NOTICE
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Copyright 2001, Texas Instruments Incorporated

iii
Chapter Title—Attribute Reference
Preface
Related Documentation From Texas Instruments
J Amplifiers and Comparators Data Book (literature number
SLOD002). This data book contains data sheets and other
informationontheTI operationalamplifiersthatcanbeusedwith this
evaluation module.
J Power Supply Circuits Data Book (literature number SLVD002).
This data book contains data sheets and other information on the TI
shunt regulators that can be used with this evaluation module.
FCC Warning
This equipment is intended for use in a laboratory test environment only. It
generates, uses, and can radiate radio frequency energy and has not been
testedforcompliancewiththelimitsofcomputingdevices pursuant to subpart
Jofpart 15ofFCCrules,whicharedesignedtoprovidereasonableprotection
against radio frequency interference. Operation of this equipment in other
environments may cause interference with radio communications, in which
case the user at his own expense will be required to take whatever measures
may be required to correct this interference.
Trademarks
PowerPAD is a trademark of Texas Instruments.

iv

Running Title—Attribute Reference
v
Chapter Title—Attribute Reference
Contents
1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Design Features 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Power Requirements 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Evaluation Module Layout 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Physical Considerations 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Area 100—Single Device SOIC 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Area 200—Dual Device SOIC 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Area 300—Quad Device SOIC 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 General Power Dissipation Considerations 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 EVM Component Placement 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 EVM Board Layout 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Example Circuits 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Schematic Conventions 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Inverting Amplifier 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Noninverting Amplifier 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Differential Amplifier 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Sallen-Key Low-Pass Filter 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Sallen-Key High-Pass Filter 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 Two Operational Amplifier Instrumentation Amplifier 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 Quad Operational Amplifier Instrumentation Amplifier 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . .

Running Title—Attribute Reference
vi
Figures
2–1 Area 100 Schematic—Single Device, SOIC (8-pin) 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 Area 200 Schematic—Dual Device, SOIC (14-pin) 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 Area 300 Schematic—Quad Device, SOIC (16-pin) 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 Maximum Power Dissipation vs Free-Air Temperature 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 EVM Component Placement 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 EVM Board Layout—Top 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–7 EVM Board Layout—Bottom 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 Inverting Amplifier with Dual Supply Using Area 100 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 Noninverting Amplifier with Single Supply Using Area 100 3-3. . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Single Operational Amplifier Differential Amplifier With Single Supply Using Area 100 3-4. .
3–4 Sallen-Key Low-Pass Filter With Dual Supply Using Area 200 3-5. . . . . . . . . . . . . . . . . . . . . . .
3–5 Sallen-Key High-Pass Filter With Single Supply Using Area 200 3-7. . . . . . . . . . . . . . . . . . . . .
3–6 Two Operational Amplifier Instrumentation Amplifier With Single Supply Using Area 200 3-9
3–7 Quad Operational Amplifier Instrumentation Amplifier With Dual Supply Using Area 300 3-11
Table
2–1 Dissipation Rating Table 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1
Introduction
Introduction
This user’s guide describes the universal operational amplifier single, dual,
quad (SOIC) evaluation module (EVM) with shutdown (SLOP248). The EVM
simplifies evaluation of Texas Instruments surface-mount op amps with or
without shutdown feature.
Topic Page
1.1 Design Features 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Power Requirements 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1

Design Features
1-2 Introduction
1.1 Design Features
The EVM board design allows many circuits to be constructed easily and
quickly. There are three circuit development areas on the board, and each
uses IC amplifiers in the SOIC package. Area 100 is for a single operational
amplifier (op amp), with or without shutdown. It also features offset nulling pin
pads. Area 200 is for a dual op amp, with or without shutdown. Area 300 is for
a quad op amp, with or without shutdown. A few possible circuits include:
- Voltage follower
- Noninverting amplifier
- Inverting amplifier
- Simple or algebraic summing amplifier
- Difference amplifier
- Current to voltage converter
- Voltage to current converter
- Integrator/low-pass filter
- Differentiator/high-pass filter
- Instrumentation amplifier
- Sallen-Key filter
The EVM PCB is of two-layer construction, with a ground plane on the solder
side. Circuit performance should be comparable to final production designs.
1.2 Power Requirements
The devices and designs that are used dictate the input power requirements.
Three input terminals are provided for each area of the board:
Vx+ Positive input power for area x00 i.e., V1+ ⇒area 100
GNDx Ground reference for area x00 i.e., GND2 ⇒area 200
Vx–Negative input power for area x00 i.e., V3–⇒area 300
Each area has four bypass capacitors –two for the positive supply, and two
forthenegativesupply.Eachsupply shouldhavea1-µFto10-µFcapacitorfor
low-frequencybypassinganda0.01-µFto0.1-µFcapacitorforhigh-frequency
bypassing.
Whenusingsingle-supplycircuits,the negativesupplyisshortedtoground by
bridgingC104orC105inarea100,C209orC210inarea200,orC311orC312
in area 300. Power input is between Vx+ and GNDx. The voltage reference
circuitry is provided for single-supply applications that require a reference
voltage to be generated.

2-1
Evaluation Module Layout
Evaluation Module Layout
This chapter shows the universal operational amplifier single, dual, quad
(SOIC) evaluation module (EVM) with shutdown board layout, schematics of
each area, and describes the relationships between the three areas.
Topic Page
2.1 Physical Considerations 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Area 100—Single Device SOIC 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Area 200—Dual Device SOIC 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Area 300—Quad Device SOIC 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 General Power Dissipation Considerations 2–7. . . . . . . . . . . . . . . . . . . . . .
2.6 Component Placement 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Board Layout 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 2

Physical Considerations
2-2 Evaluation Module Layout
2.1 Physical Considerations
The EVM board has three circuit development areas. Each area can be
separatedfromtheothersbybreaking alongthescorelines.Thecircuitlayout
in each area supports an op amp package, voltage reference, and ancillary
devices. The op amp package is unique to each area as described in the
following paragraphs. The voltage reference and supporting devices are the
same for all areas. Surface-mount or through-hole components can be used
for all capacitors and resistors on the board.
The voltage reference can be either surface-mount or through-hole. If
surface-mount is desired, the TLV431ACDBV5 or TLV431AIDBV5 adjustable
shunt regulators can be used. If through hole is desired, the TLV431ACLP,
TLV431AILP, TL431CLP, TL431ACLP, TL431ILP, or TL431AILP adjustable
shunt regulators can be used. Refer to Texas Instruments’Power Supply
Circuits Data Book (literature number SLVD002) for details on usage of these
shunt regulators.
Each passive component (resistor or capacitor) has a surface mount 1206
footprint with through holes at 0.2″spacing on the outside of the 1206 pads.
C105,C106,C107,C207,C208,C209,C312,C314,andC315haveasurface
mount 1210 footprint with through holes at 0.2″spacing on the outside of the
1210 pads. Therefore, either surface-mount or through-hole parts can be
used. The potentiometer for the offset nulling feature in area 100 can also be
either a surface-mount or a through-hole unit.
Figures 2–1 through 2–3 show schematics for each of the board areas. The
schematics show all components that the board layout can accommodate.
Theseshouldonlybeusedasreference,sincenotallcomponentswillbeused
at any one time.

Physical Considerations
2-3
Evaluation Module Layout
2.2 Area 100—Single Device SOIC
Area 100 uses 1xx reference designators, and is compatible with a single op
amp, with or without shutdown, packaged as an 8-pin SOIC. This
surface-mount package is designated by a D suffix in TI part numbers, as in
TxxxxCD, TxxxxID, etc.
Offset nulling can be extremely important in some applications. The EVM
accommodates TI IC op amps that provide this feature. The input offset can
be adjusted by connecting a 100-kΩpotentiometer between terminals 1 and
5 of the device and connecting the wiper to VCC–via a resistor (R101) as
shown below. This resistor is used to fine tune the offset adjustment. For
example, when using the TLC070 or TLC071 device and a 100-kΩnulling
potentiometer, the offset voltage adjustment is ±10 mV when R101 is 5.6 kΩ
and ±3 mV when R101 is 20 kΩ.
When using the nonshutdown version of the device, pin 8 of the IC is a no
connect.
Figure 2–1 shows the area 100 schematic.
Figure 2–1.Area 100 Schematic—Single Device, SOIC (8 pin)
C107 C108
C105 C104
V1+
V1–
V1+
GND1
V1–
Power Supply Bypass
+
–
14
3
2
V1+
V1–
R112
C109
R114 C110
R110
R109
R104
R103
R102
R105
C101
C102
OUT
A101–
A102–
A103+
A104+
U101 SD
C103
R106 A1 FLT
6
8
7
5
R101
R111
U102
R113
Voltage Reference
V1+ VREF1
R108
C106
V1–
R107

Physical Considerations
2-4 Evaluation Module Layout
2.3 Area 200—Dual Device SOIC
Area 200 uses 2xx reference designators, and is compatible with dual op
amps, with or without shutdown, packaged as an 8-pin (without shutdown) or
14-pin (with shutdown) SOIC. This package is designated by a D suffix in TI
part numbers, as in TxxxxCD.
When using the nonshutdown version of the device, ensure that the IC is
aligned at the top of the IC pad array—the last six PCB pads (three on each
side—pins 5, 6, 7, 8, 9, and 10) will not be used.
Figure 2–2 shows the area 200 schematic.
Figure 2–2.Area 200 Schematic—Dual Device, SOIC (14 pin)
B2/SD
C206 C207
C209 C210
V2+
V2–
V2+
GND2
V2–
Power Supply Bypass
+
–
14
1
4
3
2
V2+
V2–
R212
C215
R216 C211
R221
R220
R218
R219
R217
R215
C212
C213
A2OUT
1/2 Dual Op Amp
A201–
A202–
A203+
A204+
+
–
R206
C202
R207 C203
R204
R203
R205
R201
R202
R209
C204
C201
B2OUT
1/2 Dual Op Amp
B201–
B202–
B203+
B204+
U201a
U201b
13
11
12
C214
R214 A2 FLT
C205
R208 B2 FLT
A2/SD
6
9
R211
U202
R213
Voltage Reference
V2+ VREF2
R210
C208

Physical Considerations
2-5
Evaluation Module Layout
2.4 Area 300—Quad Device SOIC
Area 300 uses 3xx reference designators, and is compatible with quad op
amps, with or without shutdown, packaged in a 14-pin (without shutdown) or
16-pin (with shutdown) SOIC. This surface-mount package is designated by
a D suffix in TI part numbers, as in TxxxxID.
When using the nonshutdown version of the device, ensure that the IC is
aligned at the top of the IC pad array—the last two PCB pads (one on each
side—pins 8 and 9) will not be used.
Figure 2–3 shows the area 300 schematic.

Physical Considerations
2-6 Evaluation Module Layout
Figure 2–3.Area 300 Schematic—Quad Device SOIC (16 pin)
C313 C314
C311 C312
V3+
V3–
V3+
GND3
V3–
Power Supply Bypass +
–
4
1
13
3
2
V3+
V3–
R302
C301
R304 C302
R301
R303
R305
R306
R308
R307
C304
C303
A3 OUT
A301–
A302–
A303+
A304+
U301A
C305
R309 A3 FLT
AB3/SD
8
+
–7
5
6
R318
C308
R314 C310
R310
R312
R317
R313
R315
R311
C307
C309
B3 OUT
B301–
B302–
B303+
B304+ U301B
C306
R316 B3 FLT
+
–10
12
11
R325
C316
R323 C317
R322
R324
R326
R327
R329
R328
C318
C319
C3 OUT
C301–
C302–
C303+
C304+
U301C
C320
R330
CD3/SD
9
+
–16
14
15
R339
C321
R331 C324
R332
R333
R334
R335
R336
R337
C322
C325
D3 OUT
D301–
D302–
D303+
D304+ U301D
C323
R338
C3 FLT
D3 FLT
R320
U302
R319
Voltage Reference
V1+ VREF3
R321
C315

General Power Dissipation Considerations
2-7
Evaluation Module Layout
2.5 General Power Dissipation Considerations
For a given θJA, the maximum power dissipation is shown in Figure 2–4 and is calculated by the
following formula:
PD +ǒ
TMAX–TA
q
JA
Ǔ
Where: PD= Maximum power dissipation of Txxxx IC (watts)
TMAX= Absolute maximum junction temperature (150°C)
TA= Free-air temperature (°C)
θJA = θJC +θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
Figure 2–4.Maximum Power Dissipation vs Free-Air Temperature
2
1.5
1
0–55 –25 5
Maximum Power Dissipation –W
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
35
TA–Free-Air Temperature –°C
65 95 125
SOIC (16-pin)
Package
Low-K Test PCB
θJA = 114.7°C/W
SOIC (8-pin)
Package
Low-K Test PCB
SOIC (14-pin)
Package
Low-K Test PCB
TJ= 150°C
0.5
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Table 2–1.Dissipation Rating Table
PACKAGE θJC
(°C/W) θJA (°C/W) TA≤25°C POWER RATING
D (8) 38.3 176 710 mW
D (14) 26.9 122.3 1022 mW
D (16) 25.7 114.7 1090 mW

EVM Component Placement
2-8 Evaluation Module Layout
2.6 EVM Component Placement
Figure 2–5 shows component placement for the EVM board.
Figure 2–5.EVM Component Placement

EVM Board Layout
2-9
Evaluation Module Layout
2.7 EVM Board Layout
Figures 2–6 and 2–7 show the EVM top and bottom board layouts,
respectively.
Figure 2–6.EVM Board Layout—Top

EVM Board Layout
2-10 Evaluation Module Layout
Figure 2–7.EVM Board Layout—Bottom

3-1
Example Circuits
Example Circuits
This chapter shows and discusses several example circuits that can be
constructedusing the universal operational amplifierEVM. The circuits are all
classic designs that can be found in most operational amplifier design books.
Topic Page
3.1 Schematic Conventions 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Inverting Amplifier 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Noninverting Amplifier 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Differential Amplifier 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Sallen-Key Low-Pass Filter 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Sallen-Key High-Pass Filter 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 Two Operational Amplifier Instrumentation Amplifier 3–8. . . . . . . . . . . .
3.8 Quad Operational Amplifier Instrumentation Amplifier 3–10. . . . . . . . .
Chapter 3

Schematic Conventions
3-2 Example Circuits
3.1 Schematic Conventions
Figures 3–1 through 3–6 show schematic examples of circuits that can be
constructedusingtheuniversaloperationalamplifierEVMwithshutdown.The
components that are placed on the board are shown in bold. Unused
components are blanked out. Jumpers and other changes are noted. These
examples are only a few of the many circuits that can be built.
3.2 Inverting Amplifier
Figure 3–1 shows area 100 equipped with a single operational amplifier
configured as an inverting amplifier using dual power supplies.
Basic setup is done by choice of input and feedback resistors. The transfer
function for the circuit as shown is:
VOUT
+* VIN R112
R109
To cancel the effects of input bias current, set R105 = R112 || R109, or use a
0-Ωjumper for R105 if the operational amplifier is a low input bias operational
amplifier.
Figure 3–1.Inverting Amplifier With Dual Supply Using Area 100
C107 C108
C105 C104
V1+
V1–
V1+
GND1
V1–
Power Supply Bypass
+
–76
4
3
2
V1+
V1–
R112
C109
R114 C110
R110
R109
R104
R103
R102
R105
C101
C102
A OUT
A101–
A102–
A103+
A104–
R111 C
RAU102
R113
Voltage Reference
U101
V1+
VREF1
R108
+
–Vin
VOUT = –VIN R112
R109
R105 = R112 II R109,
or Short if Using Low
Input Bias Op Amp
Not Used
0.1 µF 10 µF
0.1 µF 10 µF
8SD
A1 FLT
R106
C103
C106
+
–
1
3
2
V1–
5
R101
R107
Optional
5.6 k
100 k
6