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AM1808
SPRS653E –FEBRUARY 2010–REVISED MARCH 2014
AM1808 ARM
®
Microprocessor
1 AM1808 ARM Microprocessor
1.1 Features
1
• 375- and 456-MHz ARM926EJ-S™ RISC MPU • Programmable Real-Time Unit Subsystem
(PRUSS)
• ARM926EJ-S Core – Two Independent Programmable Real-Time Unit
– 32-Bit and 16-Bit ( Thumb®) Instructions (PRU) Cores
– Single-Cycle MAC • 32-Bit Load-Store RISC Architecture
– ARM Jazelle®Technology • 4KB of Instruction RAM per Core
– Embedded ICE-RT™ for Real-Time Debug • 512 Bytes of Data RAM per Core
• ARM9™ Memory Architecture • PRUSS can be Disabled via Software to
– 16KB of Instruction Cache Save Power
– 16KB of Data Cache • Register 30 of Each PRU is Exported from
– 8KB of RAM (Vector Table) the Subsystem in Addition to the Normal R31
– 64KB of ROM Output of the PRU Cores.
• Enhanced Direct Memory Access Controller 3 – Standard Power-Management Mechanism
(EDMA3): • Clock Gating
– 2 Channel Controllers • Entire Subsystem Under a Single PSC Clock
– 3 Transfer Controllers Gating Domain
– 64 Independent DMA Channels – Dedicated Interrupt Controller
– 16 Quick DMA Channels – Dedicated Switched Central Resource
– Programmable Transfer Burst Size • USB 1.1 OHCI (Host) with Integrated PHY (USB1)
• 128KB of On-Chip Memory • USB 2.0 OTG Port with Integrated PHY (USB0)
• 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and – USB 2.0 High- and Full-Speed Client
DDR2 Interfaces) – USB 2.0 High-, Full-, and Low-Speed Host
• Two External Memory Interfaces: – End Point 0 (Control)
– EMIFA – End Points 1,2,3,4 (Control, Bulk, Interrupt or
• NOR (8- or 16-Bit-Wide Data) ISOC) RX and TX
• NAND (8- or 16-Bit-Wide Data) • One Multichannel Audio Serial Port (McASP):
• 16-Bit SDRAM with 128-MB Address Space – Transmit and Receive Clocks
– DDR2/Mobile DDR Memory Controller with one – Two Clock Zones and 16 Serial Data Pins
of the following: – Supports TDM, I2S, and Similar Formats
• 16-Bit DDR2 SDRAM with 256-MB Address – DIT-Capable
Space – FIFO Buffers for Transmit and Receive
• 16-Bit mDDR SDRAM with 256-MB Address • Two Multichannel Buffered Serial Ports (McBSPs):
Space – Transmit and Receive Clocks
• Three Configurable 16550-Type UART Modules: – Supports TDM, I2S, and Similar Formats
– With Modem Control Signals – AC97 Audio Codec Interface
– 16-Byte FIFO – Telecom Interfaces (ST-Bus, H100)
– 16x or 13x Oversampling Option – 128-Channel TDM
• LCD Controller – FIFO Buffers for Transmit and Receive
• Two Serial Peripheral Interfaces (SPIs) Each with • 10/100 Mbps Ethernet MAC (EMAC):
Multiple Chip Selects – IEEE 802.3 Compliant
• Two Multimedia Card (MMC)/Secure Digital (SD)
Card Interfaces with Secure Data I/O (SDIO) – MII Media-Independent Interface
Interfaces – RMII Reduced Media-Independent Interface
• Two Master and Slave Inter-Integrated Circuits – Management Data I/O (MDIO) Module
( I2C Bus™)
• One Host-Port Interface (HPI) with 16-Bit-Wide
Muxed Address and Data Bus For High Bandwidth
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

AM1808
SPRS653E –FEBRUARY 2010–REVISED MARCH 2014 www.ti.com
• Video Port Interface (VPIF): • Three 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
– Two 8-Bit SD (BT.656), Single 16-Bit or Single
Raw (8-, 10-, and 12-Bit) Video Capture • One 64-Bit General-Purpose or Watchdog Timer
Channels (Configurable as Two 32-Bit General-Purpose
Timers)
– Two 8-Bit SD (BT.656), Single 16-Bit Video
Display Channels • Two Enhanced High-Resolution Pulse Width
Modulators (eHRPWMs):
• Universal Parallel Port (uPP): – Dedicated 16-Bit Time-Base Counter with
– High-Speed Parallel Interface to FPGAs and Period and Frequency Control
Data Converters – 6 Single-Edge Outputs, 6 Dual-Edge Symmetric
– Data Width on Both Channels is 8- to 16-Bit Outputs, or 3 Dual-Edge Asymmetric Outputs
Inclusive – Dead-Band Generation
– Single-Data Rate or Dual-Data Rate Transfers – PWM Chopping by High-Frequency Carrier
– Supports Multiple Interfaces with START,
ENABLE, and WAIT Controls – Trip Zone Input
• Serial ATA (SATA) Controller: • Three 32-Bit Enhanced Capture (eCAP) Modules:
– Supports SATA I (1.5 Gbps) and SATA II – Configurable as 3 Capture Inputs or 3 Auxiliary
(3.0 Gbps) Pulse Width Modulator (APWM) Outputs
– Supports all SATA Power-Management – Single-Shot Capture of up to Four Event Time-
Features Stamps
– Hardware-Assisted Native Command Queueing • 361-Ball Pb-Free Plastic Ball Grid Array (PBGA)
(NCQ) for up to 32 Entries [ZCE Suffix], 0.65-mm Ball Pitch
– Supports Port Multiplier and Command-Based • 361-Ball Pb-Free PBGA [ZWT Suffix], 0.80-mm
Switching Ball Pitch
• Real-Time Clock (RTC) with 32-kHz Oscillator and • Commercial or Extended Temperature
Separate Power Rail
1.2 Applications
• Gaming • Data Concentrators
• Medical, Healthcare, Fitness • Building Automation
• Printers • Set Top Box
• ePOS • Industrial Automation
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1.3 Description
The AM1808 ARM Microprocessor is a low-power applications processor based on ARM926EJ-S.
The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs)
to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and
high processing performance life through the maximum flexibility of a fully integrated mixed processor
solution.
The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and
processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and
memory system can operate continuously.
The ARM core has a coprocessor 15 (CP15), protection module, and data and program memory
management units (MMUs) with table look-aside buffers. The ARM core processor has separate 16-KB
instruction and 16-KB data caches. Both are four-way associative with virtual index virtual tag (VIVT). The
ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.
The peripheral set includes: a 10/100 Mbps Ethernet media access controller (EMAC) with a management
data input/output (MDIO) module; one USB2.0 OTG interface; one USB1.1 OHCI interface; two inter-
integrated circuit (I2C Bus) interfaces; one multichannel audio serial port (McASP) with 16 serializers and
FIFO buffers; two multichannel buffered serial ports (McBSPs) with FIFO buffers; two serial peripheral
interfaces (SPIs) with multiple chip selects; four 64-bit general-purpose timers each configurable (one
configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-
purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and
event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and
CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced
capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width
modulator (APWM) outputs; two external memory interfaces; an asynchronous and SDRAM external
memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR
controller.
The EMAC provides an efficient interface between the device and a network. The EMAC supports both
10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an
MDIO interface is available for PHY configuration. The EMAC supports the MII and RMII interfaces.
The SATA controller provides a high-speed interface to mass data storage devices. The SATA controller
supports SATA I (1.5 Gbps) and SATA II (3.0 Gbps).
The universal parallel port (uPP) provides a high-speed interface to many types of data converters,
FPGAs or other parallel devices. The uPP supports programmable data widths between 8- to 16-bits on
both channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE,
and WAIT signals to provide control for a variety of data converters.
A video port interface (VPIF) is included providing a flexible video I/O port.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections in this document and
the associated peripheral reference guides.
The device has a complete set of development tools for the ARM processor. These tools include C
compilers, and scheduling, and a Windows®debugger interface for visibility into source code execution.
Device Information
PART NUMBER PACKAGE BODY SIZE
AM1808ZCE NFBGA (361) 13,00 mm x 13,00 mm
AM1808ZWT NFBGA (361) 16,00 mm x 16,00 mm
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Switched Central Resource (SCR)
16KB
I-Cache
16KB
D-Cache
4KB ETB
ARM926EJ-S CPU
With MMU
ARM Subsystem
JTAG Interface
System Control
Input
Clock(s)
64KB ROM
8KB RAM
(Vector Table)
Power/Sleep
Controller
Pin
Multiplexing
PLL/Clock
Generator
w/OSC
General-
Purpose
Timer (x3)
Serial Interfaces
Audio Ports
McASP
w/FIFO
DMA
Peripherals
Display Internal Memory
LCD
Ctlr
128KB
RAM
External Memory InterfacesConnectivity
EDMA3
(x2)
Control Timers
ePWM
(x2)
eCAP
(x3)
EMIFA(8b/16B)
NAND/Flash
16b SDRAM
DDR2/MDDR
Controller
RTC/
32-kHz
OSC
I C
(x2)
2SPI
(x2)
UART
(x3)
McBSP
(x2)
Video
VPIF
Parallel Port
uPP
EMAC
10/100
(MII/RMII)
MDIO
USB1.1
OHCI Ctlr
PHY
USB2.0
OTG Ctlr
PHY
HPI
MMC/SD
(8b)
(x2)
SATA
Customizable Interface
PRU Subsystem
Memory
Protection
AM1808
SPRS653E –FEBRUARY 2010–REVISED MARCH 2014 www.ti.com
1.4 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the device.
(1) Note: Not all peripherals are available at the same time due to multiplexing.
Figure 1-1. Functional Block Diagram
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Table of Contents
1 AM1808 ARM Microprocessor......................... 16.10 External Memory Interface A (EMIFA) .............. 98
1.1 Features .............................................. 16.11 DDR2/mDDR Memory Controller .................. 109
1.2 Applications........................................... 26.12 Memory Protection Units .......................... 122
1.3 Description............................................ 36.13 MMC / SD / SDIO (MMCSD0, MMCSD1) ......... 125
1.4 Functional Block Diagram ............................ 46.14 Serial ATA Controller (SATA)...................... 128
2 Revision History ......................................... 66.15 Multichannel Audio Serial Port (McASP) .......... 133
3 Device Overview ......................................... 76.16 Multichannel Buffered Serial Port (McBSP)........ 142
3.1 Device Characteristics................................ 76.17 Serial Peripheral Interface Ports (SPI0, SPI1)..... 151
3.2 Device Compatibility.................................. 86.18 Inter-Integrated Circuit Serial Ports (I2C).......... 172
6.19 Universal Asynchronous Receiver/Transmitter
3.3 ARM Subsystem...................................... 8(UART)............................................. 176
3.4 Memory Map Summary ............................. 11 6.20 Universal Serial Bus OTG Controller (USB0)
3.5 Pin Assignments .................................... 14 [USB2.0 OTG] ..................................... 178
3.6 Pin Multiplexing Control............................. 17 6.21 Universal Serial Bus Host Controller (USB1)
3.7 Terminal Functions.................................. 18 [USB1.1 OHCI]..................................... 185
3.8 Unused Pin Configurations.......................... 58 6.22 Ethernet Media Access Controller (EMAC)........ 186
4 Device Configuration.................................. 60 6.23 Management Data Input/Output (MDIO)........... 193
4.1 Boot Modes ......................................... 60 6.24 LCD Controller (LCDC) ............................ 195
4.2 SYSCFG Module.................................... 60 6.25 Host-Port Interface (UHPI)......................... 210
4.3 Pullup/Pulldown Resistors .......................... 63 6.26 Universal Parallel Port (uPP) ...................... 218
5 Specifications........................................... 64 6.27 Video Port Interface (VPIF) ........................ 223
5.1 Absolute Maximum Ratings Over Operating 6.28 Enhanced Capture (eCAP) Peripheral............. 228
Junction Temperature Range 6.29 Enhanced High-Resolution Pulse-Width Modulator
(Unless Otherwise Noted) ................................. 64 (eHRPWM)......................................... 231
5.2 Handling Ratings.................................... 64 6.30 Timers.............................................. 236
5.3 Recommended Operating Conditions............... 65 6.31 Real Time Clock (RTC) ............................ 238
5.4 Notes on Recommended Power-On Hours (POH) .67 6.32 General-Purpose Input/Output (GPIO)............. 241
5.5 Electrical Characteristics Over Recommended 6.33 Programmable Real-Time Unit Subsystem (PRUSS)
Ranges of Supply Voltage and Operating Junction ..................................................... 245
Temperature (Unless Otherwise Noted) ............ 68 6.34 Emulation Logic.................................... 248
6 Peripheral Information and Electrical 7 Device and Documentation Support.............. 256
Specifications........................................... 69 7.1 Device Support..................................... 256
6.1 Parameter Information .............................. 69
6.2 Recommended Clock and Control Signal Transition 7.2 Documentation Support............................ 257
Behavior............................................. 70 7.3 Community Resources............................. 257
6.3 Power Supplies...................................... 70 7.4 Trademarks ........................................ 257
6.4 Reset ................................................ 71 7.5 Electrostatic Discharge Caution ................... 258
6.5 Crystal Oscillator or External Clock Input........... 75 7.6 Glossary............................................ 258
6.6 Clock PLLs .......................................... 76 8 Mechanical Packaging and Orderable
6.7 Interrupts ............................................ 81 Information............................................. 258
6.8 Power and Sleep Controller (PSC).................. 87 8.1 Thermal Data for ZCE Package ................... 258
6.9 EDMA ............................................... 92 8.2 Thermal Data for ZWT Package................... 259
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2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data manual revision history highlights the changes made to the SPRS653D device-specific data
manual to make it an SPRS653E revision.
Revision History
SEE ADDITIONS/MODIFICATIONS/DELETIONS
• Turned on Navigation Icons on top of first page
• Moved Trademarks information from first page to within Section 7, Device and Documentation
Global Support.
• Moved ESDS Warning to within Section 7, Device and Documentation Support.
• Updated Features, Applications, and Description for consistency and translation.
Section 1.3 Added NEW Device Information Table.
Description Table 3-3 thru Table 3-27:
Section 3.7 • Updated/Changed footnote beginning with "IPD = Internal Pulldown resistor..."; added
Terminal Functions sentence "For more detailed information on pullup/pulldown..."
Table 3-19, Universal Serial Bus (USB) Terminal Functions
Section 3.7.17
Universal Serial Bus Modules • Updated/Changed the capacitor value in USB0_VDDA12 pin DESCRIPTION from "1 μF" to
(USB0, USB1) "0.22-μF"
Table 3-30, Unused USB0 and USB1 Signal Configurations:
Section 3.8 • Updated/Changed USB0_VDDA12 row by combining two columns and changing text from
Unused Pin Configurations "...to an external filter capacitor" to "...to an external 0.22-μF filter capacitor"
Updated/Changed title from "Device Operating Conditions" to "Specifications"
Section 5.2, Handling Ratings:
Section 5
Specifications • Split handling, ratings, and certifications from the Abs Max table and placed in NEW Handling
Ratings table.
Section 5.4 Table 5-1, Recommended Power-On Hours:
Notes on Recommended • Updated/Changed all applicable Silicon Revisions from "B" to "B/E"
Power-On Hours Figure 6-12, Asynchronous Memory Read Timing for EMIFA:
Section 6.10.5 • Added vertical lines to show difference between Setup, Strobe, and Hold
EMIFA Electrical/Timing Figure 6-13, Asynchronous Memory Write Timing for EMIFA:
• Added vertical lines to show difference between Setup, Strobe, and Hold
Table 6-45, SATA Routing Specifications:
Section 6.14.2.4
Routing Specifications • Added NEW footnote beginning with "The SATA_REFCLK(P/N)..."
Section 7.1.2 Figure 7-1, Device Nomenclature:
Device and Development- • Added "E = Silicon Revision 2.3" under SILICON REVISION
Support Tool Nomenclature
Section 7.6 Added NEW section.
Glossary
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3 Device Overview
3.1 Device Characteristics
Table 3-1 provides an overview of the device. The table shows significant features of the device, including
the capacity of on-chip RAM, peripherals, and the package type with pin count.
Table 3-1. Characteristics of the Device
HARDWARE FEATURES AM1808
DDR2, 16-bit bus width, up to 156 MHz
DDR2/mDDR Controller Mobile DDR, 16-bit bus width, up to 150 MHz
Asynchronous (8/16-bit bus width) RAM, Flash,
EMIFA 16-bit SDRAM, NOR, NAND
Flash Card Interface MMC and SD cards supported
64 independent channels, 16 QDMA channels,
EDMA3 2 channel controllers, 3 transfer controllers
4 64-Bit General Purpose (each configurable as 2 separate
Timers 32-bit timers, one configurable as Watch Dog)
UART 3 (each with RTS and CTS flow control)
SPI 2 (Each with one hardware chip select)
I2C 2 (both Master/Slave)
Peripherals Multichannel Audio Serial Port [McASP] 1 (each with transmit/receive, FIFO buffer, 16 serializers)
Not all peripherals pins
are available at the Multichannel Buffered Serial Port [McBSP] 2 (each with transmit/receive, FIFO buffer, 16)
same time (for more 10/100 Ethernet MAC with Management Data I/O 1 (MII or RMII Interface)
detail, see the Device
Configurations section). 4 Single Edge, 4 Dual Edge Symmetric, or
eHRPWM 2 Dual Edge Asymmetric Outputs
eCAP 3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs
USB 2.0 (USB0) High-Speed OTG Controller with on-chip OTG PHY
USB 1.1 (USB1) Full-Speed OHCI (as host) with on-chip PHY
General-Purpose Input/Output Port 9 banks of 16-bit
LCD Controller 1
SATA Controller 1 (Supports both SATA I and SATAII)
Universal Parallel Port (uPP) 1
Video Port Interface (VPIF) 1 (video in and video out)
PRU Subsystem (PRUSS) 2 Programmable PRU Cores
Size (Bytes) 168KB RAM
ARM
16KB I-Cache
16KB D-Cache
On-Chip Memory Organization 8KB RAM (Vector Table)
64KB ROM
ADDITIONAL MEMORY
128KB RAM
JTAG BSDL_ID DEVIDR0 Register 0x0B7D_102F
CPU Frequency MHz ARM926 375 MHz (1.2V) or 456 MHz (1.3V)
1.2 V nominal for 375 MHz version
Core (V) 1.3 V nominal for 456 MHz version
Voltage I/O (V) 1.8V or 3.3 V
13 mm x 13 mm, 361-Ball 0.65 mm pitch, PBGA (ZCE)
Packages 16 mm x 16 mm, 361-Ball 0.80 mm pitch, PBGA (ZWT)
Product Preview (PP), 375 MHz versions - PD
Product Status(1) Advance Information (AI), 456 MHz versions - PD
or Production Data (PD)
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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3.2 Device Compatibility
The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc.
3.3 ARM Subsystem
The ARM Subsystem includes the following features:
• ARM926EJ-S RISC processor
• ARMv5TEJ (32/16-bit) instruction set
• Little endian
• System Control Co-Processor 15 (CP15)
• MMU
• 16KB Instruction cache
• 16KB Data cache
• Write Buffer
• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
• ARM Interrupt controller
3.3.1 ARM926EJ-S RISC CPU
The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of
ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications
where full memory management, high performance, low die size, and low power are all important. The
ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to
trade off between high performance and high code density. Specifically, the ARM926EJ-S processor
supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes,
providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code
overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both
hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a
complete high performance subsystem, including:
• ARM926EJ -S integer core
• CP15 system control coprocessor
• Memory Management Unit (MMU)
• Separate instruction and data caches
• Write buffer
• Separate instruction and data (internal RAM) interfaces
• Separate instruction and data AHB bus interfaces
• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available
at http://www.arm.com
3.3.2 CP15
The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and
data caches, Memory Management Unit (MMU), and other ARM subsystem functions. The CP15 registers
are programmed using the MRC and MCR ARM instructions, when the ARM in a privileged mode such as
supervisor or system mode.
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3.3.3 MMU
A single set of two level page tables stored in main memory is used to control the address translation,
permission checks and memory region attributes for both data and instruction accesses. The MMU uses a
single unified Translation Lookaside Buffer (TLB) to cache the information held in the page tables. The
MMU features are:
• Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.
• Mapping sizes are:
– 1MB (sections)
– 64KB (large pages)
– 4KB (small pages)
– 1KB (tiny pages)
• Access permissions for large pages and small pages can be specified separately for each quarter of
the page (subpage permissions)
• Hardware page table walks
• Invalidate entire TLB, using CP15 register 8
• Invalidate TLB entry, selected by MVA, using CP15 register 8
• Lockdown of TLB entries, using CP15 register 10
3.3.4 Caches and Write Buffer
The size of the Instruction cache is 16KB, Data cache is 16KB. Additionally, the caches have the following
features:
• Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA)
• Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with
two dirty bits in the Dcache
• Dcache supports write-through and write-back (or copy back) cache operation, selected by memory
region using the C and B bits in the MMU translation tables
• Critical-word first cache refilling
• Cache lockdown registers enable control over which cache ways are used for allocation on a line fill,
providing a mechanism for both lockdown, and controlling cache corruption
• Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG
RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the
TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the
possibility of TLB misses related to the write-back address.
• Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of
the Dcache or Icache, and regions of virtual memory.
The write buffer is used for all writes to a noncachable bufferable region, write-through region and write
misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for
cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a
four-address buffer. The Dcache write-back has eight data word entries and a single address entry.
3.3.5 Advanced High-Performance Bus (AHB)
The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the Config bus and
the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the
Config Bus and the external memories bus.
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3.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an
Embedded Trace Macrocell (ETM). The ARM926ES-J Subsystem in the device also includes the
Embedded Trace Buffer (ETB). The ETM consists of two parts:
• Trace Port provides real-time trace capability for the ARM9.
• Triggering facilities provide trigger resources, which include address and data comparators, counter,
and sequencers.
The device trace port is not pinned out and is instead only connected to the Embedded Trace Buffer. The
ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace
data.
3.3.7 ARM Memory Mapping
By default the ARM has access to most on and off chip memory areas, including EMIFA, DDR2, and the
additional 128K byte on chip SRAM. Likewise almost all of the on chip peripherals are accessible to the
ARM by default.
To improve security and/or robustness, the device has extensive memory and peripheral protection units
which can be configured to limit access rights to the various on/off chip resources to specific hosts;
including the ARM as well as other master peripherals. This allows the system tasks to be partitioned
between the ARM and DSP as best suites the particular application; while enhancing the overall
robustness of the solution.
See Table 3-2 for a detailed top level device memory map that includes the ARM memory space.
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3.4 Memory Map Summary
Note: Read/Write accesses to illegal or reserved addresses in the memory map may cause undefined
behavior.
Table 3-2. Device Top Level Memory Map
Start Address End Address Size ARM Mem Map EDMA Mem Map PRUSS Mem Master LCDC Mem
Map Peripheral Mem Map
Map
0x0000 0000 0x0000 0FFF 4K PRUSS Local
Address Space
0x0000 1000 0x01BB FFFF
0x01BC 0000 0x01BC 0FFF 4K ARM ETB
memory
0x01BC 1000 0x01BC 17FF 2K ARM ETB reg
0x01BC 1800 0x01BC 18FF 256 ARM Ice Crusher
0x01BC 1900 0x01BF FFFF
0x01C0 0000 0x01C0 7FFF 32K EDMA3 CC
0x01C0 8000 0x01C0 83FF 1K EDMA3 TC0
0x01C0 8400 0x01C0 87FF 1K EDMA3 TC1
0x01C0 8800 0x01C0 FFFF
0x01C1 0000 0x01C1 0FFF 4K PSC 0
0x01C1 1000 0x01C1 1FFF 4K PLL Controller 0
0x01C1 2000 0x01C1 3FFF
0x01C1 4000 0x01C1 4FFF 4K SYSCFG0
0x01C1 5000 0x01C1 FFFF
0x01C2 0000 0x01C2 0FFF 4K Timer0
0x01C2 1000 0x01C2 1FFF 4K Timer1
0x01C2 2000 0x01C2 2FFF 4K I2C 0
0x01C2 3000 0x01C2 3FFF 4K RTC
0x01C2 4000 0x01C3 FFFF
0x01C4 0000 0x01C4 0FFF 4K MMC/SD 0
0x01C4 1000 0x01C4 1FFF 4K SPI 0
0x01C4 2000 0x01C4 2FFF 4K UART 0
0x01C4 3000 0x01CF FFFF
0x01D0 0000 0x01D0 0FFF 4K McASP 0 Control
0x01D0 1000 0x01D0 1FFF 4K McASP 0 AFIFO Ctrl
0x01D0 2000 0x01D0 2FFF 4K McASP 0 Data
0x01D0 3000 0x01D0 BFFF
0x01D0 C000 0x01D0 CFFF 4K UART 1
0x01D0 D000 0x01D0 DFFF 4K UART 2
0x01D0 E000 0x01D0 FFFF
0x01D1 0000 0x01D1 07FF 2K McBSP0
0x01D1 0800 0x01D1 0FFF 2K McBSP0 FIFO Ctrl
0x01D1 1000 0x01D1 17FF 2K McBSP1
0x01D1 1800 0x01D1 1FFF 2K McBSP1 FIFO Ctrl
0x01D1 2000 0x01DF FFFF
0x01E0 0000 0x01E0 FFFF 64K USB0
0x01E1 0000 0x01E1 0FFF 4K UHPI
0x01E1 1000 0x01E1 2FFF
0x01E1 3000 0x01E1 3FFF 4K LCD Controller
0x01E1 4000 0x01E1 4FFF 4K Memory Protection Unit 1 (MPU 1)
Copyright © 2010–2014, Texas Instruments Incorporated Device Overview 11
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Table 3-2. Device Top Level Memory Map (continued)
Start Address End Address Size ARM Mem Map EDMA Mem Map PRUSS Mem Master LCDC Mem
Map Peripheral Mem Map
Map
0x01E1 5000 0x01E1 5FFF 4K Memory Protection Unit 2 (MPU 2)
0x01E1 6000 0x01E1 6FFF 4K UPP
0x01E1 7000 0x01E1 7FFF 4K VPIF
0x01E1 8000 0x01E1 9FFF 8K SATA
0x01E1 A000 0x01E1 AFFF 4K PLL Controller 1
0x01E1 B000 0x01E1 BFFF 4K MMCSD1
0x01E1 C000 0x01E1 FFFF
0x01E2 0000 0x01E2 1FFF 8K EMAC Control Module RAM
0x01E2 2000 0x01E2 2FFF 4K EMAC Control Module Registers
0x01E2 3000 0x01E2 3FFF 4K EMAC Control Registers
0x01E2 4000 0x01E2 4FFF 4K EMAC MDIO port
0x01E2 5000 0x01E2 5FFF 4K USB1
0x01E2 6000 0x01E2 6FFF 4K GPIO
0x01E2 7000 0x01E2 7FFF 4K PSC 1
0x01E2 8000 0x01E2 8FFF 4K I2C 1
0x01E2 9000 0x01E2 BFFF
0x01E2 C000 0x01E2 CFFF 4K SYSCFG1
0x01E2 D000 0x01E2 FFFF
0x01E3 0000 0x01E3 7FFF 32K EDMA3 CC1
0x01E3 8000 0x01E3 83FF 1K EDMA3 TC2
0x01E3 8400 0x01EF FFFF
0x01F0 0000 0x01F0 0FFF 4K eHRPWM 0
0x01F0 1000 0x01F0 1FFF 4K HRPWM 0
0x01F0 2000 0x01F0 2FFF 4K eHRPWM 1
0x01F0 3000 0x01F0 3FFF 4K HRPWM 1
0x01F0 4000 0x01F0 5FFF
0x01F0 6000 0x01F0 6FFF 4K ECAP 0
0x01F0 7000 0x01F0 7FFF 4K ECAP 1
0x01F0 8000 0x01F0 8FFF 4K ECAP 2
0x01F0 9000 0x01F0 BFFF
0x01F0 C000 0x01F0 CFFF 4K Timer2
0x01F0 D000 0x01F0 DFFF 4K Timer3
0x01F0 E000 0x01F0 EFFF 4K SPI1
0x01F0 F000 0x01F0 FFFF
0x01F1 0000 0x01F1 0FFF 4K McBSP0 FIFO Data
0x01F1 1000 0x01F1 1FFF 4K McBSP1 FIFO Data
0x01F1 2000 0x3FFF FFFF
0x4000 0000 0x5FFF FFFF 512M EMIFA SDRAM data (CS0)
0x6000 0000 0x61FF FFFF 32M EMIFA async data (CS2)
0x6200 0000 0x63FF FFFF 32M EMIFA async data (CS3)
0x6400 0000 0x65FF FFFF 32M EMIFA async data (CS4)
0x6600 0000 0x67FF FFFF 32M EMIFA async data (CS5)
0x6800 0000 0x6800 7FFF 32K EMIFA Control Regs
0x6800 8000 0x7FFF FFFF
0x8000 0000 0x8001 FFFF 128K On-Chip RAM
0x8002 0000 0xAFFF FFFF
12 Device Overview Copyright © 2010–2014, Texas Instruments Incorporated
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Table 3-2. Device Top Level Memory Map (continued)
Start Address End Address Size ARM Mem Map EDMA Mem Map PRUSS Mem Master LCDC Mem
Map Peripheral Mem Map
Map
0xB000 0000 0xB000 7FFF 32K DDR2/mDDR Control Regs
0xB000 8000 0xBFFF FFFF
0xC000 0000 0xCFFF FFFF 256M DDR2/mDDR Data
0xD000 0000 0xE000 0000
0xFFFD 0000 0xFFFD FFFF 64K ARM local ROM
0xFFFE 0000 0xFFFE DFFF
0xFFFE E000 0xFFFE FFFF 8K ARM Interrupt
Controller
0xFFFF 0000 0xFFFF 1FFF 8K ARM local RAM ARM Local RAM
(PRU0 only)
0xFFFF 2000 0xFFFF FFFF
Copyright © 2010–2014, Texas Instruments Incorporated Device Overview 13
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W
V
U
T
R
P
N
M
L
K
10987654321
10987654321
DVDD3318_C
VP_CLKOUT3/
PRU1_R30[0]/
GP6[1]/
PRU1_R31[1]
SATA_VSS
SATA_RXP
VP_CLKOUT2/
MMCSD1_DAT[2]/
PRU1_R30[2]/
GP6[3]/
PRU1_R31[3]
SATA_RXN
SATA_VDD
SATA_REFCLKN SATA_REGSATA_REFCLKP SATA_VDD
SATA_VDD SATA_VDDRSATA_VDD
DVDD3318_C
DDR_A[11]
VP_DOUT[15]/
LCD_D[15]/
UPP_XD[7]/
GP7[7]/
BOOT[7]
DVDD3318_C
DVDD18
DDR_DVDD18 DDR_DVDD18
DDR_D[15]
DDR_RAS
DDR_CLKPDDR_CLKN
DDR_A[2]DDR_A[10]
VSS
LCD_AC_ENB_CS/
GP6[0]/
PRU1_R31[28]
DDR_A[13]
DDR_CAS
DDR_A[5] DDR_CKE DDR_BA[0]
VSS
CVDD
RVDD
DDR_A[9] DDR_A[1] DDR_WE DDR_D[10]
DDR_A[7] DDR_A[0] DDR_D[12]
DDR_A[12] DDR_A[3] DDR_CS
DDR_A[6]
DDR_DQM[1]
SATA_VSS CVDD
SATA_VSS
DDR_DVDD18
VP_DOUT[12]/
LCD_D[12]/
UPP_XD[4]/
GP7[4]/
BOOT[4]
DDR_VREF
DDR_BA[1]
DDR_A[8] DDR_A[4] DDR_BA[2]
SATA_VSS
W
V
U
T
R
P
N
M
L
K
DDR_D[13]
VSS VSS VSS
VSS DVDD18 VSS VSS VSS VSS
NC_M3 VSS VSS VSS VSS CVDD CVDD VSS
DDR_DVDD18DDR_DVDD18DDR_DVDD18DDR_DVDD18
DVDD3318_C
VP_DOUT[13]/
LCD_D[13]/
UPP_XD[5]/
GP7[5]/
BOOT[5]
VP_DOUT[14]/
LCD_D[14]/
UPP_XD[6]/
GP7[6]/
BOOT[6]
DDR_DVDD18 DDR_DVDD18 DDR_DVDD18
VP_DOUT[9]/
LCD_D[9]/
UPP_XD[1]/
GP7[1]/
BOOT[1]
VP_DOUT[10]/
LCD_D[10]/
UPP_XD[2]/
GP7[2]/
BOOT[2]
VP_DOUT[11]/
LCD_D[11]/
UPP_XD[3]/
GP7[3]/
BOOT[3]
VP_DOUT[6]/
LCD_D[6]/
UPP_XD[14]/
GP7[14]/
PRU1_R31[14]
VP_DOUT[7]/
LCD_D[7]/
UPP_XD[15]/
GP7[15]/
PRU1_R31[15]
VP_DOUT[8]/
LCD_D[8]/
UPP_XD[0]/
GP7[0]/
BOOT[0]
VP_DOUT[3]/
LCD_D[3]/
UPP_XD[11]/
GP7[11]/
PRU1_R31[11]
VP_DOUT[4]/
LCD_D[4]/
UPP_XD[12]/
GP7[12]/
PRU1_R31[12]
VP_DOUT[5]/
LCD_D[5]/
UPP_XD[13]/
GP7[13]/
PRU1_R31[13]
VP_DOUT[0]/
LCD_D[0]/
UPP_XD[8]/
GP7[8]/
PRU1_R31[8]
VP_DOUT[1]/
LCD_D[1]/
UPP_XD[9]/
GP7[9]/
PRU1_R31[9]
VP_DOUT[2]/
LCD_D[2]/
UPP_XD[10]/
GP7[10]/
PRU1_R31[10]
A B
CD
AM1808
SPRS653E –FEBRUARY 2010–REVISED MARCH 2014 www.ti.com
3.5 Pin Assignments
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in
the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings.
3.5.1 Pin Map (Bottom View)
The following graphics show the bottom view of the ZCE and ZWT packages pin assignments in four
quadrants (A, B, C, and D). The pin assignments for both packages are identical.
Figure 3-1. Pin Map (Quad A)
14 Device Overview Copyright © 2010–2014, Texas Instruments Incorporated
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W
V
U
T
R
P
N
M
L
K
191817161514131211
191817161514131211
USB1_VDDA33
DVDD3318_C
CVDD
USB_CVDD
DVDD3318_C
DDR_DQGATE0 DVDD18 DDR_DQGATE1
DDR_D[9] DDR_D[8]DDR_D[11]
DVDD18
RTC_CVDD
RESET
USB0_DM USB0_DP
VP_DIN[11]/
UHPI_HD[3]/
UPP_D[3]/
PRU0_R30[11]/
PRU0_R31[11]
USB0_VDDA33 USB0_VBUS
USB1_DM
VP_DIN[0]/
UHPI_HD[8]/
UPP_D[8]/
RMII_CRS_DV/
PRU1_R31[29]
VP_DIN[1]/
UHPI_HD[9]/
UPP_D[9]/
RMII_MHZ_50_CLK /
PRU0_R31[23]
VP_DIN[2]/
UHPI_HD[10]/
UPP_D[10]/
RMII_RXER /
PRU0_R31[24]
VP_DIN[4]/
UHPI_HD[12]/
UPP_D[12]/
RMII_RXD[1]/
PRU0_R31[26]
PRU0_R30[28]/
UHPI_HCNTL1/
UPP_CHA_START/
GP6[10]
USB1_DP
PLL0_VDDA
PRU0_R30[30] /
/
PRU1_R30[11]/
GP6[12]
UHPI_HINT
USB0_VDDA18
VP_DIN[5]/
UHPI_HD[13]/
UPP_D[13]/
RMII_TXEN/
PRU0_R31[27]
DDR_D[1]
VP_DIN[7]/
UHPI_HD[15]/
UPP_D[15]/
RMII_TXD[1]/
PRU0_R31[29]
OSCVSS
DDR_D[2]
VP_DIN[6]/
UHPI_HD[14]/
UPP_D[14]/
RMII_TXD[0]/
PRU0_R31[28]
VP_DIN[3]/
UHPI_HD[11]/
UPP_D[11]/
RMII_RXD[0]/
PRU0_R31[25]
VP_DIN[14]_
HSYNC/
UHPI_HD[6]/
UPP_D[6]/
PRU0_R30[14]/
PRU0_R31[14]
EMU1
VP_DIN[8]/
UHPI_HD[0]/
UPP_D[0]/
GP6[5]/
PRU1_R31[0]
USB0_VDDA12
TDI
NC_N16
PRU0_R30[26]/
UHPI_HR /
UPP_CHA_WAIT/
GP6[8]/
PRU1_R31[17]
WVP_DIN[12]/
UHPI_HD[4]/
UPP_D[4]/
PRU0_R30[12]/
PRU0_R31[12]
RESETOUT
UHPI_HAS
/
/
PRU1_R30[14]/
GP6[15]
RSV2
RTCK/
GP8[0] OSCOUT
DDR_D[0]
PRU0_R30[27]/
UHPI_HHWIL/
UPP_CHA_ENABLE/
GP6[9]
VP_DIN[13]_
FIELD/
UHPI_HD[5]/
UPP_D[5]/
PRU0_R30[13]/
PRU0_R31[13]
TRST OSCIN
VP_CLKIN1/
/
PRU1_R30[9]/
GP6[6]/
PRU1_R31[16]
UHPI_HDS1 VP_DIN[15]_
VSYNC/
UHPI_HD[7]/
UPP_D[7]/
PRU0_R30[15]/
PRU0_R31[15]
VP_CLKIN0/
/
PRU1_R30[10]/
GP6[7]/
UPP_2xTXCLK
UHPI_HCS
VP_DIN[10]/
UHPI_HD[2]/
UPP_D[2]/
PRU0_R30[10]/
PRU0_R31[10]
VSS DVDD3318_B
PLL0_VSSA
TMS
PRU0_R30[31]/
/
PRU1_R30[12]
GP6[13]
UHPI_HRDY
NC_M14 PLL1_VSSA
PLL1_VDDA
USB1_VDDA18 USB0_ID
VP_DIN[9]/
UHPI_HD[1]/
UPP_D[1]/
PRU0_R30[9]/
PRU0_R31[9]
CLKOUT/
/
PRU1_R30[13]/
GP6[14]
UHPI_HDS2
USB0_DRVVBUS
DDR_DQS[0]
PRU0_R30[29]/
UHPI_HCNTL0/
UPP_CHA_CLOCK/
GP6[11]
W
V
U
T
R
P
N
M
L
K
DDR_DQM[0]
DDR_D[3]
DDR_D[4]
DDR_D[6]
DDR_ZP
DDR_D[5]
DDR_D[7]
DDR_D[14]
DDR_DQS[1]
VSS
VSS
VSS
VSS
VSS
CVDD DVDD3318_C
DVDD3318_C
DVDD3318_C
AA B
CD
AM1808
www.ti.com SPRS653E –FEBRUARY 2010–REVISED MARCH 2014
Figure 3-2. Pin Map (Quad B)
Copyright © 2010–2014, Texas Instruments Incorporated Device Overview 15
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H
G
F
E
D
C
B
A
191817161514131211
191817161514131211
CVDD
EMA_A[8]/
PRU1_R30[16]/
GP5[8]
EMA_A[14]/
MMCSD0_DAT[7]/
PRU1_R30[22]/
GP5[14]/
PRU1_R31[22]
EMA_A[15]/
MMCSD0_DAT[6]/
PRU1_R30[23]/
GP5[15]/
PRU1_R31[23]
EMA_A[10]/
PRU1_R30[18]/
GP5[10]/
PRU1_R31[18]
EMA_A[9]/
PRU1_R30[17]/
GP5[9]
EMA_A[13]/
PRU0_R30[21]/
PRU1_R30[21]
GP5[13]/
PRU1_R31[21]
EMA_A[12]/
PRU1_R30[20]/
GP5[12]/
PRU1_R31[20]
EMA_A[16]/
MMCSD0_DAT[5]/
PRU1_R30[24]/
GP4[0]
EMA_A[18]/
MMCSD0_DAT[3]/
PRU1_R30[26]/
GP4[2]
DVDD3318_B
DVDD18
EMA_A[6]/
GP5[6]
EMA_A[5]/
GP5[5]
EMA_A[2]/
GP5[2]
EMA_A[7]/
PRU1_R30[15]/
GP5[7]
EMA_A[4]/
GP5[4]
SPI0_SIMO/
EPWMSYNCO/
GP8[5]/
MII_CRS
SPI0_SCS[5]/
UART0_RXD/
GP8[4]/
MII_RXD[3]
SPI1_SCS[1]/
EPWM1A/
PRU0_R30[8]/
GP2[15]/
TM64P2_IN12
SPI0_SCS[4]/
UART0_TXD/
GP8[3]/
MII_RXD[2]
SPI0_CLK/
EPWM0A/
GP1[8]/
MII_RXCLK
SPI1_SCS[3]/
UART1_RXD/
SATA_LED/
GP1[1]
SPI1_SCS[0]/
EPWM1B/
PRU0_R30[7]/
GP2[14]/
TM64P3_IN12
EMA_OE/
GP3[10]
SPI1_SCS[4]/
UART2_TXD/
I2C1_SDA/
GP1[2]
EMA_A[3]/
GP5[3]
DVDD18
RTC_VSS
EMA_WAIT[0]/
PRU0_R30[0]/
GP3[8]/
PRU0_R31[0]
EMA_RAS/
PRU0_R30[3]/
GP2[5]/
PRU0_R31[3]
SPI0_SCS[3]
UART0_CTS
/
/
GP8[2]/
MII_RXD[1]/
SATA_MP_SWITCH
SPI0_SCS[0]/
TM64P1_OUT12/
GP1[6]/
MDIO/
TM64P1_IN12
SPI0_SOMI/
EPWMSYNCI/
GP8[6]/
MII_RXER
SPI0_SCS[2]
UART0_RTS
/
/
GP8[1]/
MII_RXD[0]/
SATA_CP_DET
SPI1_SCS[7]/
I2C0_SCL/
TM64P2_OUT12/
GP1[5]
SPI1_SIMO/
GP2[10]
SPI1_CLK/
GP2[13]
EMA_CS[3]/
GP3[14] VSS
VSS SPI1_ENA/
GP2[12] RTC_XO
EMA_CS[2]/
GP3[15]
EMA_WAIT[1]/
PRU0_R30[1]/
GP2[1]/
PRU0_R31[1]
EMA_A[20]/
MMCSD0_DAT[1]/
PRU1_R30[28]/
GP4[4]
EMA_BA[1]/
GP2[9]
SPI0_ENA/
EPWM0B/
PRU0_R30[6]/
MII_RXDV
EMA_CS[5]/
GP3[12]
SPI1_SCS[5]/
UART2_RXD/
I2C1_SCL/
GP1[3]
EMA_A[0]/
GP5[0]
EMA_BA[0]/
GP2[8]
EMA_A[1]/
GP5[1]
DVDD3318_B
SPI0_SCS[1]/
TM64P0_OUT12/
GP1[7]/
MDCLK/
TM64P0_IN12
DVDD3318_A
SPI1_SCS[6]/
I2C0_SDA/
TM64P3_OUT12/
GP1[4]
EMA_CS[0]/
GP2[0]
CVDD SPI1_SOMI/
GP2[11] H
G
F
E
D
C
B
A
JTDO
TCK EMU0 RTC_XI RSVDN J
SPI1_SCS[2]/
UART1_TXD/
SATA_CP_POD/
GP1[0]
EMA_A[11]/
PRU1_R30[19]/
GP5[11]/
PRU1_R31[19]
EMA_A[17]/
MMCSD0_DAT[4]/
PRU1_R30[25]
GP4[1]
DVDD3318_B DVDD3318_B
DVDD18 CVDD DVDD3318_A DVDD3318_A
RVDD
CVDD CVDD
VSS CVDD DVDD18 DVDD3318_B
C
A B
D
AM1808
SPRS653E –FEBRUARY 2010–REVISED MARCH 2014 www.ti.com
Figure 3-3. Pin Map (Quad C)
16 Device Overview Copyright © 2010–2014, Texas Instruments Incorporated
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J
H
G
F
E
D
C
B
A
10987654321
10987654321
EMA_D[15]/
GP3[7]
AXR15/
EPWM0TZ[0]/
ECAP2_APWM2/
GP0[7]
ACLKR/
PRU0_R30[20]/
GP0[15]/
PRU0_R31[22]
ACLKX/
PRU0_R30[19]/
GP0[14]/
PRU0_R31[21]
AHCLKX/
USB_REFCLKIN/
/
GP0[10]/
PRU0_R31[17]
UART1_CTS
AFSX/
GP0[12]/
PRU0_R31[19]
AFSR/
GP0[13]/
PRU0_R31[20]
AXR9/
DX1/
GP0[1]
AXR4/
FSR0/
GP1[12]/
MII_COL
AXR5/
CLKX0/
GP1[13]/
MII_TXCLK
AXR7/
EPWM1TZ[0]/
PRU0_R30[17]
GP1[15]/
PRU0_R31[7]
AXR10/
DR1/
GP0[2]
AXR1/
DX0/
GP1[9]/
MII_TXD[1]
AXR3/
FSX0/
GP1[11]/
MII_TXD[3]
AXR2/
DR0/
GP1[10]/
MII_TXD[2]
MMCSD1_DAT[6]/
LCD_MCLK/
PRU1_R30[6]/
GP8[10]/
PRU1_R31[7]
RTC_ALARM/
/
GP0[8]/
UART2_CTS
DEEPSLEEP
AXR0/
ECAP0_APWM0/
GP8[7]/
MII_TXD[0]/
CLKS0
PRU0_R30[24]/
MMCSD1_CLK/
UPP_CHB_START/
GP8[14]/
PRU1_R31[26]
MMCSD1_DAT[4]/
LCD_VSYNC/
PRU1_R30[4]/
GP8[8]/
PRU1_R31[5]
SATA_VSS
PRU0_R30[22]/
PRU1_R30[8]/
UPP_CHB_WAIT/
GP8[12]/
PRU1_R31[24]
AXR8/
CLKS1/
ECAP1_APWM1/
GP0[0]/
PRU0_R31[8]
AXR12/
FSR1/
GP0[4]
EMA_D[4]/
GP4[12]
AXR14/
CLKR1/
GP0[6]
EMA_WEN_DQM[1]/
GP2[2]
EMA_D[0]/
GP4[8]
EMA_A[19]/
MMCSD0_DAT[2]/
PRU1_R30[27]/
GP4[3]
EMA_D[9]/
GP3[1]
EMA_A_R /
GP3[9]
W
MMCSD0_CLK/
PRU1_R30[31]/
GP4[7]
EMA_D[8]/
GP3[0]
EMA_D[13]/
GP3[5]
VP_CLKIN2/
MMCSD1_DAT[3]/
PRU1_R30[3]/
GP6[4]/
PRU1_R31[4]
VP_CLKIN3/
MMCSD1_DAT[1]/
PRU1_R30[1]/
GP6[2]/
PRU1_R31[2]
AMUTE/
GP0[9]/
PRU0_R31[16]
PRU0_R30[16]/
UART2_RTS/
DVDD3318_A
DVDD3318_A
EMA_WE/
GP3[11]
EMA_D[10]/
GP3[2]
EMA_D[3]/
GP4[11]
EMA_SDCKE/
PRU0_R30[4]/
GP2[6]/
PRU0_R31[4]
EMA_D[14]/
GP3[6]
EMA_D[7]/
GP4[15]
EMA_D[1]/
GP4[9]
EMA_A[22]/
MMCSD0_CMD/
PRU1_R30[30]/
GP4[6]
EMA_D[2]/
GP4[10]
EMA_A[21]/
MMCSD0_DAT[0]/
PRU1_R30[29]/
GP4[5]
PRU0_R30[23]/
MMCSD1_CMD/
UPP_CHB_ENABLE/
GP8[13]/
PRU1_R31[25]
AHCLKR/
/
GP0[11]/
PRU0_R31[18]
PRU0_R30[18]/
UART1_RTS EMA_D[12]/
GP3[4]
EMA_WEN_DQM[0]/
GP2[3]
EMA_CLK/
PRU0_R30[5]/
GP2[7]/
PRU0_R31[5]
AXR6/
CLKR0/
GP1[14]/
MII_TXEN/
PRU0_R31[6]
AXR11/
FSX1/
GP0[3]
EMA_D[6]/
GP4[14]
EMA_D[11]/
GP3[3]
RVDD EMA_D[5]/
GP4[13]
MMCSD1_DAT[7]/
LCD_PCLK/
PRU1_R30[7]/
GP8[11]
MMCSD1_DAT[5]/
LCD_HSYNC/
PRU1_R30[5]/
GP8[9]/
PRU1_R31[6]
PRU0_R30[25]/
MMCSD1_DAT[0]/
UPP_CHB_CLOCK/
GP8[15]/
PRU1_R31[27]
AXR13/
CLKX1/
GP0[5]
J
H
G
F
E
D
C
B
A
EMA_CS[4]/
GP3[13]
EMA_CAS/
PRU0_R30[2]/
GP2[4]/
PRU0_R31[2]
DVDD3318_B DVDD3318_B DVDD3318_B DVDD3318_B
DVDD18 CVDD CVDD DVDD3318_B DVDD18
SATA_VSS DVDD3318_A
VSS VSS
CVDD CVDD VSS VSS CVDD
SATA_TXP SATA_TXN DVDD3318_C CVDD VSS VSS
A B
CD
AM1808
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Figure 3-4. Pin Map (Quad D)
3.6 Pin Multiplexing Control
Device level pin multiplexing is controlled by registers PINMUX0 - PINMUX19 in the SYSCFG module.
For the device family, pin multiplexing can be controlled on a pin-by-pin basis. Each pin that is multiplexed
with several different functions has a corresponding 4-bit field in one of the PINMUX registers.
Pin multiplexing selects which of several peripheral pin functions controls the pin's IO buffer output data
and output enable values only. The default pin multiplexing control for almost every pin is to select 'none'
of the peripheral functions in which case the pin's IO buffer is held tri-stated.
Note that the input from each pin is always routed to all of the peripherals that share the pin; the PINMUX
registers have no effect on input from a pin.
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3.7 Terminal Functions
Table 3-3 to Table 3-29 identify the external signal names, the associated pin/ball numbers along with the
mechanical package designator, the pin type (I, O, IO, OZ, or PWR), whether the pin/ball has any internal
pullup/pulldown resistors, whether the pin/ball is configurable as an IO in GPIO mode, and a functional pin
description.
3.7.1 Device Reset and JTAG
Table 3-3. Reset and JTAG Terminal Functions
SIGNAL POWER
TYPE(1) PULL(2) DESCRIPTION
GROUP(3)
NAME NO.
RESET
RESET K14 I IPU B Device reset input
RESETOUT / UHPI_HAS / PRU1_R30[14] / T17 O(4) CP[21] C Reset output
GP6[15]
JTAG
TMS L16 I IPU B JTAG test mode select
TDI M16 I IPU B JTAG test data input
TDO J18 O IPU B JTAG test data output
TCK J15 I IPU B JTAG test clock
TRST L17 I IPD B JTAG test reset
EMU0 J16 I/O IPU B Emulation pin
EMU1 K16 I/O IPU B Emulation pin
RTCK/ GP8[0] (5) K17 I/O IPD B JTAG Test Clock Return Clock Output
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor. CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. For more detailed information on pullup/pulldown resistors and situations
where external pullup/pulldown resistors are required, see the Device Configuration section. For electrical specifications on pullup and
internal pulldown circuits, see the Device Operating Conditions section.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
(4) Open drain mode for RESETOUT function.
(5) GP8[0] is initially configured as a reserved function after reset and will not be in a predictable state. This signal will only be stable after
the GPIO configuration for this pin has been completed. Users should carefully consider the system implications of this pin being in an
unknown state after reset.
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3.7.2 High-Frequency Oscillator and PLL
Table 3-4. High-Frequency Oscillator and PLL Terminal Functions
SIGNAL POWER
TYPE(1) PULL(2) DESCRIPTION
GROUP(3)
NAME NO.
CLKOUT / UHPI_HDS2 / T18 O CP[22] C PLL Observation Clock
PRU1_R30[13] / GP6[14]
1.2-V OSCILLATOR
OSCIN L19 I — — Oscillator input
OSCOUT K19 O — — Oscillator output
OSCVSS L18 GND — — Oscillator ground
1.2-V PLL0
PLL0_VDDA L15 PWR — — PLL analog VDD (1.2-V filtered supply)
PLL0_VSSA M17 GND — — PLL analog VSS (for filter)
1.2-V PLL1
PLL1_VDDA N15 PWR — — PLL analog VDD (1.2-V filtered supply)
PLL1_VSSA M15 GND — — PLL analog VSS (for filter)
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where nis the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. For more detailed information on pullup/pulldown resistors and situations
where external pullup/pulldown resistors are required, see the Device Configuration section. For electrical specifications on pullup and
internal pulldown circuits, see the Device Operating Conditions section.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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3.7.3 Real-Time Clock and 32-kHz Oscillator
Table 3-5. Real-Time Clock (RTC) and 1.2-V, 32-kHz Oscillator Terminal Functions
SIGNAL POWER
TYPE(1) PULL(2) DESCRIPTION
GROUP(3)
NAME NO.
RTC_XI J19 I — — RTC 32-kHz oscillator input
RTC_XO H19 O — — RTC 32-kHz oscillator output
RTC_ALARM / UART2_CTS / GP0[8] / DEEPSLEEP F4 O CP[0] A RTC Alarm
RTC module core power
RTC_CVDD L14 PWR — — (isolated from chip CVDD)
RTC_Vss H18 GND — — Oscillator ground
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where nis the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,
an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see the Device Configuration section. For electrical specifications on pullup and internal pulldown
circuits, see the Device Operating Conditions section.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
3.7.4 DEEPSLEEP Power Control
Table 3-6. DEEPSLEEP Power Control Terminal Functions
SIGNAL POWER
TYPE(1) PULL(2) DESCRIPTION
GROUP(3)
NAME NO.
RTC_ALARM / UART2_CTS / GP0[8] / DEEPSLEEP F4 I CP[0] A DEEPSLEEP power control output
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where nis the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,
an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see the Device Configuration section. For electrical specifications on pullup and internal pulldown
circuits, see the Device Operating Conditions section.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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