Texas Instruments OMAP36 Series Product manual

OMAP™
Public Version
OMAP36xx Multimedia Device
Silicon Revision 1.x
Texas Instruments OMAP™ Family of Products
Version N
Technical Reference Manual
Literature Number: SWPU177N
December 2009–Revised November 2010

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Public Version
Contents
Preface .................................................................................................................................... 175
1 Introduction .................................................................................................................... 187
1.1 Overview .................................................................................................................. 188
1.2 Environment .............................................................................................................. 189
1.3 Description ................................................................................................................ 191
1.3.1 MPU Subsystem ................................................................................................ 191
1.3.2 IVA2.2 Subsystem .............................................................................................. 192
1.3.3 On-Chip Memory ................................................................................................ 193
1.3.4 External Memory Interfaces ................................................................................... 193
1.3.5 DMA Controllers ................................................................................................. 193
1.3.6 Multimedia ....................................................................................................... 194
1.3.7 Comprehensive Power Management ......................................................................... 195
1.3.8 Peripherals ....................................................................................................... 195
1.4 POP Concept ............................................................................................................. 197
1.5 OMAP36xx Family ....................................................................................................... 198
1.6 Device Identification ..................................................................................................... 200
2 Memory Mapping ............................................................................................................. 203
2.1 Introduction ............................................................................................................... 204
2.2 Global Memory Space Mapping ....................................................................................... 206
2.3 L3 and L4 Memory Space Mapping ................................................................................... 209
2.3.1 L3 Memory Space Mapping ................................................................................... 209
2.3.2 L4 Memory Space Mapping ................................................................................... 210
2.3.2.1 L4-Core Memory Space Mapping ...................................................................... 210
2.3.2.2 L4-Wakeup Memory Space Mapping .................................................................. 213
2.3.2.3 L4-Peripheral Memory Space Mapping ................................................................ 214
2.3.2.4 L4-Emulation Memory Space Mapping ................................................................ 215
2.3.3 Register Access Restrictions .................................................................................. 216
2.4 IVA2.2 Subsystem Memory Space Mapping ......................................................................... 218
2.4.1 IVA2.2 Subsystem Internal Memory and Cache Allocation ............................................... 218
2.4.1.1 IVA2.2 Subsystem Memory Hierarchy ................................................................. 218
2.4.1.2 IVA2.2 Cache Allocation ................................................................................. 219
2.4.2 DSP Access to L2 Memories .................................................................................. 220
2.4.2.1 DSP Access to L2 ROM ................................................................................. 220
2.4.2.2 DSP Access to L2 RAM ................................................................................. 220
2.4.3 DSP and EDMA Access to Memories and Peripherals .................................................... 220
2.4.4 L3 Interconnect View of the IVA2.2 Subsystem Memory Space ......................................... 221
2.4.5 DSP View of the IVA2.2 Subsystem Memory Space ....................................................... 221
2.4.6 EDMA View of the IVA2.2 Subsystem Memory Space .................................................... 223
3 Power, Reset, and Clock Management ................................................................................ 225
3.1 Introduction to Power Managements .................................................................................. 226
3.1.1 Goal of Power Management ................................................................................... 226
3.1.2 Power-Management Techniques ............................................................................. 226
3.1.2.1 Dynamic Voltage and Frequency Scaling ............................................................. 226
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3.1.2.2 SmartReflex Adaptive Voltage Scaling (AVS) ........................................................ 227
3.1.2.3 Dynamic Power Switching ............................................................................... 228
3.1.2.4 Standby Leakage Management ......................................................................... 228
3.1.2.5 DPS Versus SLM ......................................................................................... 229
3.1.2.6 Adaptive Body Bias (ABB) ............................................................................... 229
3.1.2.7 Combining Power-Management Techniques ......................................................... 229
3.1.3 Architectural Blocks for Power Management ................................................................ 230
3.1.3.1 Clock Domain ............................................................................................. 230
3.1.3.2 Power Domain ............................................................................................ 231
3.1.3.3 Voltage Domain ........................................................................................... 232
3.1.4 Device Power-Management Architecture .................................................................... 233
3.1.4.1 Module Interface and Functional Clocks ............................................................... 234
3.1.4.2 Autoidle Clock Control ................................................................................... 235
3.1.5 SmartReflex Voltage-Control Overview ...................................................................... 236
3.1.5.1 Manual SmartReflex Voltage Control .................................................................. 237
3.1.5.2 Automatic SmartReflex Voltage Control ............................................................... 238
3.2 PRCM Overview ......................................................................................................... 239
3.2.1 Introduction ...................................................................................................... 239
3.2.2 PRCM Features ................................................................................................. 241
3.3 PRCM Environment ...................................................................................................... 242
3.3.1 External Clock Signals ......................................................................................... 243
3.3.2 External Reset Signals ......................................................................................... 244
3.3.3 External Power Signals ........................................................................................ 245
3.4 PRCM Integration ........................................................................................................ 246
3.4.1 Power-Management Scheme, Reset, and Interrupt Requests ............................................ 249
3.4.1.1 Power Domain ............................................................................................ 249
3.4.1.2 Resets ...................................................................................................... 249
3.4.1.3 Interrupt Requests ........................................................................................ 250
3.5 PRCM Functional Description .......................................................................................... 251
3.5.1 PRCM Reset Manager Functional Description .............................................................. 251
3.5.1.1 Overview ................................................................................................... 251
3.5.1.2 General Characteristics of Reset Signals ............................................................. 251
3.5.1.2.1 Scope .................................................................................................. 252
3.5.1.2.2 Occurrence ............................................................................................ 252
3.5.1.2.3 Source Type .......................................................................................... 252
3.5.1.3 Reset Sources ............................................................................................ 252
3.5.1.3.1 Global Reset Sources ............................................................................... 253
3.5.1.3.2 Local Reset Sources ................................................................................. 254
3.5.1.4 Reset Distribution ......................................................................................... 255
3.5.1.5 Power Domain Reset Descriptions ..................................................................... 256
3.5.1.5.1 MPU Power Domain ................................................................................. 256
3.5.1.5.2 NEON Power Domain ............................................................................... 256
3.5.1.5.3 IVA2 Power Domain ................................................................................. 256
3.5.1.5.4 CORE Power Domain ............................................................................... 256
3.5.1.5.5 DSS Power Domain .................................................................................. 257
3.5.1.5.6 CAM Power Domain ................................................................................. 257
3.5.1.5.7 USBHOST Power Domain .......................................................................... 257
3.5.1.5.8 SGX Power Domain ................................................................................. 257
3.5.1.5.9 WKUP Power Domain ............................................................................... 257
3.5.1.5.10 PER Power Domain ................................................................................. 258
3.5.1.5.11 SmartReflex Power Domain ........................................................................ 258
3.5.1.5.12 DPLL Power Domains ............................................................................... 258
3.5.1.5.13 EFUSE Power Domain .............................................................................. 258
4Contents SWPU177N–December 2009–Revised November 2010
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3.5.1.5.14 BANDGAP Logic ..................................................................................... 259
3.5.1.5.15 External Warm Reset Assertion .................................................................... 259
3.5.1.6 Reset Logging ............................................................................................. 259
3.5.1.6.1 PRCM Reset Logging Mechanism ................................................................. 259
3.5.1.6.2 SCM Reset Logging ................................................................................. 260
3.5.1.7 Reset Management Overview ........................................................................... 260
3.5.1.8 Reset Summary ........................................................................................... 265
3.5.1.9 Reset Sequences ......................................................................................... 268
3.5.1.9.1 Power-Up Sequence ................................................................................. 268
3.5.1.9.2 Global Warm Reset Sequence ..................................................................... 270
3.5.1.9.3 IVA2.2 Subsystem Power-Up Sequence .......................................................... 272
3.5.1.9.4 IVA2 Software Reset Sequence .................................................................... 274
3.5.1.9.5 IVA2 Global Warm Reset Sequence .............................................................. 276
3.5.1.9.6 IVA2 Power Domain Wake-Up Cold Reset Sequence .......................................... 278
3.5.2 PRCM Power Manager Functional Description ............................................................. 281
3.5.2.1 Overview ................................................................................................... 281
3.5.2.1.1 Introduction ............................................................................................ 281
3.5.2.1.2 Device Partitioning ................................................................................... 282
3.5.2.1.3 Memory and Logic Power Management .......................................................... 284
3.5.2.1.4 Retention Till Access (RTA) Memory Feature .................................................... 284
3.5.2.1.5 Power Domain States ............................................................................... 285
3.5.2.1.6 Power State Transitions ............................................................................. 285
3.5.2.1.7 Device Power Modes ................................................................................ 286
3.5.2.1.8 Isolation Between Power Domains ................................................................ 286
3.5.2.2 Power Domain Implementation ......................................................................... 286
3.5.2.2.1 Device Power Domains .............................................................................. 286
3.5.2.2.2 Power Domain Memory Status ..................................................................... 288
3.5.2.2.3 Power Domain State Transition Rules ............................................................ 288
3.5.2.2.4 Power Domain Dependencies ...................................................................... 288
3.5.2.2.5 Power Domain Controls ............................................................................. 289
3.5.3 PRCM Clock Manager Functional Description .............................................................. 291
3.5.3.1 Overview ................................................................................................... 291
3.5.3.1.1 Interface and Functional Clocks .................................................................... 292
3.5.3.2 External Clock I/Os ....................................................................................... 293
3.5.3.2.1 External Clock Inputs ................................................................................ 293
3.5.3.2.2 External Clock Outputs .............................................................................. 294
3.5.3.2.3 Summary .............................................................................................. 294
3.5.3.3 Internal Clock Generation ............................................................................... 294
3.5.3.3.1 PRM .................................................................................................... 296
3.5.3.3.2 CM ..................................................................................................... 298
3.5.3.3.3 DPLLs .................................................................................................. 300
3.5.3.3.4 DPLL Clock Summary ............................................................................... 308
3.5.3.3.5 Summary .............................................................................................. 308
3.5.3.4 Clock Distribution ......................................................................................... 309
3.5.3.4.1 Power Domain Clock Distribution .................................................................. 309
3.5.3.4.2 Clock Distribution Summary ........................................................................ 323
3.5.3.5 External Clock Controls .................................................................................. 325
3.5.3.5.1 Clock Request (sys_clkreq) Control ............................................................... 325
3.5.3.5.2 System Clock Oscillator Control .................................................................... 326
3.5.3.5.3 External Output Clock1 (sys_clkout1) Control .................................................... 329
3.5.3.5.4 External Output Clock2 (sys_clkout2) Control .................................................... 329
3.5.3.6 DPLL Control .............................................................................................. 329
3.5.3.6.1 DPLL Multiplier and Divider Factors ............................................................... 329
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SWPU177N–December 2009–Revised November 2010 Contents
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3.5.3.6.2 DPLL Modes .......................................................................................... 329
3.5.3.6.3 DPLL Low-Power Mode ............................................................................. 331
3.5.3.6.4 DPLL Clock Path Power Down ..................................................................... 332
3.5.3.6.5 Recalibration .......................................................................................... 332
3.5.3.6.6 DPLL Programming Sequence ..................................................................... 333
3.5.3.7 Internal Clock Controls ................................................................................... 334
3.5.3.7.1 PRM Source-Clock Controls ........................................................................ 334
3.5.3.7.2 CM Source-Clock Controls .......................................................................... 336
3.5.3.7.3 Common Interface Clock Controls ................................................................. 338
3.5.3.7.4 DPLL Source-Clock Controls ....................................................................... 339
3.5.3.7.5 SGX Power Domain Clock Controls ............................................................... 340
3.5.3.7.6 CORE Power Domain Clock Controls ............................................................. 341
3.5.3.7.7 EFUSE Power Domain Clock Controls ............................................................ 343
3.5.3.7.8 DSS Power Domain Clock Controls ............................................................... 343
3.5.3.7.9 CAM Power Domain Clock Controls ............................................................... 344
3.5.3.7.10 USBHOST Power Domain Clock Controls ....................................................... 345
3.5.3.7.11 WKUP Power Domain Clock Controls ............................................................ 346
3.5.3.7.12 PER Power Domain Clock Controls ............................................................... 347
3.5.3.7.13 SMARTREFLEX Power Domain Clock Controls ................................................. 349
3.5.3.8 Clock Configurations ..................................................................................... 350
3.5.3.8.1 Processor Clock Configurations .................................................................... 350
3.5.3.8.2 Interface and Peripheral Functional Clock Configurations ...................................... 351
3.5.4 PRCM Idle and Wake-Up Management ..................................................................... 353
3.5.4.1 Overview ................................................................................................... 353
3.5.4.2 Sleep Transition ........................................................................................... 355
3.5.4.3 Wakeup .................................................................................................... 355
3.5.4.4 Device Wake-Up Events ................................................................................. 356
3.5.4.5 Sleep and Wake-Up Dependencies .................................................................... 361
3.5.4.5.1 Sleep Dependencies ................................................................................. 361
3.5.4.5.2 Wake-Up Dependencies ............................................................................ 363
3.5.4.6 USBHOST/USBTLL Save-and-Restore Management ............................................... 366
3.5.4.6.1 USBHOST SAR Sequences ........................................................................ 368
3.5.4.6.2 USB TLL SAR Sequences .......................................................................... 368
3.5.5 PRCM Interrupts ................................................................................................ 369
3.5.6 PRCM Voltage Management Functional Description ...................................................... 371
3.5.6.1 Overview ................................................................................................... 371
3.5.6.2 Voltage Domains .......................................................................................... 375
3.5.6.3 Voltage Domain Dependencies ......................................................................... 376
3.5.6.4 Voltage-Control Architecture ............................................................................ 377
3.5.6.5 VDD1 and VDD2 Control ................................................................................ 379
3.5.6.5.1 Direct Control With VMODE Signals ............................................................... 379
3.5.6.5.2 Direct Voltage Control With I2C Interface ......................................................... 380
3.5.6.5.3 Voltage Controller and Dedicated SmartReflex I2C Interface .................................. 380
3.5.6.5.4 SmartReflex Voltage Control ....................................................................... 380
3.5.6.6 Analog Cells, LDOs, and Level Shifter Controls ...................................................... 389
3.5.6.6.1 ABB LDOs Control ................................................................................... 389
3.5.6.6.2 SRAM Voltage Control .............................................................................. 390
3.5.6.6.3 Wake-Up and Emulation Voltage Control ......................................................... 390
3.5.7 PRCM Off-Mode Management ................................................................................ 391
3.5.7.1 Overview ................................................................................................... 391
3.5.7.2 Device Off-Mode Configuration ......................................................................... 391
3.5.7.2.1 Overview .............................................................................................. 391
3.5.7.2.2 I/O Wake-Up Mechanism ........................................................................... 392
6Contents SWPU177N–December 2009–Revised November 2010
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3.5.7.3 CORE Power Domain Off-Mode Sequences ......................................................... 393
3.5.7.3.1 Sleep Sequences (Transition From On to Retention/Off) ....................................... 393
3.5.7.3.2 Wake-Up Sequences (Transition From Retention/Off to On) .................................. 394
3.5.7.4 Device Off-Mode Sequences ............................................................................ 394
3.5.7.4.1 Sleep Sequences .................................................................................... 394
3.5.7.4.2 Wake-Up Sequences ................................................................................ 396
3.6 PRCM Basic Programming Model ..................................................................................... 397
3.6.1 Global Registers ................................................................................................ 397
3.6.1.1 Revision Information Registers ......................................................................... 397
3.6.1.2 PRCM Configuration Registers ......................................................................... 397
3.6.1.3 Interrupt Configuration Registers ....................................................................... 397
3.6.1.3.1 MPU Interrupt Event Sources ...................................................................... 398
3.6.1.3.2 MPU Interrupt Registers ............................................................................. 399
3.6.1.3.3 IVA2.2 Interrupt Event Sources .................................................................... 399
3.6.1.3.4 IVA2 Interrupt Registers ............................................................................. 399
3.6.1.4 Event Generator Control Registers ..................................................................... 399
3.6.1.5 Output Signal Polarity Control Registers .............................................................. 400
3.6.1.5.1 CM_POLCTRL (CM Polarity Control Register) ................................................... 400
3.6.1.5.2 PRM_POLCTRL (PRM Polarity Control Register) ............................................... 401
3.6.1.6 SRAM Precharge Time Control Register .............................................................. 402
3.6.1.6.1 PRM_SRAM_PCHARGE (Voltage SRAM Precharge Counter Register) ..................... 402
3.6.2 Clock Management Registers ................................................................................. 402
3.6.2.1 System Clock Control Registers ........................................................................ 402
3.6.2.1.1 PRM_CLKSRC_CTRL (Clock Source Control Register) ........................................ 402
3.6.2.1.2 PRM_CLKSETUP (Source-Clock Setup Register) .............................................. 402
3.6.2.1.3 PRM_CLKSEL (Source-Clock Selection Register) .............................................. 402
3.6.2.2 External Clock Output Control Registers .............................................................. 402
3.6.2.2.1 PRM_CLKOUT_CTRL (Clock Out Control Register) ............................................ 402
3.6.2.2.2 CM_CLKOUT_CTRL (Clock Out Control Register) .............................................. 403
3.6.2.3 DPLL Clock Control Registers .......................................................................... 403
3.6.2.3.1 CM_CLKSELn_PLL_ <processor_name> (Processor DPLL Clock Selection Register) .... 403
3.6.2.3.2 CM_CLKSELn_PLL (DPLL Clock Selection Register) .......................................... 403
3.6.2.3.3 CM_CLKEN_PLL_<processor_name> (Processor DPLL Clock Enable Register) .......... 404
3.6.2.3.4 CM_CLKEN_PLL (DPLL Enable Register) ....................................................... 404
3.6.2.3.5 CM_AUTOIDLE_PLL_ <processor_name> (Processor DPLL Autoidle Register) ........... 404
3.6.2.3.6 CM_AUTOIDLE_PLL (DPLL Autoidle Register) ................................................. 405
3.6.2.3.7 CM_AUTOIDLE1_PLL (DPLL5 Autoidle Register) .............................................. 405
3.6.2.3.8 CM_IDLEST_CKGEN (Source-Clock Idle-Status Register) .................................... 405
3.6.2.3.9 CM_IDLEST2_CKGEN (DPLL5 Source-Clock Idle-Status Register) .......................... 405
3.6.2.3.10 CM_IDLEST_PLL_ <processor_name> (Processor DPLL Idle-Status Register) ............ 405
3.6.2.4 Power-Domain Clock Control Registers ............................................................... 406
3.6.2.4.1 CM_CLKSEL_ <domain_name> (Clock Select Register) ....................................... 406
3.6.2.4.2 CM_FCLKEN_ <domain_name> (Functional Clock Enable Register) ........................ 407
3.6.2.4.3 CM_ICLKEN_ <domain_name> (Interface Clock Enable Register) ........................... 407
3.6.2.4.4 CM_AUTOIDLE_ <domain_name> (Autoidle Register) ......................................... 408
3.6.2.4.5 CM_IDLEST_ <domain_name> (Idle-Status Register) .......................................... 408
3.6.2.4.6 CM_CLKSTCTRL_ <domain_name> (Clock State Control Register) ......................... 409
3.6.2.4.7 CM_CLKSTST_ <domain_name> (Clock State Status Register) .............................. 410
3.6.2.4.8 CM_SLEEPDEP_ <domain_name> (Sleep Dependency Control Register) ................. 410
3.6.2.5 Domain Wake-Up Control Registers ................................................................... 411
3.6.2.5.1 PM_WKEN_ <domain_name> (Wake-Up Enable Register) .................................... 411
3.6.2.5.2 PM_WKST_ <domain_name> (Wake-Up Status Register) ..................................... 411
3.6.2.5.3 PM_WKDEP_ <domain_name> (Wake-Up Dependency Register) ........................... 412
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SWPU177N–December 2009–Revised November 2010 Contents
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3.6.2.5.4 PM_ <processor_name> GRPSEL_ <domain_name> (Processor Group Selection Register)
.......................................................................................................... 413
3.6.3 Reset Management Registers ................................................................................. 413
3.6.3.1 Reset Control .............................................................................................. 413
3.6.3.1.1 PRM_RSTTIME (Reset Time Register) ........................................................... 413
3.6.3.1.2 RM_RSTCTRL_ <domain_name> (Reset Control Register) ................................... 414
3.6.3.1.3 RM_RSTST_ <domain_name> (Reset Status Register) ........................................ 414
3.6.4 Power Management Registers ................................................................................ 416
3.6.4.1 PM_PWSTCTRL_ <domain_name> (Power State Control Register) .............................. 416
3.6.4.2 PM_PWSTST_ <domain_name> (Power State Status Register) .................................. 418
3.6.4.3 PM_PREPWSTST_ <domain_name> (Previous Power State Status Register) ................. 419
3.6.5 Voltage Management Registers ............................................................................... 419
3.6.5.1 External Voltage Control Register Descriptions ...................................................... 419
3.6.5.1.1 PRM_VOLTSETUP (Voltage Setup Time Register) ............................................. 419
3.6.5.1.2 PRM_VOLTOFFSET (Voltage Offset Register) .................................................. 420
3.6.5.1.3 PRM_VOLTCTRL (Voltage Source Control Register) ........................................... 421
3.6.5.2 Voltage Controller Registers ............................................................................ 421
3.6.5.2.1 PRM_VC_SMPS_SA (Voltage Controller SMPS Slave Address Register) .................. 422
3.6.5.2.2 PRM_VC_SMPS_VOL_RA (Voltage Controller SMPS Voltage Register Address Register)
.......................................................................................................... 422
3.6.5.2.3 PRM_VC_SMPS_CMD_RA (Voltage Controller SMPS Command Register Address Register)
.......................................................................................................... 422
3.6.5.2.4 PRM_VC_CMD_VAL_0 and PRM_VC_CMD_VAL_1 (Voltage Controller Command and
Voltage Value Register 0 and 1) ................................................................... 422
3.6.5.2.5 PRM_VC_CH_CONF (Voltage Controller Channel Configuration Register) ................. 422
3.6.5.2.6 PRM_VC_I2C_CFG (Voltage Controller I2C Interface Configuration Register) .............. 422
3.6.5.2.7 PRM_VC_BYPASS_VAL (Voltage Controller Bypass Command Register) .................. 423
3.6.5.3 Voltage Processor Registers ............................................................................ 423
3.6.5.3.1 PRM_VP_CONFIG (Voltage Processor Configuration Register) .............................. 423
3.6.5.3.2 PRM_VP_VSTEPMIN (Voltage Processor Minimum Voltage Step) ........................... 423
3.6.5.3.3 PRM_VP_VSTEPMAX (Voltage Processor Maximum Voltage Step) ......................... 423
3.6.5.3.4 PRM_VP_VLIMITTO (Voltage Processor Voltage Limit and Time-Out) ...................... 424
3.6.5.3.5 PRM_VP_VOLTAGE (Voltage Processor Voltage Register) ................................... 424
3.6.5.3.6 PRM_VP_STATUS (Voltage Processor Status Register) ...................................... 424
3.6.6 Generic Programming Examples ............................................................................. 424
3.6.6.1 Clock Control .............................................................................................. 424
3.6.6.1.1 Enabling and Disabling the Functional Clocks ................................................... 424
3.6.6.1.2 Enabling and Disabling the Interface Clocks ..................................................... 426
3.6.6.1.3 Enabling and Disabling the Inactive State ........................................................ 427
3.6.6.1.4 Processor Clock Control ............................................................................ 428
3.6.6.2 Reset Management ....................................................................................... 431
3.6.6.3 Wake-Up Control ......................................................................................... 431
3.6.6.4 SmartReflex Module Initialization Basic Programming Model ...................................... 432
3.6.6.5 Voltage Processor Initialization Basic Programming Model ......................................... 435
3.6.6.6 Voltage Controller Initialization Basic Programming Model ......................................... 439
3.6.6.7 Changing OPP Using the SmartReflex Module ....................................................... 442
3.6.6.8 Changing OPP Using Only the Voltage Processor Module ......................................... 444
3.6.6.9 Event Generator Programming Examples ............................................................. 446
3.7 PRCM Use Cases and Tips ............................................................................................ 447
3.7.1 DVFS Using Device SmartReflex With TWL5030 Power IC .............................................. 447
3.7.1.1 Device DVFS Support Architecture .................................................................... 447
3.7.1.2 TWL5030 DVFS Support Architecture ................................................................. 448
3.7.1.2.1 SMPS .................................................................................................. 448
3.7.1.2.2 I2C Interface ........................................................................................... 449
8Contents SWPU177N–December 2009–Revised November 2010
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3.7.1.3 DVFS Using SmartReflex ................................................................................ 450
3.7.1.3.1 Device SmartReflex Initialization ................................................................... 451
3.7.1.3.2 Switch VDD1 OPPs .................................................................................. 453
3.7.1.3.3 Switch VDD2 OPPs .................................................................................. 454
3.7.2 Voltage Control Using VMODE ............................................................................... 456
3.7.2.1 Introduction ................................................................................................ 456
3.7.2.2 Programming Sequence ................................................................................. 457
3.7.2.2.1 Initialization Procedure .............................................................................. 457
3.7.2.2.2 VMODE Signals Toggling ........................................................................... 457
3.7.2.2.3 Summary Flow Chart ................................................................................ 458
3.8 PRCM Register Manual ................................................................................................. 459
3.8.1 CM Module Registers .......................................................................................... 459
3.8.1.1 CM Instance Summary ................................................................................... 459
3.8.1.2 IVA2_CM Registers ...................................................................................... 459
3.8.1.2.1 IVA2_CM Register Summary ....................................................................... 459
3.8.1.2.2 IVA2_CM Registers .................................................................................. 460
3.8.1.3 OCP_System_Reg_CM Registers ..................................................................... 466
3.8.1.3.1 OCP_System_Reg_CM Register Summary ...................................................... 466
3.8.1.3.2 OCP_System_Reg_CM Registers ................................................................. 466
3.8.1.4 MPU_CM Registers ...................................................................................... 467
3.8.1.4.1 MPU_CM Register Summary ....................................................................... 467
3.8.1.4.2 MPU_CM Registers .................................................................................. 467
3.8.1.5 CORE_CM Registers .................................................................................... 473
3.8.1.5.1 CORE_CM Register Summary ..................................................................... 473
3.8.1.5.2 CORE_CM Registers ................................................................................ 474
3.8.1.6 SGX_CM Registers ....................................................................................... 487
3.8.1.6.1 SGX_CM Register Summary ....................................................................... 487
3.8.1.6.2 SGX_CM Registers .................................................................................. 488
3.8.1.7 WKUP_CM Registers .................................................................................... 492
3.8.1.7.1 WKUP_CM Register Summary ..................................................................... 492
3.8.1.7.2 WKUP_CM Registers ................................................................................ 492
3.8.1.8 Clock_Control_Reg_CM Registers ..................................................................... 497
3.8.1.8.1 Clock_Control_Reg_CM Register Summary ..................................................... 497
3.8.1.8.2 Clock_Control_Reg_CM Registers ................................................................ 498
3.8.1.9 DSS_CM Registers ....................................................................................... 510
3.8.1.9.1 DSS_CM Register Summary ....................................................................... 510
3.8.1.9.2 DSS_CM Registers .................................................................................. 510
3.8.1.10 CAM_CM Registers ...................................................................................... 517
3.8.1.10.1 CAM_CM Register Summary ....................................................................... 517
3.8.1.10.2 CAM_CM Registers .................................................................................. 518
3.8.1.11 PER_CM Registers ....................................................................................... 523
3.8.1.11.1 PER_CM Register Summary ....................................................................... 523
3.8.1.11.2 PER_CM Registers .................................................................................. 524
3.8.1.12 EMU_CM Registers ...................................................................................... 534
3.8.1.12.1 EMU_CM Register Summary ....................................................................... 534
3.8.1.12.2 EMU_CM Registers .................................................................................. 535
3.8.1.13 Global_Reg_CM Registers .............................................................................. 540
3.8.1.13.1 Global_Reg_CM Register Summary .............................................................. 540
3.8.1.13.2 Global_Reg_CM Registers ......................................................................... 540
3.8.1.14 NEON_CM Registers .................................................................................... 541
3.8.1.14.1 NEON_CM Register Summary ..................................................................... 541
3.8.1.14.2 NEON_CM Registers ................................................................................ 541
3.8.1.15 USBHOST_CM Registers ............................................................................... 543
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3.8.1.15.1 USBHOST_CM Register Summary ................................................................ 543
3.8.1.15.2 USBHOST_CM Registers ........................................................................... 543
3.8.2 PRM Module Registers ......................................................................................... 548
3.8.2.1 PRM Instance Summary ................................................................................. 548
3.8.2.2 IVA2_PRM Registers ..................................................................................... 548
3.8.2.2.1 IVA2_PRM Register Summary ..................................................................... 548
3.8.2.2.2 IVA2_PRM Registers ................................................................................ 549
3.8.2.3 OCP_System_Reg_PRM Registers .................................................................... 559
3.8.2.3.1 OCP_System_Reg PRM Register Summary ..................................................... 559
3.8.2.3.2 OCP_System_Reg_PRM Registers ............................................................... 559
3.8.2.4 MPU_PRM Registers Registers ........................................................................ 568
3.8.2.4.1 MPU_PRM Registers Register Summary ......................................................... 568
3.8.2.4.2 MPU_PRM Registers ................................................................................ 568
3.8.2.5 CORE_PRM Registers ................................................................................... 575
3.8.2.5.1 CORE_PRM Register Summary ................................................................... 575
3.8.2.5.2 CORE_PRM Registers .............................................................................. 576
3.8.2.6 SGX_PRM Registers ..................................................................................... 591
3.8.2.6.1 SGX_PRM Register Summary ..................................................................... 591
3.8.2.6.2 SGX_PRM Registers ................................................................................ 592
3.8.2.7 WKUP_PRM Registers .................................................................................. 595
3.8.2.7.1 WKUP_PRM Register Summary ................................................................... 595
3.8.2.7.2 WKUP_PRM Registers .............................................................................. 596
3.8.2.8 Clock_Control_Reg_PRM Registers ................................................................... 600
3.8.2.8.1 Clock_Control_Reg_PRM Register Summary .................................................... 600
3.8.2.8.2 Clock_Control_Reg_PRM Registers ............................................................... 601
3.8.2.9 DSS_PRM Registers ..................................................................................... 602
3.8.2.9.1 DSS_PRM Register Summary ..................................................................... 602
3.8.2.9.2 DSS_PRM Registers ................................................................................ 602
3.8.2.10 CAM_PRM Registers .................................................................................... 607
3.8.2.10.1 CAM_PRM Registers ................................................................................ 607
3.8.2.10.2 CAM_PRM Registers ................................................................................ 607
3.8.2.11 PER_PRM Registers ..................................................................................... 611
3.8.2.11.1 PER_PRM Register Summary ..................................................................... 611
3.8.2.11.2 PER_PRM Registers ................................................................................ 611
3.8.2.12 EMU_PRM Registers .................................................................................... 624
3.8.2.12.1 EMU_PRM Register Summary ..................................................................... 624
3.8.2.12.2 EMU_PRM Registers ................................................................................ 624
3.8.2.13 Global_Reg_PRM Registers ............................................................................ 626
3.8.2.13.1 Global_Reg_PRM Register Summary ............................................................. 626
3.8.2.13.2 Global_Reg_PRM Registers ........................................................................ 627
3.8.2.14 NEON_PRM Registers ................................................................................... 650
3.8.2.14.1 NEON_PRM Register Summary ................................................................... 650
3.8.2.14.2 NEON_PRM Registers .............................................................................. 651
3.8.2.15 USBHOST_PRM Registers ............................................................................. 654
3.8.2.15.1 USBHOST_PRM Register Summary .............................................................. 654
3.8.2.15.2 USBHOST_PRM Registers ......................................................................... 655
3.8.3 SR Registers ..................................................................................................... 661
3.8.3.1 SR Instance Summary ................................................................................... 661
3.8.3.2 SR Registers .............................................................................................. 661
3.8.3.2.1 SR Register Summary ............................................................................... 661
3.8.3.2.2 SR Registers .......................................................................................... 662
4 MPU Subsystem .............................................................................................................. 675
4.1 MPU Subsystem Overview ............................................................................................. 676
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4.1.1 Introduction ...................................................................................................... 676
4.1.2 Features .......................................................................................................... 676
4.2 MPU Subsystem Integration ............................................................................................ 678
4.2.1 MPU Subsystem Clock and Reset Distribution ............................................................. 679
4.2.1.1 Clock Distribution ......................................................................................... 679
4.2.1.2 Reset Distribution ......................................................................................... 680
4.2.2 ARM Subchip .................................................................................................... 682
4.2.2.1 ARM Overview ............................................................................................ 682
4.2.2.2 ARM Description .......................................................................................... 682
4.2.2.2.1 ARM Cortex-A8 Instruction, Data, and Private Peripheral Port ................................ 682
4.2.2.2.2 MPU Subsystem Features .......................................................................... 682
4.2.2.3 Clock, Reset, and Power Management ................................................................ 683
4.2.2.3.1 Clocks .................................................................................................. 683
4.2.2.3.2 Reset ................................................................................................... 683
4.2.2.3.3 Power Management ................................................................................. 683
4.2.3 Local Interconnect .............................................................................................. 683
4.2.3.1 Description ................................................................................................. 683
4.2.3.2 Clocks, Reset, and Power Management .............................................................. 683
4.2.3.2.1 Clocks .................................................................................................. 683
4.2.3.2.2 Reset ................................................................................................... 683
4.2.3.2.3 Power Management ................................................................................. 684
4.2.4 Interrupt Controller .............................................................................................. 684
4.2.4.1 Clocks ...................................................................................................... 684
4.2.4.2 Reset ....................................................................................................... 684
4.2.4.3 Power Management ...................................................................................... 684
4.3 MPU Subsystem Functional Description .............................................................................. 685
4.3.1 Interrupts ......................................................................................................... 685
4.3.2 Power Management ............................................................................................ 685
4.3.2.1 Power Domains ........................................................................................... 685
4.3.2.2 Power States .............................................................................................. 686
4.3.2.3 Power Modes .............................................................................................. 686
4.3.2.4 Transitions ................................................................................................. 688
4.4 MPU Subsystem Basic Programming Model ......................................................................... 690
4.4.1 MPU Subsystem Initialization Sequence .................................................................... 690
4.4.2 Clock Control .................................................................................................... 690
4.4.3 MPU Power Mode Transitions ................................................................................ 690
4.4.3.1 Basic Power-On Reset ................................................................................... 690
4.4.3.2 MPU Into Standby Mode ................................................................................. 690
4.4.3.3 MPU Out of Standby Mode .............................................................................. 691
4.4.3.4 MPU Power-On From a Powered-Off State ........................................................... 691
4.4.4 ARM Programming Model ..................................................................................... 691
5 IVA2.2 Subsystem ............................................................................................................ 693
5.1 IVA2.2 Subsystem Overview ........................................................................................... 694
5.1.1 IVA2.2 Subsystem Key Features ............................................................................. 694
5.2 IVA2.2 Subsystem Integration .......................................................................................... 696
5.2.1 Clocking, Reset, and Power-Management Scheme ........................................................ 697
5.2.1.1 Clocks ...................................................................................................... 697
5.2.1.1.1 IVA2.2 Clocks ......................................................................................... 697
5.2.1.2 Resets ...................................................................................................... 697
5.2.1.2.1 Hardware Resets ..................................................................................... 697
5.2.1.2.2 Software Resets ...................................................................................... 699
5.2.1.3 Power Domain ............................................................................................ 699
5.2.2 Hardware Requests ............................................................................................. 701
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SWPU177N–December 2009–Revised November 2010 Contents
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5.2.2.1 DMA Requests ............................................................................................ 701
5.2.2.2 Interrupt Requests ........................................................................................ 702
5.3 IVA2.2 Subsystem Functional Description ............................................................................ 706
5.3.1 DSP Megamodule ............................................................................................... 706
5.3.1.1 DSP Overview ............................................................................................. 707
5.3.1.2 Program Memory Controller Overview ................................................................. 708
5.3.1.3 DMC Overview ............................................................................................ 708
5.3.1.4 UMC Overview ............................................................................................ 709
5.3.1.5 EMC Overview ............................................................................................ 710
5.3.1.6 Memory Protection Overview ........................................................................... 710
5.3.1.7 INTC ........................................................................................................ 710
5.3.1.7.1 Event Type ............................................................................................ 712
5.3.1.7.2 Event Behavior ....................................................................................... 712
5.3.1.7.3 Event Detection ....................................................................................... 713
5.3.1.7.4 Event Selection ....................................................................................... 713
5.3.1.7.5 Event Combination ................................................................................... 714
5.3.1.7.6 Interrupt Event Error ................................................................................. 714
5.3.1.7.7 PDC Overview ........................................................................................ 714
5.3.1.8 Other DSP Reference Documents ..................................................................... 714
5.3.2 DMA Engines .................................................................................................... 716
5.3.2.1 EDMA ...................................................................................................... 716
5.3.2.1.1 Third-Party Channel Controller ..................................................................... 717
5.3.2.1.2 Third-Party Transfer Controller ..................................................................... 722
5.3.2.1.3 EDMA Hardware Parameters ....................................................................... 725
5.3.2.2 EDMA Access to Video Accelerator/Sequencer ...................................................... 726
5.3.2.3 IDMA ....................................................................................................... 727
5.3.3 MMU .............................................................................................................. 727
5.3.3.1 MMU VA-to-PA Translation .............................................................................. 728
5.3.3.2 MMU Configuration ....................................................................................... 729
5.3.4 Video Accelerator/Sequencer Local Interconnect .......................................................... 730
5.3.5 SL2 Interface .................................................................................................... 731
5.3.5.1 BWO ........................................................................................................ 732
5.3.5.2 Arbiter ...................................................................................................... 733
5.3.5.3 Restrictions on SL2 Memory Usage .................................................................... 733
5.3.5.4 Error Management ........................................................................................ 733
5.3.6 Wake-Up Generator ............................................................................................ 733
5.3.6.1 Interrupts, DMA Requests, and Event Management ................................................. 734
5.3.6.1.1 Event Generation ..................................................................................... 734
5.3.6.1.2 Individual Event Masking ............................................................................ 735
5.3.6.1.3 Individual Event Mask Clear ........................................................................ 736
5.3.6.2 Idle Handshake ........................................................................................... 737
5.3.7 SYSC Module ................................................................................................... 737
5.3.7.1 Divided Clock Generation ............................................................................... 738
5.3.7.2 Clock Management, Power-Down, and Wake-Up .................................................... 738
5.3.7.3 Boot Configuration ........................................................................................ 739
5.3.7.4 Interconnect Optimization ................................................................................ 739
5.3.7.5 Video Accelerator/Sequencer SYSC ................................................................... 739
5.3.7.5.1 Reset ................................................................................................... 739
5.3.7.5.2 Power Management ................................................................................. 739
5.3.7.5.3 Interrupt Handler ..................................................................................... 740
5.3.8 Local Memories ................................................................................................. 740
5.3.8.1 ROM Overview ............................................................................................ 742
5.3.8.2 RAM Overview ............................................................................................ 742
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5.3.9 Local Interconnect Network .................................................................................... 742
5.3.9.1 Endianness ................................................................................................ 743
5.3.10 Error Reporting ................................................................................................. 743
5.4 IVA2.2 Subsystem Basic Programming Model ....................................................................... 744
5.4.1 IVA2.2 Boot ...................................................................................................... 744
5.4.1.1 IVA2.2 Boot Configuration ............................................................................... 744
5.4.1.1.1 IDLE Boot Mode ...................................................................................... 745
5.4.1.1.2 Wait in Self-Loop Mode ............................................................................. 745
5.4.1.1.3 Default Config Cache Mode ........................................................................ 745
5.4.1.1.4 User Defined Bootstrap Mode ...................................................................... 746
5.4.1.2 Example of IVA2.2 Boot ................................................................................. 746
5.4.1.2.1 Boot Under MPU Control ............................................................................ 746
5.4.1.2.2 Autonomous Boot .................................................................................... 748
5.4.2 Sequencer Boot/Reset ......................................................................................... 749
5.4.3 Cache Management ............................................................................................ 749
5.4.3.1 Cache-Size Configuration ............................................................................... 749
5.4.3.2 Cache Mode Configuration .............................................................................. 751
5.4.3.3 Cacheability Settings ..................................................................................... 752
5.4.3.4 Coherence Maintenance ................................................................................. 752
5.4.3.4.1 Memory-Mapped L1P and L1D Coherence ....................................................... 752
5.4.3.4.2 Memory-Mapped L2 Coherence ................................................................... 752
5.4.3.4.3 Device Memory Coherence ......................................................................... 752
5.4.3.4.4 Global Cache Management ......................................................................... 753
5.4.3.4.5 Block Cache Management .......................................................................... 754
5.4.3.4.6 Write-Back Completion .............................................................................. 755
5.4.3.4.7 Performance Consideration Timing ................................................................ 757
5.4.4 DMA Management .............................................................................................. 757
5.4.4.1 Transfers From/to Device Memories/Peripherals (EDMA) .......................................... 757
5.4.4.2 Internal Memory-to-Memory Transfer (IDMA) ......................................................... 757
5.4.4.3 Programming an EDMA Transfer ....................................................................... 758
5.4.4.4 Defining a Logical Channel .............................................................................. 758
5.4.4.4.1 Single Logical Channel Definition .................................................................. 758
5.4.4.4.2 Controlling Submission Granularity ................................................................ 759
5.4.4.4.3 Linking to Another Logical Channel ................................................................ 759
5.4.4.4.4 Chaining Logical Channel ........................................................................... 760
5.4.4.5 Prioritizing Defined Transfers ........................................................................... 760
5.4.4.5.1 Mapping Between DMA/QDMA Events and Event Queues .................................... 760
5.4.4.5.2 Mapping a Queue to a Transfer Controller ....................................................... 760
5.4.4.5.3 Handling Priority ...................................................................................... 761
5.4.4.5.4 Aged Priority .......................................................................................... 761
5.4.4.5.5 Optimizing 2D Transfers ............................................................................ 761
5.4.4.6 Starting the Transfer ..................................................................................... 761
5.4.4.6.1 Assigning a Logical Channel to a Trigger Event ................................................. 762
5.4.4.6.2 Manual Trigger (Software-Synchronized Transfers) ............................................. 762
5.4.4.6.3 Hardware Trigger (Hardware-Synchronized Transfers) ......................................... 762
5.4.4.6.4 Automatic Trigger (QDMA) .......................................................................... 762
5.4.4.6.5 Offloaded Configuration (Using IDMA) ............................................................ 763
5.4.4.6.6 Direct Configuration to Transfer Channel (Not Recommended) ............................... 763
5.4.4.6.7 DMA Completion Mode .............................................................................. 764
5.4.4.6.8 Partial Versus Total Completion .................................................................... 764
5.4.4.6.9 Tracking DMA Completion .......................................................................... 765
5.4.4.6.10 DMA Interrupt Service Routine ..................................................................... 765
5.4.4.6.11 Benchmarking ........................................................................................ 766
13
SWPU177N–December 2009–Revised November 2010 Contents
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5.4.5 IVA2.2 Extended Function Interface .......................................................................... 766
5.4.5.1 Overview ................................................................................................... 766
5.4.5.2 C64x+ EFI Instructions ................................................................................... 766
5.4.5.3 C64x+ EFI Use in IVA2.2 ................................................................................ 770
5.4.5.3.1 Read Registers Using the EFI Programming Model ............................................. 770
5.4.5.3.2 Write Registers Using the EFI Programming Model ............................................. 771
5.4.6 iME and iLF Basic Programming Model ..................................................................... 772
5.4.6.1 Typical Use ................................................................................................ 772
5.4.7 iVLCD Basic Programming Model ............................................................................ 773
5.4.7.1 Setting Up Registers for Q/IQ Operation .............................................................. 775
5.4.7.1.1 Q/IQ Matrix Setup - Inverse Quantizer Matrix .................................................... 775
5.4.7.1.2 Q/IQ Rounding ........................................................................................ 775
5.4.7.1.3 Q/IQ Offset ............................................................................................ 775
5.4.7.1.4 Q/IQ Threshold ....................................................................................... 775
5.4.7.2 Setting Up Registers for VLC Operation ............................................................... 775
5.4.7.3 Setting Up Registers for VLD Operation ............................................................... 777
5.4.7.4 Calculating the Number of Bits Processed During a VLD Run ..................................... 779
5.4.7.5 Setting Up Registers for CAVLC Operation ........................................................... 779
5.4.8 Interrupt Management .......................................................................................... 780
5.4.8.1 Interrupt Flow in IVA2.2 Subsystem .................................................................... 780
5.4.8.2 Event Combined Programming Sequence ............................................................ 782
5.4.8.3 Event <-> Interrupt Mapping Programming Sequence .............................................. 782
5.4.8.4 Interrupt Exception Programming Sequence .......................................................... 782
5.4.8.5 Interrupt Controller Basic Programming Model for Power Down of IVA2.2 Subsystem ......... 783
5.4.8.6 Interrupt Controller Basic Programming Model for Power On of IVA2.2 Subsystem ............ 783
5.4.8.7 Video and Sequencer Module interrupt Handling .................................................... 786
5.4.8.7.1 Sequencer Interrupt .................................................................................. 786
5.4.8.7.2 DSP Megamodule Interrupt ......................................................................... 786
5.4.9 Memory Management .......................................................................................... 788
5.4.9.1 External Memory .......................................................................................... 788
5.4.9.1.1 Cacheability ........................................................................................... 788
5.4.9.1.2 Virtual Addressing .................................................................................... 788
5.4.9.2 Internal Memory ........................................................................................... 788
5.4.9.2.1 Memory Protection ................................................................................... 788
5.4.9.2.2 Bandwidth Management ............................................................................. 793
5.4.9.3 SL2 Memory Management .............................................................................. 795
5.4.9.3.1 SL2 Performance Optimizations ................................................................... 795
5.4.9.3.2 SL2 Performance Limitations ....................................................................... 795
5.4.9.3.3 SL2 Illegal Accesses ................................................................................. 795
5.4.10 IVA2.2 Power Management .................................................................................. 796
5.4.10.1 Clock Management ....................................................................................... 796
5.4.10.1.1 Clock Configuration .................................................................................. 796
5.4.10.1.2 Clock Gating .......................................................................................... 796
5.4.10.2 Reset Management ....................................................................................... 796
5.4.10.3 Power-Down and Wake-Up Management ............................................................. 797
5.4.10.4 Powering Down L2$ Memory While IVA2 is Active .................................................. 800
5.4.10.5 Video and Sequencer Module Management .......................................................... 801
5.4.10.5.1 Module Dynamic Power Savings .................................................................. 801
5.4.10.5.2 System Dynamic Power Savings .................................................................. 801
5.4.11 Error Identification Process ................................................................................... 802
5.4.11.1 Error Reporting for IDMA Module ....................................................................... 802
5.4.11.2 Error Reporting for EDMA Module ..................................................................... 802
5.4.11.3 Error Reporting for the L3 Interconnect ................................................................ 803
14 Contents SWPU177N–December 2009–Revised November 2010
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5.4.12 Recommendations for Static Settings ....................................................................... 803
5.5 IVA2.2 Subsystem Register Manual ................................................................................... 804
5.5.1 IC Registers ...................................................................................................... 804
5.5.1.1 IC Register Mapping Summary ......................................................................... 805
5.5.1.2 IC Register Descriptions ................................................................................. 805
5.5.2 SYS Registers ................................................................................................... 813
5.5.2.1 SYS Register Mapping Summary ...................................................................... 813
5.5.2.2 SYS Register Descriptions .............................................................................. 813
5.5.3 IDMA Registers .................................................................................................. 816
5.5.3.1 IDMA Register Mapping Summary ..................................................................... 816
5.5.3.2 IDMA Register Descriptions ............................................................................. 816
5.5.4 XMC Registers .................................................................................................. 828
5.5.4.1 XMC Register Mapping Summary ...................................................................... 828
5.5.4.2 XMC Register Descriptions .............................................................................. 829
5.5.5 TPCC Registers ................................................................................................. 854
5.5.5.1 TPCC Register Mapping Summary .................................................................... 854
5.5.5.2 TPCC Register Descriptions ............................................................................ 857
5.5.6 TPTC0 and TPTC1 Registers ................................................................................. 954
5.5.6.1 TPTC0 and TPTC1 Register Mapping Summary ..................................................... 954
5.5.6.2 TPTC0 and TPTC1 Register Descriptions ............................................................ 956
5.5.7 SYSC Registers ................................................................................................. 979
5.5.7.1 SYSC Register Mapping Summary .................................................................... 979
5.5.7.2 SYSC Register Descriptions ............................................................................ 981
5.5.8 WUGEN Registers .............................................................................................. 985
5.5.8.1 WUGEN Register Mapping Summary ................................................................. 985
5.5.8.2 WUGEN Register Descriptions ......................................................................... 986
5.5.9 iVLCD Registers ............................................................................................... 1004
5.5.9.1 iVLCD Register Mapping Summary ................................................................... 1004
5.5.9.2 iVLCD Register Descriptions .......................................................................... 1006
5.5.10 SEQ Registers ................................................................................................ 1044
5.5.10.1 SEQ Register Mapping Summary ..................................................................... 1044
5.5.10.2 SEQ Register Descriptions ............................................................................ 1044
5.5.11 Video System Controller Registers ........................................................................ 1051
5.5.11.1 Video System Controller Register Mapping Summary ............................................. 1051
5.5.11.2 Video System Controller Register Descriptions ..................................................... 1051
5.5.12 iME Registers ................................................................................................. 1057
5.5.12.1 iME Register Mapping Summary ...................................................................... 1057
5.5.12.2 iME Register Descriptions .............................................................................. 1058
5.5.13 iLF Registers .................................................................................................. 1068
5.5.13.1 iLF Register Mapping Summary ....................................................................... 1068
5.5.13.2 iLF Register Descriptions .............................................................................. 1069
5.5.14 IA_GEM Registers ........................................................................................... 1079
5.5.14.1 IA_GEM Register Mapping Summary ................................................................ 1079
5.5.14.2 IA_GEM Register Descriptions ........................................................................ 1079
5.5.15 IA_EDMA Registers .......................................................................................... 1080
5.5.15.1 IA_EDMA Register Mapping Summary .............................................................. 1080
5.5.15.2 IA_EDMA Register Descriptions ...................................................................... 1080
5.5.16 IA_SEQ Registers ............................................................................................ 1081
5.5.16.1 IA_SEQ Register Mapping Summary ................................................................. 1081
5.5.16.2 IA_SEQ Register Descriptions ........................................................................ 1081
6 Camera Image Signal Processor ...................................................................................... 1085
6.1 Camera ISP Overview ................................................................................................. 1086
6.1.1 Camera ISP Features ......................................................................................... 1088
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6.2 Camera ISP Environment ............................................................................................. 1091
6.2.1 Camera ISP Functions ........................................................................................ 1091
6.2.2 Camera ISP Signal Descriptions ............................................................................ 1092
6.2.3 Camera ISP Connectivity Schemes ......................................................................... 1093
6.2.4 Camera ISP Protocols and Data Formats .................................................................. 1096
6.2.4.1 Camera ISP Parallel Generic Configuration Protocol and Data Format (8, 10, 11, 12 Bits) .. 1096
6.2.4.2 Camera ISP Parallel Generic Configuration: JPEG Sensor Connection on the Parallel Interface
............................................................................................................. 1097
6.2.4.3 Camera ISP ITU-R BT.656 Protocol and Data Formats (8, 10 Bits) ............................. 1097
6.2.4.4 Camera ISP CSI1/CCP2 Protocol and Data Formats .............................................. 1099
6.2.4.4.1 Camera ISP CSI1/CCP2 Pixel Data Format .................................................... 1102
6.2.4.5 Camera ISP CSI2 Protocol and Data Format ....................................................... 1112
6.2.4.5.1 Camera ISP CSI2 Lane Merger .................................................................. 1112
6.2.4.5.2 Camera ISP CSI2 Protocol Layer ................................................................ 1113
6.2.4.5.3 Camera ISP CSI2 Pixel Data Format ............................................................ 1120
6.3 Camera ISP Integration ................................................................................................ 1139
6.3.1 Camera ISP Clocking, Reset, and Power-Management Scheme ....................................... 1139
6.3.1.1 Camera ISP Clocks ..................................................................................... 1139
6.3.1.1.1 Camera ISP Clock Tree ............................................................................ 1140
6.3.1.1.2 Camera ISP Clock Descriptions .................................................................. 1140
6.3.1.1.3 Camera ISP Clock Configuration ................................................................. 1141
6.3.1.2 Camera ISP Power Management ..................................................................... 1142
6.3.1.2.1 Camera ISP Local Power Management ......................................................... 1142
6.3.1.2.2 Camera ISP System Power Management ....................................................... 1142
6.3.1.3 Camera ISP Power Domain ........................................................................... 1143
6.3.1.4 Camera ISP Resets ..................................................................................... 1143
6.3.1.4.1 Camera ISP Hardware Reset ..................................................................... 1143
6.3.1.4.2 Camera ISP Software Reset ...................................................................... 1144
6.3.2 Camera ISP Hardware Requests ............................................................................ 1144
6.3.2.1 Camera ISP Interrupt Requests ....................................................................... 1144
6.4 Camera ISP Functional Description .................................................................................. 1154
6.4.1 Camera ISP Block Diagram .................................................................................. 1154
6.4.1.1 Camera ISP Possible Data Paths Inside the module .............................................. 1156
6.4.1.1.1 Camera ISP RGB RAW Data ..................................................................... 1157
6.4.1.1.2 Camera ISP YUV4:2:2 Data ....................................................................... 1158
6.4.1.1.3 JPEG Data ........................................................................................... 1158
6.4.2 Camera ISP CSI1/CCP2B Receiver ........................................................................ 1159
6.4.2.1 Camera ISP CSI1/CCP2B Receiver Features ...................................................... 1159
6.4.2.2 Camera ISP CSI1/CCP2B Receiver Functional Description ...................................... 1159
6.4.2.2.1 Camera ISP CSI1/CCP2B Overview ............................................................. 1159
6.4.2.2.2 Camera ISP CSI1/CCP2B Associated PHY ..................................................... 1160
6.4.2.2.3 Camera ISP CSI1/CCP2B Physical Layer ...................................................... 1160
6.4.2.2.4 Camera ISP CSI1/CCP2B Protocol Layer ....................................................... 1161
6.4.2.2.5 Camera ISP CSI1/CCP2B Memory Read Channel ............................................ 1165
6.4.2.2.6 Camera ISP CSI1/CCP2B Image Data Operating Modes and Alignment Constraints .... 1173
6.4.3 Camera ISP CSI2 Receiver .................................................................................. 1176
6.4.3.1 Camera ISP CSI2 Receiver Features ................................................................ 1176
6.4.3.2 Camera ISP CSI2 Receiver Block Diagram ......................................................... 1176
6.4.3.3 Camera ISP CSI2 Physical Layer Lane Configuration ............................................. 1177
6.4.3.4 Camera ISP CSI2 ECC and Checksum Generation ................................................ 1177
6.4.3.4.1 Camera ISP CSI2 ECC ............................................................................ 1177
6.4.3.4.2 Camera ISP CSI2 Checksum ..................................................................... 1178
6.4.3.5 Camera ISP CSI2 RAW Image Transcoding with DPCM and A-law Compression ............ 1178
6.4.3.6 Camera ISP CSI2 Short Packet ....................................................................... 1182
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6.4.3.7 Camera ISP CSI2 Virtual Channel and Context .................................................... 1182
6.4.3.8 Camera ISP CSI2 DMA Engine ....................................................................... 1183
6.4.3.8.1 Camera ISP CSI2 Progressive Frame to Progressive Storage ............................... 1184
6.4.3.8.2 Camera ISP CSI2 Interlaced Frame to Progressive Storage ................................. 1184
6.4.3.9 Camera ISP CSI2 PHYs ............................................................................... 1185
6.4.3.10 Camera ISP CSI2 Data Decompression ............................................................. 1187
6.4.3.11 Camera ISP CSI2 EndOfFrame and EndOfLine pulses ........................................... 1187
6.4.4 Camera ISP Timing Control .................................................................................. 1188
6.4.4.1 Camera ISP Timing Control Features ................................................................ 1188
6.4.4.2 Camera ISP Timing Control Overview ............................................................... 1188
6.4.4.2.1 Camera ISP Timing Control Generator .......................................................... 1188
6.4.4.2.2 Camera ISP Timing Control Control-Signal Generator ........................................ 1188
6.4.5 Camera ISP Bridge-Lane Shifter ............................................................................ 1192
6.4.6 Camera ISP Video-Processing Front End .................................................................. 1192
6.4.6.1 Camera ISP CCDC ..................................................................................... 1193
6.4.6.1.1 Camera ISP CCDC Features ..................................................................... 1193
6.4.6.1.2 Camera ISP CCDC Block Diagram .............................................................. 1193
6.4.6.1.3 Camera ISP CCDC Functional Operations ...................................................... 1194
6.4.6.1.4 Camera ISP CCDC DMA .......................................................................... 1206
6.4.6.1.5 Camera ISP CCDC Memories .................................................................... 1206
6.4.7 Camera ISP Video-Processing Back End .................................................................. 1206
6.4.7.1 Camera ISP VPBE Preview Engine Features ....................................................... 1206
6.4.7.1.1 Camera ISP VPBE Preview Block Diagram ..................................................... 1206
6.4.7.1.2 Camera ISP VPBE Preview Input Interface ..................................................... 1207
6.4.7.1.3 Camera ISP VPBE Preview Input Formatter/Averager ........................................ 1208
6.4.7.1.4 Camera ISP VPBE Preview Dark-Frame Write ................................................. 1208
6.4.7.1.5 Camera ISP VPBE Preview Inverse A-Law ..................................................... 1208
6.4.7.1.6 Camera ISP VPBE Preview Dark-Frame Subtract or Shading Compensation ............. 1209
6.4.7.1.7 Camera ISP VPBE Preview Horizontal Median Filter .......................................... 1209
6.4.7.1.8 Camera ISP VPBE Preview Noise Filter and Faulty Pixel Correction ....................... 1209
6.4.7.1.9 Camera ISP VPBE Preview White Balance ..................................................... 1209
6.4.7.1.10 Camera ISP VPBE Preview CFA Interpolation ................................................. 1210
6.4.7.1.11 Camera ISP VPBE Preview Black Adjustment ................................................. 1210
6.4.7.1.12 Camera ISP VPBE Preview RGB Blending ..................................................... 1210
6.4.7.1.13 Camera ISP VPBE Preview Gamma Correction ............................................... 1211
6.4.7.1.14 Camera ISP VPBE Preview RGB to YCbCr Conversion, Luminance Enhancement,
Chrominance Suppression, Contrast and Brightness, and 4:2:2 Downsampling and Output
Clipping .............................................................................................. 1211
6.4.7.1.15 Camera ISP VPBE Preview Write-Buffer Interface ............................................ 1212
6.4.7.2 Camera ISP VPBE Resizer ............................................................................ 1212
6.4.7.2.1 Camera ISP VPBE Resizer Features ............................................................ 1212
6.4.7.2.2 Camera ISP VPBE Resizer Block Diagram ..................................................... 1213
6.4.7.2.3 Camera ISP VPBE Resizer Input and Output Interfaces ...................................... 1214
6.4.7.2.4 Camera ISP VPBE Resizer Horizontal and Vertical Resizing ................................ 1215
6.4.7.2.5 Camera ISP VPBE Resizer Resampling Algorithm ............................................ 1219
6.4.7.2.6 Camera ISP VPBE Resizer Luma Edge Enhancement ....................................... 1223
6.4.8 Camera ISP Statistics Collection Modules ................................................................. 1224
6.4.8.1 Camera ISP H3A ........................................................................................ 1224
6.4.8.1.1 Camera ISP H3A Features ........................................................................ 1224
6.4.8.1.2 Camera ISP H3A Autofocus Engine ............................................................. 1225
6.4.8.1.3 Camera ISP H3A AE/AWB Engine ............................................................... 1225
6.4.8.2 Camera ISP Histogram ................................................................................. 1225
6.4.8.2.1 Camera ISP Histogram Features ................................................................. 1225
6.4.8.2.2 Camera ISP Histogram Block Diagram .......................................................... 1226
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6.4.8.2.3 Camera ISP Histogram Input Interface .......................................................... 1226
6.4.8.2.4 Camera ISP Histogram White Balance .......................................................... 1226
6.4.8.2.5 Camera ISP Histogram Binning ................................................................... 1227
6.4.9 Camera ISP Central-Resource Shared Buffer Logic ..................................................... 1228
6.4.9.1 Camera ISP Shared Buffer Logic Block Diagram ................................................... 1229
6.4.9.2 Camera ISP Shared Buffer Logic Functional Operations .......................................... 1231
6.4.9.2.1 Camera ISP Shared Buffer Logic Parameters .................................................. 1231
6.4.9.2.2 Camera ISP Shared Buffer Logic Write-Buffer Logic (WBL) and Write Buffer ............. 1231
6.4.9.2.3 Camera ISP Shared Buffer Logic Read Buffer Logic (RBL) and Read Buffer .............. 1232
6.4.9.2.4 Camera ISP Shared Buffer Logic Arbitration .................................................... 1232
6.4.9.3 Camera ISP Shared Buffer Logic Memories ........................................................ 1232
6.4.9.4 Camera ISP Shared Buffer Logic Debug Registers ................................................ 1232
6.4.10 Camera ISP Circular Buffer ................................................................................. 1233
6.4.10.1 Camera ISP Circular Buffer Feature List ............................................................. 1233
6.4.10.2 Camera ISP Circular Buffer Interrupts ................................................................ 1234
6.4.10.3 Camera ISP Circular Buffer Functional Description ................................................ 1234
6.4.10.3.1 Camera ISP Circular Buffer Bandwidth Control Feedback Loop ............................. 1234
6.4.10.3.2 Camera ISP Circular Buffer Window Management ............................................ 1240
6.4.10.3.3 Camera ISP Circular Buffer CPU Interaction ................................................... 1243
6.4.11 Camera ISP MMU Logic ..................................................................................... 1243
6.4.11.1 Camera ISP MMU Features ........................................................................... 1243
6.4.11.2 Camera ISP MMU Functional Description ........................................................... 1244
6.5 Camera ISP Basic Programming Model ............................................................................. 1244
6.5.1 Programming the ISP PRCM Clocks Configuration ....................................................... 1244
6.5.2 Programming the CSI1/CCP2B or CSI2 Receiver Associated PHY .................................... 1244
6.5.2.1 Camera ISP CSIPHY Initialization for Work With CSI2 Receiver ................................. 1244
6.5.2.2 Camera ISP CSIPHY Initialization for Work With CSI1/CCP2B Receiver ....................... 1246
6.5.3 Programming the CSI1/CCP2B Receiver .................................................................. 1247
6.5.3.1 Camera ISP CSI1/CCP2B Hardware Setup/Initialization .......................................... 1247
6.5.3.1.1 Camera ISP CSI1/CCP2B Reset Behavior ...................................................... 1247
6.5.3.2 Camera ISP CSI1/CCP2B Event and Status Checking ............................................ 1248
6.5.3.3 Camera ISP CSI1/CCP2B Register Accessibility During Frame Processing .................... 1248
6.5.3.4 Camera ISP CSI1/CCP2B Enable/Disable the Hardware ......................................... 1248
6.5.3.5 Camera ISP CSI1/CCP2B Select the Signaling Scheme .......................................... 1249
6.5.3.6 Camera ISP CSI1/CCP2B Control of the PHY ...................................................... 1249
6.5.3.7 Camera ISP CSI1/CCP2B Select the Mode: MIPI CSI1 or CCP2B .............................. 1249
6.5.3.8 Camera ISP CSI1/CCP2B Burst Settings ............................................................ 1249
6.5.3.9 Camera ISP CSI1/CCP2B Debug Mode ............................................................. 1249
6.5.3.10 Camera ISP CSI1/CCP2B Video Port ................................................................ 1249
6.5.3.11 Camera ISP CSI1/CCP2B Logical Channels ........................................................ 1250
6.5.3.12 Camera ISP CSI1/CCP2B Controls ................................................................... 1251
6.5.3.13 Camera ISP CSI1/CCP2B Region of Interest ....................................................... 1251
6.5.3.14 Camera ISP CSI1/CCP2B CRC ....................................................................... 1251
6.5.3.15 Camera ISP CSI1/CCP2B Destination Format ...................................................... 1251
6.5.3.16 Camera ISP CSI1/CCP2B Frame Acquisition ....................................................... 1251
6.5.3.17 Camera ISP CSI1/CCP2B Synchronization Codes ................................................. 1252
6.5.3.18 Camera ISP CSI1/CCP2B Status Data .............................................................. 1252
6.5.3.19 Camera ISP CSI1/CCP2B Pixel Data Region ....................................................... 1253
6.5.3.20 Camera ISP CSI1/CCP2B Memory Read Channel ................................................. 1255
6.5.3.20.1 Camera ISP CSI1/CCP2B Write Data From Sensor to Memory ............................. 1255
6.5.3.20.2 Camera ISP CSI1/CCP2B Read Data from Memory .......................................... 1255
6.5.4 Programming the CSI2 Receiver ............................................................................ 1256
6.5.4.1 Camera ISP CSI2 Enabling the Interface ............................................................ 1256
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6.5.4.2 Camera ISP CSI2 Reset Management ............................................................... 1256
6.5.4.3 Camera ISP CSI2 Enable Video/Picture Acquisition ............................................... 1257
6.5.4.4 Camera ISP CSI2 Disable Video/Picture Acquisition ............................................... 1258
6.5.4.5 Camera ISP CSI2 Capture a Finite Number of Frames ............................................ 1258
6.5.4.6 Camera ISP CSI2 Configure a Periodic Event During Frame Acquisition ....................... 1259
6.5.4.7 Camera ISP CSI2 Linking a Context to a Virtual Channel and a Data Type .................... 1259
6.5.4.8 Camera ISP CSI2 Progressive and Interleaved Frame Configuration ........................... 1261
6.5.5 Programming the Timing CTRL Module .................................................................... 1261
6.5.5.1 Camera ISP Timing CTRL Timing Generator ....................................................... 1261
6.5.5.2 Camera ISP Timing CTRL Camera-Control Signal Generator .................................... 1261
6.5.5.2.1 Camera ISP Timing CTRL Vertical Synchro-Based Control-Signal Generation or
Externally-Generated cam_global_reset ......................................................... 1262
6.5.5.2.2 Camera ISP Timing CTRL Internally-Generated cam_global_reset-Based Control-Signal
Generation ........................................................................................... 1262
6.5.5.2.3 Camera ISP Timing CTRL STROBE and PRESTROBE Signal Generation for Red-Eye
Removal .............................................................................................. 1263
6.5.6 Programming the CCDC ...................................................................................... 1264
6.5.6.1 Camera ISP CCDC Hardware Setup/Initialization .................................................. 1264
6.5.6.1.1 Camera ISP CCDC Reset Behavior .............................................................. 1264
6.5.6.1.2 Camera ISP CCDC Register Setup .............................................................. 1264
6.5.6.1.3 Camera ISP CCDC Pixel Selection (Framing) Register Dependencies ..................... 1266
6.5.6.2 Camera ISP CCDC Enable/Disable Hardware ...................................................... 1268
6.5.6.3 Camera ISP CCDC Events and Status Checking .................................................. 1268
6.5.6.3.1 Camera ISP CCDC Interrupts ..................................................................... 1268
6.5.6.3.2 Camera ISP CCDC CCDC_VD0_IRQ and CCDC_VD1_IRQ Interrupts .................... 1268
6.5.6.3.3 Camera ISP CCDC CCDC_VD2_IRQ Interrupt ................................................ 1269
6.5.6.3.4 Camera ISP CCDC Status Checking ............................................................ 1269
6.5.6.4 Camera ISP CCDC Register Accessibility During Frame Processing ........................... 1269
6.5.6.5 Camera ISP CCDC Interframe Operations .......................................................... 1270
6.5.6.6 Camera ISP CCDC Operations ....................................................................... 1270
6.5.6.6.1 Camera ISP CCDC Image-Sensor Configuration .............................................. 1270
6.5.6.6.2 Camera ISP CCDC Image-Signal Processing .................................................. 1273
6.5.6.7 Camera ISP CCDC Summary of Constraints ....................................................... 1280
6.5.7 Programming the Preview Engine ........................................................................... 1280
6.5.7.1 Camera ISP Preview Setup/Initialization ............................................................. 1280
6.5.7.1.1 Camera ISP Preview Reset Behavior ............................................................ 1280
6.5.7.1.2 Camera ISP Preview Register Setup ............................................................ 1280
6.5.7.1.3 Camera ISP Preview Table Setup ................................................................ 1282
6.5.7.2 Camera ISP Preview Enable/Disable Hardware .................................................... 1283
6.5.7.3 Camera ISP Preview Events and Status Checking ................................................. 1283
6.5.7.4 Camera ISP Preview Register Accessibility During Frame Processing .......................... 1283
6.5.7.5 Camera ISP Preview Interframe Operations ........................................................ 1284
6.5.7.6 Camera ISP Preview Summary of Constraints ...................................................... 1284
6.5.8 Programming the Resizer .................................................................................... 1285
6.5.8.1 Camera ISP Resizer Setup/Initialization ............................................................. 1285
6.5.8.1.1 Camera ISP Resizer Reset Behavior ............................................................ 1285
6.5.8.1.2 Camera ISP Resizer Register Setup ............................................................. 1285
6.5.8.2 Camera ISP Resizer Enable/Disable Hardware ..................................................... 1286
6.5.8.3 Camera ISP Resizer Events and Status Checking ................................................. 1286
6.5.8.4 Camera ISP Resizer Register Accessibility During Frame Processing .......................... 1287
6.5.8.5 Camera ISP Resizer Inter-Frame Operations ....................................................... 1287
6.5.8.5.1 Camera ISP Resizer Multiple Passes for Large Resizing Operations ....................... 1287
6.5.8.5.2 Camera ISP Resizer Processing Time Calculation ............................................ 1288
6.5.8.6 Camera ISP Resizer Summary of Constraints ...................................................... 1288
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6.5.9 Programming the H3A ........................................................................................ 1289
6.5.9.1 Camera ISP H3A Setup/Initialization ................................................................. 1289
6.5.9.1.1 Camera ISP H3A Reset Behavior ................................................................ 1290
6.5.9.1.2 Camera ISP H3A Register Setup ................................................................. 1290
6.5.9.2 Camera ISP H3A Enable/Disable Hardware ........................................................ 1291
6.5.9.3 Camera ISP H3A Event and Status Checking ...................................................... 1291
6.5.9.4 Camera ISP H3A Register Accessibility During Frame Processing .............................. 1291
6.5.9.5 Camera ISP H3A Interframe Operations ............................................................. 1292
6.5.9.6 Camera ISP H3A Summary of Constraints .......................................................... 1292
6.5.10 Programming the Histogram ................................................................................ 1292
6.5.10.1 Camera ISP Histogram Setup/Initialization .......................................................... 1292
6.5.10.1.1 Camera ISP Histogram Reset Behavior ......................................................... 1292
6.5.10.1.2 Camera ISP Histogram Reset of Histogram Output Memory ................................. 1292
6.5.10.1.3 Camera ISP Histogram Register Setup ......................................................... 1293
6.5.10.2 Camera ISP Histogram Enable/Disable Hardware ................................................. 1293
6.5.10.3 Camera ISP Histogram Event and Status Checking ............................................... 1293
6.5.10.4 Camera ISP Histogram Register Accessibility During Frame Processing ....................... 1294
6.5.10.5 Camera ISP Histogram Interframe Operations ...................................................... 1294
6.5.10.6 Camera ISP Histogram Summary of Constraints ................................................... 1295
6.5.11 Programming the Central-Resource SBL ................................................................. 1295
6.5.11.1 Camera ISP Central-Resource SBL Setup/Initialization ........................................... 1295
6.5.11.1.1 Camera ISP Central-Resource SBLReset Behavior ........................................... 1295
6.5.11.1.2 Camera ISP Central-Resource SBLRegister Setup ........................................... 1295
6.5.11.2 Camera ISP Central-Resource SBL Enable/Disable Hardware ................................... 1295
6.5.11.3 Camera ISP Central-Resource SBL Event and Status Checking ................................. 1295
6.5.11.4 Camera ISP Central-Resource SBL Register Accessibility During Frame Processing ........ 1297
6.5.11.5 Camera ISP Central-Resource SBL Camera ISP Bandwidth Adjustments ..................... 1297
6.5.11.5.1 Camera ISP Central-Resource SBL Input From CCDC Video-Port Interface .............. 1297
6.5.11.5.2 Camera ISP Central-Resource SBL Input From Memory ..................................... 1298
6.5.12 Programming the Circular Buffer ........................................................................... 1299
6.5.12.1 Camera ISP CBUFF Setup/Initialization ............................................................. 1299
6.5.12.2 Camera ISP CBUFF Reset Behavior ................................................................. 1299
6.5.12.3 Camera ISP CBUFF Register Setup ................................................................. 1299
6.5.12.4 Camera ISP CBUFF Event and status Checking ................................................... 1299
6.5.12.4.1 Camera ISP CBUFF Interrupts ................................................................... 1299
6.5.12.4.2 Camera ISP CBUFF Status Checking ........................................................... 1300
6.5.12.5 Camera ISP CBUFF Register Accessibility During Frame Processing .......................... 1300
6.5.12.6 Camera ISP CBUFF Operations ...................................................................... 1300
6.5.13 Programming the Camera ISP Software Reset .......................................................... 1300
6.6 Camera ISP Register Manual ......................................................................................... 1302
6.6.1 Camera ISP Instance Summary ............................................................................. 1302
6.6.1.1 Camera ISP Registers Summary ..................................................................... 1302
6.6.1.2 Camera ISP Register Description ..................................................................... 1303
6.6.2 Camera ISP CBUFF Registers .............................................................................. 1329
6.6.2.1 Camera ISP CBUFF Register Summary ............................................................. 1329
6.6.2.2 Camera ISP CBUF Register Description ............................................................. 1330
6.6.3 Camera ISP CCP2 Registers ................................................................................ 1340
6.6.3.1 Camera ISP CCP2 Register Summary ............................................................... 1340
6.6.3.2 Camera ISP CCP2 Register Description ............................................................. 1340
6.6.4 Camera ISP CCDC Registers ............................................................................... 1372
6.6.4.1 Camera ISP CCDC Register Summary .............................................................. 1372
6.6.4.2 Camera ISP CCDC Register Description ............................................................ 1373
6.6.5 Camera ISP HIST Registers ................................................................................. 1404
20 Contents SWPU177N–December 2009–Revised November 2010
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