Texas Instruments OMAP36 Series Product manual

OMAP™
Public Version
OMAP36xx Multimedia Device
Silicon Revision 1.x
Texas Instruments OMAP™ Family of Products
Version N
Technical Reference Manual
Literature Number: SWPU177N
December 2009–Revised November 2010

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Public Version
Contents
Preface .................................................................................................................................... 175
1 Introduction .................................................................................................................... 187
1.1 Overview .................................................................................................................. 188
1.2 Environment .............................................................................................................. 189
1.3 Description ................................................................................................................ 191
1.3.1 MPU Subsystem ................................................................................................ 191
1.3.2 IVA2.2 Subsystem .............................................................................................. 192
1.3.3 On-Chip Memory ................................................................................................ 193
1.3.4 External Memory Interfaces ................................................................................... 193
1.3.5 DMA Controllers ................................................................................................. 193
1.3.6 Multimedia ....................................................................................................... 194
1.3.7 Comprehensive Power Management ......................................................................... 195
1.3.8 Peripherals ....................................................................................................... 195
1.4 POP Concept ............................................................................................................. 197
1.5 OMAP36xx Family ....................................................................................................... 198
1.6 Device Identification ..................................................................................................... 200
2 Memory Mapping ............................................................................................................. 203
2.1 Introduction ............................................................................................................... 204
2.2 Global Memory Space Mapping ....................................................................................... 206
2.3 L3 and L4 Memory Space Mapping ................................................................................... 209
2.3.1 L3 Memory Space Mapping ................................................................................... 209
2.3.2 L4 Memory Space Mapping ................................................................................... 210
2.3.2.1 L4-Core Memory Space Mapping ...................................................................... 210
2.3.2.2 L4-Wakeup Memory Space Mapping .................................................................. 213
2.3.2.3 L4-Peripheral Memory Space Mapping ................................................................ 214
2.3.2.4 L4-Emulation Memory Space Mapping ................................................................ 215
2.3.3 Register Access Restrictions .................................................................................. 216
2.4 IVA2.2 Subsystem Memory Space Mapping ......................................................................... 218
2.4.1 IVA2.2 Subsystem Internal Memory and Cache Allocation ............................................... 218
2.4.1.1 IVA2.2 Subsystem Memory Hierarchy ................................................................. 218
2.4.1.2 IVA2.2 Cache Allocation ................................................................................. 219
2.4.2 DSP Access to L2 Memories .................................................................................. 220
2.4.2.1 DSP Access to L2 ROM ................................................................................. 220
2.4.2.2 DSP Access to L2 RAM ................................................................................. 220
2.4.3 DSP and EDMA Access to Memories and Peripherals .................................................... 220
2.4.4 L3 Interconnect View of the IVA2.2 Subsystem Memory Space ......................................... 221
2.4.5 DSP View of the IVA2.2 Subsystem Memory Space ....................................................... 221
2.4.6 EDMA View of the IVA2.2 Subsystem Memory Space .................................................... 223
3 Power, Reset, and Clock Management ................................................................................ 225
3.1 Introduction to Power Managements .................................................................................. 226
3.1.1 Goal of Power Management ................................................................................... 226
3.1.2 Power-Management Techniques ............................................................................. 226
3.1.2.1 Dynamic Voltage and Frequency Scaling ............................................................. 226
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3.1.2.2 SmartReflex Adaptive Voltage Scaling (AVS) ........................................................ 227
3.1.2.3 Dynamic Power Switching ............................................................................... 228
3.1.2.4 Standby Leakage Management ......................................................................... 228
3.1.2.5 DPS Versus SLM ......................................................................................... 229
3.1.2.6 Adaptive Body Bias (ABB) ............................................................................... 229
3.1.2.7 Combining Power-Management Techniques ......................................................... 229
3.1.3 Architectural Blocks for Power Management ................................................................ 230
3.1.3.1 Clock Domain ............................................................................................. 230
3.1.3.2 Power Domain ............................................................................................ 231
3.1.3.3 Voltage Domain ........................................................................................... 232
3.1.4 Device Power-Management Architecture .................................................................... 233
3.1.4.1 Module Interface and Functional Clocks ............................................................... 234
3.1.4.2 Autoidle Clock Control ................................................................................... 235
3.1.5 SmartReflex Voltage-Control Overview ...................................................................... 236
3.1.5.1 Manual SmartReflex Voltage Control .................................................................. 237
3.1.5.2 Automatic SmartReflex Voltage Control ............................................................... 238
3.2 PRCM Overview ......................................................................................................... 239
3.2.1 Introduction ...................................................................................................... 239
3.2.2 PRCM Features ................................................................................................. 241
3.3 PRCM Environment ...................................................................................................... 242
3.3.1 External Clock Signals ......................................................................................... 243
3.3.2 External Reset Signals ......................................................................................... 244
3.3.3 External Power Signals ........................................................................................ 245
3.4 PRCM Integration ........................................................................................................ 246
3.4.1 Power-Management Scheme, Reset, and Interrupt Requests ............................................ 249
3.4.1.1 Power Domain ............................................................................................ 249
3.4.1.2 Resets ...................................................................................................... 249
3.4.1.3 Interrupt Requests ........................................................................................ 250
3.5 PRCM Functional Description .......................................................................................... 251
3.5.1 PRCM Reset Manager Functional Description .............................................................. 251
3.5.1.1 Overview ................................................................................................... 251
3.5.1.2 General Characteristics of Reset Signals ............................................................. 251
3.5.1.2.1 Scope .................................................................................................. 252
3.5.1.2.2 Occurrence ............................................................................................ 252
3.5.1.2.3 Source Type .......................................................................................... 252
3.5.1.3 Reset Sources ............................................................................................ 252
3.5.1.3.1 Global Reset Sources ............................................................................... 253
3.5.1.3.2 Local Reset Sources ................................................................................. 254
3.5.1.4 Reset Distribution ......................................................................................... 255
3.5.1.5 Power Domain Reset Descriptions ..................................................................... 256
3.5.1.5.1 MPU Power Domain ................................................................................. 256
3.5.1.5.2 NEON Power Domain ............................................................................... 256
3.5.1.5.3 IVA2 Power Domain ................................................................................. 256
3.5.1.5.4 CORE Power Domain ............................................................................... 256
3.5.1.5.5 DSS Power Domain .................................................................................. 257
3.5.1.5.6 CAM Power Domain ................................................................................. 257
3.5.1.5.7 USBHOST Power Domain .......................................................................... 257
3.5.1.5.8 SGX Power Domain ................................................................................. 257
3.5.1.5.9 WKUP Power Domain ............................................................................... 257
3.5.1.5.10 PER Power Domain ................................................................................. 258
3.5.1.5.11 SmartReflex Power Domain ........................................................................ 258
3.5.1.5.12 DPLL Power Domains ............................................................................... 258
3.5.1.5.13 EFUSE Power Domain .............................................................................. 258
4Contents SWPU177N–December 2009–Revised November 2010
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3.5.1.5.14 BANDGAP Logic ..................................................................................... 259
3.5.1.5.15 External Warm Reset Assertion .................................................................... 259
3.5.1.6 Reset Logging ............................................................................................. 259
3.5.1.6.1 PRCM Reset Logging Mechanism ................................................................. 259
3.5.1.6.2 SCM Reset Logging ................................................................................. 260
3.5.1.7 Reset Management Overview ........................................................................... 260
3.5.1.8 Reset Summary ........................................................................................... 265
3.5.1.9 Reset Sequences ......................................................................................... 268
3.5.1.9.1 Power-Up Sequence ................................................................................. 268
3.5.1.9.2 Global Warm Reset Sequence ..................................................................... 270
3.5.1.9.3 IVA2.2 Subsystem Power-Up Sequence .......................................................... 272
3.5.1.9.4 IVA2 Software Reset Sequence .................................................................... 274
3.5.1.9.5 IVA2 Global Warm Reset Sequence .............................................................. 276
3.5.1.9.6 IVA2 Power Domain Wake-Up Cold Reset Sequence .......................................... 278
3.5.2 PRCM Power Manager Functional Description ............................................................. 281
3.5.2.1 Overview ................................................................................................... 281
3.5.2.1.1 Introduction ............................................................................................ 281
3.5.2.1.2 Device Partitioning ................................................................................... 282
3.5.2.1.3 Memory and Logic Power Management .......................................................... 284
3.5.2.1.4 Retention Till Access (RTA) Memory Feature .................................................... 284
3.5.2.1.5 Power Domain States ............................................................................... 285
3.5.2.1.6 Power State Transitions ............................................................................. 285
3.5.2.1.7 Device Power Modes ................................................................................ 286
3.5.2.1.8 Isolation Between Power Domains ................................................................ 286
3.5.2.2 Power Domain Implementation ......................................................................... 286
3.5.2.2.1 Device Power Domains .............................................................................. 286
3.5.2.2.2 Power Domain Memory Status ..................................................................... 288
3.5.2.2.3 Power Domain State Transition Rules ............................................................ 288
3.5.2.2.4 Power Domain Dependencies ...................................................................... 288
3.5.2.2.5 Power Domain Controls ............................................................................. 289
3.5.3 PRCM Clock Manager Functional Description .............................................................. 291
3.5.3.1 Overview ................................................................................................... 291
3.5.3.1.1 Interface and Functional Clocks .................................................................... 292
3.5.3.2 External Clock I/Os ....................................................................................... 293
3.5.3.2.1 External Clock Inputs ................................................................................ 293
3.5.3.2.2 External Clock Outputs .............................................................................. 294
3.5.3.2.3 Summary .............................................................................................. 294
3.5.3.3 Internal Clock Generation ............................................................................... 294
3.5.3.3.1 PRM .................................................................................................... 296
3.5.3.3.2 CM ..................................................................................................... 298
3.5.3.3.3 DPLLs .................................................................................................. 300
3.5.3.3.4 DPLL Clock Summary ............................................................................... 308
3.5.3.3.5 Summary .............................................................................................. 308
3.5.3.4 Clock Distribution ......................................................................................... 309
3.5.3.4.1 Power Domain Clock Distribution .................................................................. 309
3.5.3.4.2 Clock Distribution Summary ........................................................................ 323
3.5.3.5 External Clock Controls .................................................................................. 325
3.5.3.5.1 Clock Request (sys_clkreq) Control ............................................................... 325
3.5.3.5.2 System Clock Oscillator Control .................................................................... 326
3.5.3.5.3 External Output Clock1 (sys_clkout1) Control .................................................... 329
3.5.3.5.4 External Output Clock2 (sys_clkout2) Control .................................................... 329
3.5.3.6 DPLL Control .............................................................................................. 329
3.5.3.6.1 DPLL Multiplier and Divider Factors ............................................................... 329
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SWPU177N–December 2009–Revised November 2010 Contents
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3.5.3.6.2 DPLL Modes .......................................................................................... 329
3.5.3.6.3 DPLL Low-Power Mode ............................................................................. 331
3.5.3.6.4 DPLL Clock Path Power Down ..................................................................... 332
3.5.3.6.5 Recalibration .......................................................................................... 332
3.5.3.6.6 DPLL Programming Sequence ..................................................................... 333
3.5.3.7 Internal Clock Controls ................................................................................... 334
3.5.3.7.1 PRM Source-Clock Controls ........................................................................ 334
3.5.3.7.2 CM Source-Clock Controls .......................................................................... 336
3.5.3.7.3 Common Interface Clock Controls ................................................................. 338
3.5.3.7.4 DPLL Source-Clock Controls ....................................................................... 339
3.5.3.7.5 SGX Power Domain Clock Controls ............................................................... 340
3.5.3.7.6 CORE Power Domain Clock Controls ............................................................. 341
3.5.3.7.7 EFUSE Power Domain Clock Controls ............................................................ 343
3.5.3.7.8 DSS Power Domain Clock Controls ............................................................... 343
3.5.3.7.9 CAM Power Domain Clock Controls ............................................................... 344
3.5.3.7.10 USBHOST Power Domain Clock Controls ....................................................... 345
3.5.3.7.11 WKUP Power Domain Clock Controls ............................................................ 346
3.5.3.7.12 PER Power Domain Clock Controls ............................................................... 347
3.5.3.7.13 SMARTREFLEX Power Domain Clock Controls ................................................. 349
3.5.3.8 Clock Configurations ..................................................................................... 350
3.5.3.8.1 Processor Clock Configurations .................................................................... 350
3.5.3.8.2 Interface and Peripheral Functional Clock Configurations ...................................... 351
3.5.4 PRCM Idle and Wake-Up Management ..................................................................... 353
3.5.4.1 Overview ................................................................................................... 353
3.5.4.2 Sleep Transition ........................................................................................... 355
3.5.4.3 Wakeup .................................................................................................... 355
3.5.4.4 Device Wake-Up Events ................................................................................. 356
3.5.4.5 Sleep and Wake-Up Dependencies .................................................................... 361
3.5.4.5.1 Sleep Dependencies ................................................................................. 361
3.5.4.5.2 Wake-Up Dependencies ............................................................................ 363
3.5.4.6 USBHOST/USBTLL Save-and-Restore Management ............................................... 366
3.5.4.6.1 USBHOST SAR Sequences ........................................................................ 368
3.5.4.6.2 USB TLL SAR Sequences .......................................................................... 368
3.5.5 PRCM Interrupts ................................................................................................ 369
3.5.6 PRCM Voltage Management Functional Description ...................................................... 371
3.5.6.1 Overview ................................................................................................... 371
3.5.6.2 Voltage Domains .......................................................................................... 375
3.5.6.3 Voltage Domain Dependencies ......................................................................... 376
3.5.6.4 Voltage-Control Architecture ............................................................................ 377
3.5.6.5 VDD1 and VDD2 Control ................................................................................ 379
3.5.6.5.1 Direct Control With VMODE Signals ............................................................... 379
3.5.6.5.2 Direct Voltage Control With I2C Interface ......................................................... 380
3.5.6.5.3 Voltage Controller and Dedicated SmartReflex I2C Interface .................................. 380
3.5.6.5.4 SmartReflex Voltage Control ....................................................................... 380
3.5.6.6 Analog Cells, LDOs, and Level Shifter Controls ...................................................... 389
3.5.6.6.1 ABB LDOs Control ................................................................................... 389
3.5.6.6.2 SRAM Voltage Control .............................................................................. 390
3.5.6.6.3 Wake-Up and Emulation Voltage Control ......................................................... 390
3.5.7 PRCM Off-Mode Management ................................................................................ 391
3.5.7.1 Overview ................................................................................................... 391
3.5.7.2 Device Off-Mode Configuration ......................................................................... 391
3.5.7.2.1 Overview .............................................................................................. 391
3.5.7.2.2 I/O Wake-Up Mechanism ........................................................................... 392
6Contents SWPU177N–December 2009–Revised November 2010
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3.5.7.3 CORE Power Domain Off-Mode Sequences ......................................................... 393
3.5.7.3.1 Sleep Sequences (Transition From On to Retention/Off) ....................................... 393
3.5.7.3.2 Wake-Up Sequences (Transition From Retention/Off to On) .................................. 394
3.5.7.4 Device Off-Mode Sequences ............................................................................ 394
3.5.7.4.1 Sleep Sequences .................................................................................... 394
3.5.7.4.2 Wake-Up Sequences ................................................................................ 396
3.6 PRCM Basic Programming Model ..................................................................................... 397
3.6.1 Global Registers ................................................................................................ 397
3.6.1.1 Revision Information Registers ......................................................................... 397
3.6.1.2 PRCM Configuration Registers ......................................................................... 397
3.6.1.3 Interrupt Configuration Registers ....................................................................... 397
3.6.1.3.1 MPU Interrupt Event Sources ...................................................................... 398
3.6.1.3.2 MPU Interrupt Registers ............................................................................. 399
3.6.1.3.3 IVA2.2 Interrupt Event Sources .................................................................... 399
3.6.1.3.4 IVA2 Interrupt Registers ............................................................................. 399
3.6.1.4 Event Generator Control Registers ..................................................................... 399
3.6.1.5 Output Signal Polarity Control Registers .............................................................. 400
3.6.1.5.1 CM_POLCTRL (CM Polarity Control Register) ................................................... 400
3.6.1.5.2 PRM_POLCTRL (PRM Polarity Control Register) ............................................... 401
3.6.1.6 SRAM Precharge Time Control Register .............................................................. 402
3.6.1.6.1 PRM_SRAM_PCHARGE (Voltage SRAM Precharge Counter Register) ..................... 402
3.6.2 Clock Management Registers ................................................................................. 402
3.6.2.1 System Clock Control Registers ........................................................................ 402
3.6.2.1.1 PRM_CLKSRC_CTRL (Clock Source Control Register) ........................................ 402
3.6.2.1.2 PRM_CLKSETUP (Source-Clock Setup Register) .............................................. 402
3.6.2.1.3 PRM_CLKSEL (Source-Clock Selection Register) .............................................. 402
3.6.2.2 External Clock Output Control Registers .............................................................. 402
3.6.2.2.1 PRM_CLKOUT_CTRL (Clock Out Control Register) ............................................ 402
3.6.2.2.2 CM_CLKOUT_CTRL (Clock Out Control Register) .............................................. 403
3.6.2.3 DPLL Clock Control Registers .......................................................................... 403
3.6.2.3.1 CM_CLKSELn_PLL_ <processor_name> (Processor DPLL Clock Selection Register) .... 403
3.6.2.3.2 CM_CLKSELn_PLL (DPLL Clock Selection Register) .......................................... 403
3.6.2.3.3 CM_CLKEN_PLL_<processor_name> (Processor DPLL Clock Enable Register) .......... 404
3.6.2.3.4 CM_CLKEN_PLL (DPLL Enable Register) ....................................................... 404
3.6.2.3.5 CM_AUTOIDLE_PLL_ <processor_name> (Processor DPLL Autoidle Register) ........... 404
3.6.2.3.6 CM_AUTOIDLE_PLL (DPLL Autoidle Register) ................................................. 405
3.6.2.3.7 CM_AUTOIDLE1_PLL (DPLL5 Autoidle Register) .............................................. 405
3.6.2.3.8 CM_IDLEST_CKGEN (Source-Clock Idle-Status Register) .................................... 405
3.6.2.3.9 CM_IDLEST2_CKGEN (DPLL5 Source-Clock Idle-Status Register) .......................... 405
3.6.2.3.10 CM_IDLEST_PLL_ <processor_name> (Processor DPLL Idle-Status Register) ............ 405
3.6.2.4 Power-Domain Clock Control Registers ............................................................... 406
3.6.2.4.1 CM_CLKSEL_ <domain_name> (Clock Select Register) ....................................... 406
3.6.2.4.2 CM_FCLKEN_ <domain_name> (Functional Clock Enable Register) ........................ 407
3.6.2.4.3 CM_ICLKEN_ <domain_name> (Interface Clock Enable Register) ........................... 407
3.6.2.4.4 CM_AUTOIDLE_ <domain_name> (Autoidle Register) ......................................... 408
3.6.2.4.5 CM_IDLEST_ <domain_name> (Idle-Status Register) .......................................... 408
3.6.2.4.6 CM_CLKSTCTRL_ <domain_name> (Clock State Control Register) ......................... 409
3.6.2.4.7 CM_CLKSTST_ <domain_name> (Clock State Status Register) .............................. 410
3.6.2.4.8 CM_SLEEPDEP_ <domain_name> (Sleep Dependency Control Register) ................. 410
3.6.2.5 Domain Wake-Up Control Registers ................................................................... 411
3.6.2.5.1 PM_WKEN_ <domain_name> (Wake-Up Enable Register) .................................... 411
3.6.2.5.2 PM_WKST_ <domain_name> (Wake-Up Status Register) ..................................... 411
3.6.2.5.3 PM_WKDEP_ <domain_name> (Wake-Up Dependency Register) ........................... 412
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SWPU177N–December 2009–Revised November 2010 Contents
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3.6.2.5.4 PM_ <processor_name> GRPSEL_ <domain_name> (Processor Group Selection Register)
.......................................................................................................... 413
3.6.3 Reset Management Registers ................................................................................. 413
3.6.3.1 Reset Control .............................................................................................. 413
3.6.3.1.1 PRM_RSTTIME (Reset Time Register) ........................................................... 413
3.6.3.1.2 RM_RSTCTRL_ <domain_name> (Reset Control Register) ................................... 414
3.6.3.1.3 RM_RSTST_ <domain_name> (Reset Status Register) ........................................ 414
3.6.4 Power Management Registers ................................................................................ 416
3.6.4.1 PM_PWSTCTRL_ <domain_name> (Power State Control Register) .............................. 416
3.6.4.2 PM_PWSTST_ <domain_name> (Power State Status Register) .................................. 418
3.6.4.3 PM_PREPWSTST_ <domain_name> (Previous Power State Status Register) ................. 419
3.6.5 Voltage Management Registers ............................................................................... 419
3.6.5.1 External Voltage Control Register Descriptions ...................................................... 419
3.6.5.1.1 PRM_VOLTSETUP (Voltage Setup Time Register) ............................................. 419
3.6.5.1.2 PRM_VOLTOFFSET (Voltage Offset Register) .................................................. 420
3.6.5.1.3 PRM_VOLTCTRL (Voltage Source Control Register) ........................................... 421
3.6.5.2 Voltage Controller Registers ............................................................................ 421
3.6.5.2.1 PRM_VC_SMPS_SA (Voltage Controller SMPS Slave Address Register) .................. 422
3.6.5.2.2 PRM_VC_SMPS_VOL_RA (Voltage Controller SMPS Voltage Register Address Register)
.......................................................................................................... 422
3.6.5.2.3 PRM_VC_SMPS_CMD_RA (Voltage Controller SMPS Command Register Address Register)
.......................................................................................................... 422
3.6.5.2.4 PRM_VC_CMD_VAL_0 and PRM_VC_CMD_VAL_1 (Voltage Controller Command and
Voltage Value Register 0 and 1) ................................................................... 422
3.6.5.2.5 PRM_VC_CH_CONF (Voltage Controller Channel Configuration Register) ................. 422
3.6.5.2.6 PRM_VC_I2C_CFG (Voltage Controller I2C Interface Configuration Register) .............. 422
3.6.5.2.7 PRM_VC_BYPASS_VAL (Voltage Controller Bypass Command Register) .................. 423
3.6.5.3 Voltage Processor Registers ............................................................................ 423
3.6.5.3.1 PRM_VP_CONFIG (Voltage Processor Configuration Register) .............................. 423
3.6.5.3.2 PRM_VP_VSTEPMIN (Voltage Processor Minimum Voltage Step) ........................... 423
3.6.5.3.3 PRM_VP_VSTEPMAX (Voltage Processor Maximum Voltage Step) ......................... 423
3.6.5.3.4 PRM_VP_VLIMITTO (Voltage Processor Voltage Limit and Time-Out) ...................... 424
3.6.5.3.5 PRM_VP_VOLTAGE (Voltage Processor Voltage Register) ................................... 424
3.6.5.3.6 PRM_VP_STATUS (Voltage Processor Status Register) ...................................... 424
3.6.6 Generic Programming Examples ............................................................................. 424
3.6.6.1 Clock Control .............................................................................................. 424
3.6.6.1.1 Enabling and Disabling the Functional Clocks ................................................... 424
3.6.6.1.2 Enabling and Disabling the Interface Clocks ..................................................... 426
3.6.6.1.3 Enabling and Disabling the Inactive State ........................................................ 427
3.6.6.1.4 Processor Clock Control ............................................................................ 428
3.6.6.2 Reset Management ....................................................................................... 431
3.6.6.3 Wake-Up Control ......................................................................................... 431
3.6.6.4 SmartReflex Module Initialization Basic Programming Model ...................................... 432
3.6.6.5 Voltage Processor Initialization Basic Programming Model ......................................... 435
3.6.6.6 Voltage Controller Initialization Basic Programming Model ......................................... 439
3.6.6.7 Changing OPP Using the SmartReflex Module ....................................................... 442
3.6.6.8 Changing OPP Using Only the Voltage Processor Module ......................................... 444
3.6.6.9 Event Generator Programming Examples ............................................................. 446
3.7 PRCM Use Cases and Tips ............................................................................................ 447
3.7.1 DVFS Using Device SmartReflex With TWL5030 Power IC .............................................. 447
3.7.1.1 Device DVFS Support Architecture .................................................................... 447
3.7.1.2 TWL5030 DVFS Support Architecture ................................................................. 448
3.7.1.2.1 SMPS .................................................................................................. 448
3.7.1.2.2 I2C Interface ........................................................................................... 449
8Contents SWPU177N–December 2009–Revised November 2010
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3.7.1.3 DVFS Using SmartReflex ................................................................................ 450
3.7.1.3.1 Device SmartReflex Initialization ................................................................... 451
3.7.1.3.2 Switch VDD1 OPPs .................................................................................. 453
3.7.1.3.3 Switch VDD2 OPPs .................................................................................. 454
3.7.2 Voltage Control Using VMODE ............................................................................... 456
3.7.2.1 Introduction ................................................................................................ 456
3.7.2.2 Programming Sequence ................................................................................. 457
3.7.2.2.1 Initialization Procedure .............................................................................. 457
3.7.2.2.2 VMODE Signals Toggling ........................................................................... 457
3.7.2.2.3 Summary Flow Chart ................................................................................ 458
3.8 PRCM Register Manual ................................................................................................. 459
3.8.1 CM Module Registers .......................................................................................... 459
3.8.1.1 CM Instance Summary ................................................................................... 459
3.8.1.2 IVA2_CM Registers ...................................................................................... 459
3.8.1.2.1 IVA2_CM Register Summary ....................................................................... 459
3.8.1.2.2 IVA2_CM Registers .................................................................................. 460
3.8.1.3 OCP_System_Reg_CM Registers ..................................................................... 466
3.8.1.3.1 OCP_System_Reg_CM Register Summary ...................................................... 466
3.8.1.3.2 OCP_System_Reg_CM Registers ................................................................. 466
3.8.1.4 MPU_CM Registers ...................................................................................... 467
3.8.1.4.1 MPU_CM Register Summary ....................................................................... 467
3.8.1.4.2 MPU_CM Registers .................................................................................. 467
3.8.1.5 CORE_CM Registers .................................................................................... 473
3.8.1.5.1 CORE_CM Register Summary ..................................................................... 473
3.8.1.5.2 CORE_CM Registers ................................................................................ 474
3.8.1.6 SGX_CM Registers ....................................................................................... 487
3.8.1.6.1 SGX_CM Register Summary ....................................................................... 487
3.8.1.6.2 SGX_CM Registers .................................................................................. 488
3.8.1.7 WKUP_CM Registers .................................................................................... 492
3.8.1.7.1 WKUP_CM Register Summary ..................................................................... 492
3.8.1.7.2 WKUP_CM Registers ................................................................................ 492
3.8.1.8 Clock_Control_Reg_CM Registers ..................................................................... 497
3.8.1.8.1 Clock_Control_Reg_CM Register Summary ..................................................... 497
3.8.1.8.2 Clock_Control_Reg_CM Registers ................................................................ 498
3.8.1.9 DSS_CM Registers ....................................................................................... 510
3.8.1.9.1 DSS_CM Register Summary ....................................................................... 510
3.8.1.9.2 DSS_CM Registers .................................................................................. 510
3.8.1.10 CAM_CM Registers ...................................................................................... 517
3.8.1.10.1 CAM_CM Register Summary ....................................................................... 517
3.8.1.10.2 CAM_CM Registers .................................................................................. 518
3.8.1.11 PER_CM Registers ....................................................................................... 523
3.8.1.11.1 PER_CM Register Summary ....................................................................... 523
3.8.1.11.2 PER_CM Registers .................................................................................. 524
3.8.1.12 EMU_CM Registers ...................................................................................... 534
3.8.1.12.1 EMU_CM Register Summary ....................................................................... 534
3.8.1.12.2 EMU_CM Registers .................................................................................. 535
3.8.1.13 Global_Reg_CM Registers .............................................................................. 540
3.8.1.13.1 Global_Reg_CM Register Summary .............................................................. 540
3.8.1.13.2 Global_Reg_CM Registers ......................................................................... 540
3.8.1.14 NEON_CM Registers .................................................................................... 541
3.8.1.14.1 NEON_CM Register Summary ..................................................................... 541
3.8.1.14.2 NEON_CM Registers ................................................................................ 541
3.8.1.15 USBHOST_CM Registers ............................................................................... 543
9
SWPU177N–December 2009–Revised November 2010 Contents
Copyright © 2009–2010, Texas Instruments Incorporated

Public Version
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3.8.1.15.1 USBHOST_CM Register Summary ................................................................ 543
3.8.1.15.2 USBHOST_CM Registers ........................................................................... 543
3.8.2 PRM Module Registers ......................................................................................... 548
3.8.2.1 PRM Instance Summary ................................................................................. 548
3.8.2.2 IVA2_PRM Registers ..................................................................................... 548
3.8.2.2.1 IVA2_PRM Register Summary ..................................................................... 548
3.8.2.2.2 IVA2_PRM Registers ................................................................................ 549
3.8.2.3 OCP_System_Reg_PRM Registers .................................................................... 559
3.8.2.3.1 OCP_System_Reg PRM Register Summary ..................................................... 559
3.8.2.3.2 OCP_System_Reg_PRM Registers ............................................................... 559
3.8.2.4 MPU_PRM Registers Registers ........................................................................ 568
3.8.2.4.1 MPU_PRM Registers Register Summary ......................................................... 568
3.8.2.4.2 MPU_PRM Registers ................................................................................ 568
3.8.2.5 CORE_PRM Registers ................................................................................... 575
3.8.2.5.1 CORE_PRM Register Summary ................................................................... 575
3.8.2.5.2 CORE_PRM Registers .............................................................................. 576
3.8.2.6 SGX_PRM Registers ..................................................................................... 591
3.8.2.6.1 SGX_PRM Register Summary ..................................................................... 591
3.8.2.6.2 SGX_PRM Registers ................................................................................ 592
3.8.2.7 WKUP_PRM Registers .................................................................................. 595
3.8.2.7.1 WKUP_PRM Register Summary ................................................................... 595
3.8.2.7.2 WKUP_PRM Registers .............................................................................. 596
3.8.2.8 Clock_Control_Reg_PRM Registers ................................................................... 600
3.8.2.8.1 Clock_Control_Reg_PRM Register Summary .................................................... 600
3.8.2.8.2 Clock_Control_Reg_PRM Registers ............................................................... 601
3.8.2.9 DSS_PRM Registers ..................................................................................... 602
3.8.2.9.1 DSS_PRM Register Summary ..................................................................... 602
3.8.2.9.2 DSS_PRM Registers ................................................................................ 602
3.8.2.10 CAM_PRM Registers .................................................................................... 607
3.8.2.10.1 CAM_PRM Registers ................................................................................ 607
3.8.2.10.2 CAM_PRM Registers ................................................................................ 607
3.8.2.11 PER_PRM Registers ..................................................................................... 611
3.8.2.11.1 PER_PRM Register Summary ..................................................................... 611
3.8.2.11.2 PER_PRM Registers ................................................................................ 611
3.8.2.12 EMU_PRM Registers .................................................................................... 624
3.8.2.12.1 EMU_PRM Register Summary ..................................................................... 624
3.8.2.12.2 EMU_PRM Registers ................................................................................ 624
3.8.2.13 Global_Reg_PRM Registers ............................................................................ 626
3.8.2.13.1 Global_Reg_PRM Register Summary ............................................................. 626
3.8.2.13.2 Global_Reg_PRM Registers ........................................................................ 627
3.8.2.14 NEON_PRM Registers ................................................................................... 650
3.8.2.14.1 NEON_PRM Register Summary ................................................................... 650
3.8.2.14.2 NEON_PRM Registers .............................................................................. 651
3.8.2.15 USBHOST_PRM Registers ............................................................................. 654
3.8.2.15.1 USBHOST_PRM Register Summary .............................................................. 654
3.8.2.15.2 USBHOST_PRM Registers ......................................................................... 655
3.8.3 SR Registers ..................................................................................................... 661
3.8.3.1 SR Instance Summary ................................................................................... 661
3.8.3.2 SR Registers .............................................................................................. 661
3.8.3.2.1 SR Register Summary ............................................................................... 661
3.8.3.2.2 SR Registers .......................................................................................... 662
4 MPU Subsystem .............................................................................................................. 675
4.1 MPU Subsystem Overview ............................................................................................. 676
10 Contents SWPU177N–December 2009–Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated