Texas Instruments TPS65910 EVM User manual

TPS65910 User Guide for OMAPL-137, OMAPL-
138, and TMS320C674x Family of Processors
User's Guide
Literature Number: SWCU071B
December 2010–Revised October 2015

Contents
1 Introduction......................................................................................................................... 4
2 Platform Connection............................................................................................................. 5
3 Power-Up Sequencing .......................................................................................................... 7
3.1 Power-Up Sequence for OMAPL-138 and TMS320C6742/6/8 Processors...................................... 7
3.2 Power-Up Sequence for OMAPL-137 Processor .................................................................... 7
3.3 Power-Up Sequence for TPS65910 ................................................................................... 8
4 Getting Started With TPS65910 and OMAPL-137, OMAPL-138, and TMS320C6742/6/8
Processors........................................................................................................................ 10
4.1 First Initialization........................................................................................................ 10
4.2 Event Management Through Interrupts.............................................................................. 11
Revision History.......................................................................................................................... 13
2Table of Contents SWCU071B–December 2010–Revised October 2015
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List of Figures
1 OMAPL-137 Power Supply Connections With TPS65910 ............................................................. 5
2 OMAPL-138, TMS320C6742/6/8 Power Connections With TPS65910 .............................................. 6
3 Power-Up Timing Diagram ................................................................................................. 9
List of Tables
1 Power Rail Requirements for OMAPL-138, TMS320C6742/6/8....................................................... 7
2 Power Rail Requirements for OMAPL-137............................................................................... 7
3 Power-Up Sequence for TPS65910....................................................................................... 8
4 EEPROM Configuration for TPS65910 ................................................................................... 9
3
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User's Guide
SWCU071B–December 2010–Revised October 2015
TPS65910 User Guide For OMAPL-137, OMAPL-138, and
TMS320C674x Family of Processors
This user's guide can be used as a reference for connectivity between the TPS65910 power-management
integrated circuit (PMIC) and TI OMAPL, TMS320C674x processors.
1 Introduction
This user's guide can be used as a reference for connectivity between the TPS65910 PMIC and TI
OMAPL, TMS320C674x processors. This user guide does not provide details about the power resources
or the functionality of the device. For such information, refer to the full specification document, TPS65910
Data Manual.
4TPS65910 User Guide For OMAPL-137, OMAPL-138, and TMS320C674x SWCU071B–December 2010–Revised October 2015
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10 Fm
VFB2
SW2
VFBIO
SWIO
2.2 Fm
VDIG2
VIO
1000 mA
VCC1
VBAT
10 Fm
VDIG2
300 mA
VDIG1
300 mA
OMAPL-137
BOOT0
BOOT1
VFB1
2.2 Hm
SW1
VDD1
1500 mA 10 Fm
TPS65910
VCC2
VCCIO
VDIG1 RTC_CVDD
PowerPadä
VDDIO
VAUX2
VAUX2
300 mA
VAUX1
300 mA
VAUX1
VMMC
VMMC
300 mA
VAUX33
150 mA
VAUX33
VPLL
VPLL
50 mA
VDAC
150 mA
VDAC
VRTC
VRTC
20 mA
VCC3
4.7 Fm
VCC4
VCC5
VCC6
VCC7
VBACKUP
5–2000 mF
OSC32KIN
OSC32KOUT
VRTC
12 pF
VREF
REFGND
100 nF
GND2
GND1
GNDIO
I2C0_SCL
SCL
I2C0_SDA
4.7 K
VIO
SDA
INT1
PWRON
NRESPWRON RESET
VBAT
GPIO_CKSYNC
(available)
TESTV
(not connected)
SW3
VFB3
VDD3
100 mA
10 K
0.6 1.5 V, DVS
12.5-m V step,
Default ON 1.2 V
–
Default ON 1.8 V
0.6 1.5 V, DVS
12.5-m V step,
Default ON 1.2 V
–
Default ON 1.2 V
Default ON 1.2 V
Default ON 3.3 V
Default ON 3.3 V
Default ON 1.8 V
Default ON 1.8 V
Always-ON 1.8 V
Default ON 1.8 V
1.2/1.5/1.8/2.7 V
1.0/1.1/1.2/1.8 V
1.8/2.5/2.8/2.85 V
1.8/2.8/2.9/3.3 V
1.8/2.0/2.8/3.3 V
1.8/2.8/3.0/3.3 V
1.8/2.6/2.8/2.85 V
1.0/1.1/1.8/2.5 V
CLK32KOUT
VDD2
1500 mA
DVDD,
USB0_VDDA33,
USB1_VDDA33
RTC_XI
PWRHOLD
VIO
CVDD
USB0_VDDA18,
USB1_VDDA18
OSC
MMC
Audio IC
Available
4.7 HmVDD3 (for HDMI or OTG)
VBAT
(Typical 3.8 V)
10 Fm
10 Fm
VDD3 is a boost supplying 5 V.
If VBAT is 5 V then this will not
be useful.
PLL0_VDDA,
RVDD
IO/LPDDR
Available
VDDIO
VIO
GPIOx
GPIOx
GPIOx
SCLSR_EN1
SDASR_EN2
SWCU071-001
2.2 Hm
2.2 Hm
10 Fm
2.2 Fm
2.2 Fm
2.2 Fm
2.2 Fm
2.2 Fm
2.2 Fm
Default ON 3.3 V
2.2 Fm
2.2 Fm
4.7 K
10 Fm
10 Fm
4.7 Fm
4.7 Fm
4.7 Fm
4.7 Fm
12 pF
www.ti.com Platform Connection
2 Platform Connection
Figure 1. OMAPL-137 Power Supply Connections With TPS65910
5
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SWCU071-002
VFB2
2.2 Hm
SW2
10 mF
VFBIO
SWIO
2.2 Fm
VDIG2
VIO
1000 mA
VCC1
VBAT
10 Fm
VDIG2
300 mA
VDIG1
300 mA
OMAPL-138
BOOT0
BOOT1
VFB1
2.2 Hm
SW1
VDD1
1500 mA
TPS65910
VCC2
VCCIO
VDIG1
RTC_CVDD
PowerPadä
VDDIO
VAUX2
VAUX2
300 mA
VAUX1
300 mA
VAUX1
VMMC
VMMC
300 mA
VAUX33
150 mA
VAUX33
VPLL
VPLL
50 mA
VDAC
150 mA
VDAC
VRTC
VRTC
20 mA
VCC3
4.7 Fm
VCC4
VCC5
VCC6
VCC7
VBACKUP
5–2000 mF
OSC32KIN
OSC32KOUT
VRTC
12 pF
12 pF
VREF
REFGND
100 nF
GND2
GND1
GNDIO
I2C0_SCL
SCL I2C0_SDA
4.7 K
VIO
SDA
INT1
PWRON
NRESPWRON RESET
VBAT
GPIO_CKSYNC
(available)
TESTV
(not connected)
SW3
VFB3
VDD3
100 mA
10 K
0.6 1.5 V, DVS
12.5-mV step,
Default ON 1.2 V
–
Default ON 1.8 V
0.6 1.5 V, DVS
12.5-mV step,
Default ON 1.2 V
–
Default ON 1.2 V
Default ON 1.2 V
Default ON 3.3 V
Default ON 3.3 V
Default ON 3.3 V
Default ON 1.8 V
Default ON 1.8 V
Always-ON 1.8 V
Default ON 1.8 V
1.2/1.5/1.8/2.7 V
1.0/1.1/1.2/1.8 V
1.8/2.5/2.8/2.85 V
1.8/2.8/2.9/3.3 V
1.8/2.0/2.8/3.3 V
1.8/2.8/3.0/3.3 V
1.8/2.6/2.8/2.85 V
1.0/1.1/1.8/2.5 V
CLK32KOUT
VDD2
1500 mA
Accelerometer/
TS
USB0_VDDA33,
USB1_VDDA33
RTC_XI
PWRHOLD
VIO
CVDD
USB0_VDDA18,
USB1_VDDA18,
DDR_DVDD18,
SATA_VDDR,
DVDD18
OSC
Audio IC
Available
4.7 HmVDD3 (for HDMI or OTG)
VBAT
(Typical 3.8 V)
10 mF
VDD3 is a boost supplying 5 V.
If VBAT is 5 V then this will not
be useful.
RVDD,
PLL0_VDDA,
PLL1_VDDA,
SATA_VDD,
USB_CVDD,
USB0_VDDA12
DVDD3318_A, (see note)
DVDD3318_B,
DVDD3318_C
Available
VDDIO
VIO
GPIOx
GPIOx
GPIOx
SCLSR_EN1
SDASR_EN2
10 Fm
10 Fm
4.7 Fm
4.7 Fm
4.7 Fm
4.7 Fm
10 mF
2.2 Hm
2.2 Fm
2.2 Fm
2.2 Fm
10 mF
10 mF
2.2 Fm
2.2 Fm
2.2 Fm
2.2 Fm
2.2 Fm
4.7 K
Platform Connection www.ti.com
NOTE: If only 1.8 V operation is required, then these domains can be merged with 1.8 V on VIO.
Figure 2. OMAPL-138, TMS320C6742/6/8 Power Connections With TPS65910
At power up, the maximum current capability (default setting) of the DCDC converters is as follows:
6TPS65910 User Guide For OMAPL-137, OMAPL-138, and TMS320C674x SWCU071B–December 2010–Revised October 2015
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• VIO(max) = 500 mA
• VDD1(max) = 1000 mA
• VDD2(max) = 1000 mA
To have the maximum current capability, the user must program the following register bits:
• VIO_REG[ILMAX] = b01 for 1 A
• VDD1_REG[ILMAX] = b1 for 1.5 A
• VDD2_REG[ILMAX] = b1 for 1.5 A
3 Power-Up Sequencing
3.1 Power-Up Sequence for OMAPL-138 and TMS320C6742/6/8 Processors
The following sections show the power-up sequence requirement for OMAPL-138 and TMS320C6742/6/8
processors. To power on the system, the user must press and release the PWRON switch (generating a
negative pulse). The BOOT pads on the TPS65910 must be connected as follows:
• BOOT0 = 0
• BOOT1 = 1
Table 1 lists the power rail requirements for OMAPL-138, TMS320C6742/6/8.
Table 1. Power Rail Requirements for OMAPL-138, TMS320C6742/6/8
Power Domain Pin Name Imax (mA) Voltage (V) Sequence
I/O RTC_CVDD 1 1.2 1(1)
Core CVDD(2) 600 1.0/1.1/1.2 2
I/O RVDD, PLL0_VDDA, PLL1_VDDA, SATA_VDD, 200 1.2 3
USB_CVDD, USB0_VDDA12
I/O USB0_VDDA18, USB1_VDDA18, DDR_DVDD18, 180 1.8 4
SATA_VDDR, DVDD18
I/O USB0_VDDA33, USB1_VDDA33(3)(4) 24 3.3 5
I/O DVDD3318_A, DVDD3318_B, DVDD3318_C 90(5) 3.3 5
(1) If RTC is not used/maintained on a separate supply, it can be included in the STATIC12 (fixed 1.2 V) group.
(2) If using CVDD at fixed 1.2 V, all 1.2-V rails may be combined. CVDD can support 1.3 V; in this case SMPS (VDD1) supplying
CVDD core can be set to 1.3-V after initial power up.
(3) If 1.8-V LVCMOS is used, power rails up with the 1.8-V rails. If 3.3-V LVCMOS is used, power it up with the ANALOG33 rails
(VDDA33_USB0/1).
(4) There is no specific required voltage ramp rate for any of the supplies LVCMOS33 (USB0_VDDA33, USB1_VDDA33) that
never exceeds STATIC18 by more than 2 V.
(5) If DVDD3318_A, B, and C are powered independently, maximum power for each rail will be 1/3 the above maximum power.
These rails can be connected independently to 1.8 or 3.3 V.
3.2 Power-Up Sequence for OMAPL-137 Processor
Table 2 lists the power rail requirements for OMAPL-137.
Table 2. Power Rail Requirements for OMAPL-137
Power Domain Pin Name Imax (mA) Voltage (V)(2) Sequence
Core RTC_CVDD(1) 0.1 1.2 1
CVDD 600 1.2 2
PLL0_VDDA, RVDD 60 1.2 3
I/O USB0_VDDA18, USB1_VDDA18 50 1.8 5
I/O DVDD, USB0VDDA33, USB1_VDDA33 115 3.3 4
7
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(1) RTC_CVDD can be combined with PLL and RAM 1.2-V supplies if desired to turn off RTC when device is off. Otherwise, power
RTC_CVDD separately with a dedicated power source.
(2) Sequencing 1.2-V supplies:
(a) RTC (RTC_CVDD) may be powered from an external device (such as a battery) before all other supplies are applied. If the
RTC is not used, RTC_CVDD must be connected to CVDD.
(b) Group 2a: CVDD core logic supply. CVDD can support 1.3 V, in this case SMPS (VDD1) supplying CVDD core can be set
to 1.3 V after initial power up.
(c) Group 2b: Other 1.2-V logic supplies (RVDD, PLL0_VDDA). Groups 2a and 2b may be powered up together or 2a first
followed by 2b.
NOTE: To correctly power on the device, the PWRHOLD signal must be high after PWRON is
pressed. In this configuration the PWRHOLD signal on TPS65910 is connected to VIO.
PWRHOLD transitions to high when VIO powers up.
3.3 Power-Up Sequence for TPS65910
To satisfy the power-up requirements for the OMAPL-138 and TMS320C6742/4/6 processorsprocessor,
the TPS65910 powers up with the default sequence when in the EEPROM boot mode configuration
(BOOT0 = 0 and BOOT1 = 1) (see Table 3). The correct power-up sequence is configured in the
EEPROM (factory programmable only).
Apart from the main power rails required by the processors, all other rails are also powered up at initial
power up to support other system peripherals.
Figure 3 shows a typical power-up timing diagram.
Table 3 shows the power-up sequence.
Table 3. Power-Up Sequence for TPS65910
TPS65910 Power Rail Voltage (V) Sequence Number Delay (ms)
PWRON(1) – –
VDIG1 1.2 1 2
VDD1 1.2 2 2
VDD2 1.2 3 2
VIO 1.8 4 2
VDIG2 1.2 4 0
VAUX33 3.3 5 2
VMMC 3.3 5 0
VAUX1 1.8 6 2
VAUX2 3.3 6 0
VDAC 1.8 7 2
VPLL 1.8 7 0
(1) The PWRON signal is the start-on event. All timings listed are with respect to the previous event.
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SWCU071-003
PWRON button
VDD_RTC/ VRTC 1.8 V
CLK32KOUT TPS65910 internal clock 32 kHz released to processor
VDIG1 1.2 V
VDD1 1.2 V
VDD2 1.2 V
VIO 1.8 V
VDIG2 1.2 V
VAUX33 3.3 V
VMMC 3.3 V
VAUX1 3.3 V
VAUX2 3.3 V
VDAC 1.8 V
VPLL 1.8 V
Event: 1 2 3
Time slot (2 ms between slot): 0 1 2 3 4 5 6 7
Event description: 1 PWRON button press falling edge
2 Valid press after debounce
3 First step of power-up sequence available for DCDC, LDO activation. Time slot 0 is for internal use.
Note: PWRON press must be maintained until PWRHOLD acknowledge, or, for shorter PWRON press,
PWRHOLD must go high within 984 ms of valid PWRON press (event 2). To ensure this, PWRHOLD is tied to VIO.
www.ti.com Power-Up Sequencing
Figure 3. Power-Up Timing Diagram
Table 4. EEPROM Configuration for TPS65910
Register Bit Description Option Selected
VDD1_OP_REG SEL VDD1 voltage level selection for boot 1.2 V
VDD1_REG VGAIN_SEL VDD1 gain selection, x1 or x2 x1
EEPROM VDD1 time slot selection 2
DCDCCTRL_REG VDD1_PSKIP VDD1 pulse skip mode enable Skip enabled
VDD2_OP_REG / SEL VDD2 voltage level selection for boot 1.2 V
VDD2_SR_REG
VDD2_REG VGAIN_SEL VDD2 gain selection, x1 or x3 x1
EEPROM VDD2 time slot selection 3
DCDCCTRL_REG VDD2_PSKIP VDD2 pulse skip mode enable Skip enabled
VIO_REG SEL VIO voltage selection 1.8 V
EEPROM VIO time slot selection 4
DCDCCTRL_REG VIO_PSKIP VIO pulse skip mode enable Skip enabled
EEPROM VDD3 time slot OFF
VDIG1_REG SEL LDO voltage selection 1.2
EEPROM LDO time slot 1
VDIG2_REG SEL LDO voltage selection 1.2 V
EEPROM LDO time slot 4
VDAC_REG SEL LDO voltage selection 1.8 V
EEPROM LDO time slot 7
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Table 4. EEPROM Configuration for TPS65910 (continued)
Register Bit Description Option Selected
VPLL_REG SEL LDO voltage selection 1.8 V
EEPROM LDO time slot 7
VAUX1_REG SEL LDO voltage selection 1.8 V
EEPROM LDO time slot 6
VMMC_REG SEL LDO voltage selection 3.3 V
EEPROM LDO time slot 5
VAUX33_REG SEL LDO voltage selection 3.3 V
EEPROM LDO time slot 5
VAUX2_REG SEL LDO voltage selection 3.3 V
EEPROM LDO time slot 6
CLK32KOUT pin CLK32KOUT time slot 7
NRESPWRON pin NRESPWRON time slot 7 + 1
VRTC_REG VRTC_OFFMASK 0 = VRTC LDO will be in low-power mode during Low-power mode
OFF state.
1 = VRC LDO will be in full-power mode during
OFF state.
DEVCTRL_REG RTC_PWDN 0 = RTC in normal power mode 1
1 = Clock gating of RTC register and logic, low-
power mode
DEVCTRL_REG CK32K_CTRL 0 = Clock source is crystal/external clock. Crystal
1 = Clock source is internal RC oscillator.
DEVCTRL2_REG TSLOT_LENGTH Boot sequence time slot duration: 2 ms
0 = 0.5 ms
1 = 2 ms
DEVCTRL2_REG IT_POL 0 = INT1 signal will be active low. 1
1 = INT1 signal will be active high.
INT_MSK_REG VMBHI_IT_MSK 0 = Device automatically switches on at NO 0 = Automatic switch on
SUPPLY-to-OFF or BACKUP-to-OFF transition. from supply insertion
1 = Start-up reason is required before switch-on.
VMBCH_REG VMBCH_SEL[1:0] Select threshold for main battery comparator 3 V
threshold VMBCH.
4 Getting Started With TPS65910 and OMAPL-137, OMAPL-138, and TMS320C6742/6/8
Processors
4.1 First Initialization
4.1.1 I/O Polarity/Muxing Configuration
Program DEVCTRL2_REG.SLEEPSIG_POL according to the GPIO from the processor. This can be set to
active low or active high for SLEEP transition. Software configuration allows specific power resources to
enter low consumption state.
Set DEVCTRL_REG.DEV_SLP = 1 to allow SLEEP transition when requested.
Update the GPIO0 configuration (GPIO0_REG) based on your needs.
4.1.2 Define Wake-Up/Interrupt Event (SLEEP or OFF)
Select the appropriate bits in the INT_MSK_REG and INT_MSK2_REG registers to activate an interrupt to
the processor on the INT1 line.
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