Texas Instruments DP83867E User manual

User's Guide
DP83867 Dual-Port TSN PCIe Application Interface Card
ABSTRACT
This user's guide describes the design, setup, and function of the DP83867 Dual-Port TSN PCIe Application
Interface Card (AIC). The PCIe AIC supports two Ethernet ports with 1000/100/10 Mb/s and is compliant with the
IEEE 802.3 standard. This reference design supports SGMII for MAC connections.
The AIC card can be interfaced to the Intel Tiger Lake H IoT and Alder Lake S reference design through the
PCIe interface.
Table of Contents
1 Introduction.............................................................................................................................................................................2
1.1 Overview............................................................................................................................................................................ 2
1.2 Hardware Features............................................................................................................................................................ 3
1.3 Software Features..............................................................................................................................................................3
1.4 Block Diagram....................................................................................................................................................................4
2 Board Overview...................................................................................................................................................................... 5
2.1 Components.......................................................................................................................................................................5
2.2 PCIe Header Signals..........................................................................................................................................................6
3 Quick Start...............................................................................................................................................................................7
4 Schematic, Board Layout, and Bill of Materials...................................................................................................................8
4.1 Board Layout .....................................................................................................................................................................8
4.2 Schematic........................................................................................................................................................................ 10
4.3 Bill of Materials.................................................................................................................................................................15
5 Revision History................................................................................................................................................................... 18
Trademarks
All trademarks are the property of their respective owners.
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1 Introduction
1.1 Overview
Figure 1-1. DP83867 Dual-Port TSN PCIe Application Interface Card (Top View)
Figure 1-2. DP83867 Dual-Port TSN PCIe Application Interface Card (Bottom View)
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The DP83867 Dual-Port TSN PCIe Application Interface Card plugs into the Intel Tiger Lake or Alder Lake
reference design through the PCIe interface connector. This is an easy way to evaluate the functionality of the
DP83867 Ethernet PHY with the Intel CPU reference design.
Note that the PCIe interface connector is used only as a form factor and uses proprietary interface signal
assignment as given by the Intel reference design. The PCIe form factor carries the SGMII signaling for two
Ethernet ports, MDIO/MDC, power supply and control signals.
The AIC supports MDIO access via dedicated a SMI interface over the PCIe interface. The two DP83867 PHYs
use different MDIO addresses to be addressed via the common interface.
For easy testing and development purpose, the AIC card supports several pin headers for signal probing.
The AIC uses the two RJ45 jack LEDs to show PHY link and speed indication with one LED, and PHY data
transfer activity with the second LED.
Note
The AIC card supports resistor and capacitor mounting options to deploy DP83869 Ethernet PHY
instead of DP83867 on each Ethernet interface port by using the same PHY footprint on the PCB.
1.2 Hardware Features
DP83867 Dual-Port TSN PCIe Application Interface Card features:
• Two DP83867 Gbit Ethernet PHYs
• Two port SGMII MAC interface
• Common serial management interface (SMI) with MDIO/MDC signals to access both DP83867 Ethernet
PHYs
• Two RJ45 jack connector with integrated magnetics
• Two LEDs in each RJ45 jack giving status information for different PHY operation modes
• On-board power generation for all PHYs, sourced by 5 V power supply through the PCIe connector
1.3 Software Features
• All Ethernet PHY MDIO registers can be accessed via PCIe interface.
– DP83867 on Ethernet port 1 has MDIO address #0
– DP83867 on Ethernet port 2 has MDIO address #1
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1.4 Block Diagram
Intel Host Platform
DP83867 Dual-Port TSN PCIe Application Interface Card
DP83867TGL-H
SGMII_INT
SGMII_MDC
SGMII_MDIO
SGMII_RESET
SGMII_AUXTX
SGMII_PPS
SGMII_INT
SGMII_MDC
SGMII_MDIO
SGMII_RESET
SGMII_AUXTX
SGMII_PPS
SGMII TX P/N
SGMII RX P/N
MDIO
MDC
RESET_N
INT_N (OD)
AUXTX / GPIO
PPS / GPIO
XTAL1
XTAL2
MDI[3:0]
GPIO
Port 2
RJ45
SFP Connector
DP83867
SGMII TX P/N
SGMII RX P/N
MDIO
MDC
RESET_N
INT_N (OD)
AUXTX / GPIO
PPS / GPIO
XTAL1
XTAL2
MDI[3:0]
GPIO
Port 1
RJ45
PCIe
x4
RGMII HDR
RGMII TX[3:0]
RGMII RX[3:0]
2x8 HDR
2x8 HDR
TGL-U
SGMII_INT
SGMII_MDC
SGMII_MDIO
SGMII_RESET
SGMII_AUXTX
SGMII_PPS
SGMII_INT
SGMII_MDC
SGMII_MDIO
SGMII_RESET
SGMII_AUXTX
SGMII_PPS
ADL
SGMII_INT
SGMII_MDC
SGMII_MDIO
SGMII_RESET
SGMII_AUXTX
SGMII_PPS
SGMII 2 TX
SGMII 2 RX
SMB_SDA/MDIO
SMB_SCL/MDC
PLT_RST
SGMII 1 TX
SGMII 1 RX
SGMII_INT
SGMII_MDC
SGMII_MDIO
SGMII_RESET
SGMII_AUXTX
SGMII_PPS
SGMII 1 TX
SGMII 1 RX
SMB_SDA/MDIO
SMB_SCL/MDC
PLT_RST
PET/
PER0
PET/
PER1
SGMII 2 TX
SGMII 2 RX
SMB_SDA/MDIO
SMB_SCL/MDC
PLT_RST
SGMII 1 TX
SGMII 1 RX
Figure 1-3. Block Diagram
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2 Board Overview
2.1 Components
Figure 2-1 below gives a quick overview of the AIC board. The marked sections are described in the Table 2-1.
Figure 2-1. Connectors, Jumpers and LEDs
Table 2-1. Component Table
Section Description
1 RJ45 with integrated magnetic G-Bit network connection Port 1 / TSN_0
2 RJ45 with integrated magnetic G-Bit network connection Port 2 / TSN_1
3 DP83867 PHY1 for Port 1
4 DP83867 PHY2 for Port 2
5 25 MHz clock generation for both PHYs
6 Signal connector MISC0 for validation
7 Signal connector MISC1 for validation
8 Signal connector RGMII interface (optional)
9 PCIe interface
10 Power indicator LEDs.
• D10: 3.3V indicator
• D11: VDDIO indicator PHY1
• D12: VDDIO indicator PHY2
• D9: 3.3V indicator for optional SFP+ module
11 VDDIO voltage selector jumper pin-header
• J19: PHY 1
– Pin 1-2: 3.3V
– Pin 2-3: 1.8V (default)
12 VDDIO voltage selector jumper pin-header
• J21: PHY 1
– Pin 1-2: 3.3V
– Pin 2-3: 1.8V (default)
13 Shield/Earth GND for testing.
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2.2 PCIe Header Signals
Please refer to the schematics in section Section 4.2 for the PCIe signal assignment and description. The signal
assignment is following the signal layout of the Intel host platform.
2.2.1 MISC0 Signal Header
The MSIC0 signal header is for debug purpose.
Table 2-2. MISC0 Signal Header for PHY1
Pin Number Signal Description
1 MDC PHY1
3 MDIO PHY1
5 Interrupt PHY1
7 AUXTS PHY1 (Start-of-Frame time stamp)
9 PPS PHY1 (not supported by AIC)
11 Reset PHY1
13, 15 Not connected
2, 4, 6, 8, 10, 12, 14, 16 GND
2.2.2 MISC1 Signal Header
The MSIC1 signal header is for debug purposes.
Table 2-3. MISC1 Signal Header for PHY2
Pin Number Signal Description
1 MDC PHY2
3 MDIO PHY2
5 Interrupt PHY2
7 AUXTS PHY2 (Start-of-Frame time stamp)
9 PPS PHY2 (not supported by AIC)
11 Reset PHY2
13, 15 Not connected
2, 4, 6, 8, 10, 12, 14, 16 GND
2.2.3 RGMII Signal Header
RGMII signal header for PHY1 can be used to connect PHY1 via separate cable connection.
Table 2-4. RGMII Signal Header for PHY1
Pin Number Signal Description
1 TXCLK
2 RXCLK
3 TXCTL
4 RXCTL
7 TXDATA_3
8 RXDATA_3
9 TXDATA_2
10 RXDATA_2
11 TXDATA_1
12 RXDATA_1
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Table 2-4. RGMII Signal Header for PHY1 (continued)
Pin Number Signal Description
13 TXDATA_0
14 RXDATA_0
5, 6, 15, 16 GND
3 Quick Start
1. Power down the Intel host platform (Intel Tiger Lake UP3, Tiger Lake H IoT or Alder Lake S).
2. Plug-in the DP83867 Dual-Port TSN PCIe Application Interface Card into the Intel host platform.
3. Power up the Intel host platform.
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4 Schematic, Board Layout, and Bill of Materials
4.1 Board Layout
Figure 4-1. Assembly Drawing Top Layer
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Figure 4-2. Assembly Drawing Bottom Layer
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4.2 Schematic
TP3
TP4
TP5
GND
+V3.3A_RVP
+V3.3A_AUX
+V12A
+V3.3A
+V1.8A
TP6
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
BOT
B11
TOP
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
EC1
A32
EDGE_CONN_PCIe-x4
GND GND
+V12A +V12A
+V3.3A_RVP
+V3.3A_RVP
+V3.3A_AUX
X1_PRSNT_N
PRSNT_N
PRSNT_N
SGMII1_TX_D_P
SGMII1_TX_D_N
SGMII2_TX_D_P
SGMII2_TX_D_N
0R12
51kR21
100R24
100R28 GND
SGMII1_RX_D_N
SGMII2_RX_D_P
SGMII2_RX_D_N
10uF
C1
0.1uF
C2
GND
1.0kR20
+V3.3A_AUX
C3
10uF 0.1uF
C4
GND
SGMII1_RX_D_P
SGMII1_SFP_RX_D_P
SGMII1_SFP_RX_D_N
SGMII1_SFP_TX_D_P
SGMII1_SFP_TX_D_N
12
3 4
5 6
7 8
9 10
11 12
13 14
15 16
J1
PRPC008DAAN-RC
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
J3
GND
GND
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
J2
PRPC008DAAN-RC
MISC0_HDR
MISC1_HDR
RGMII_HDR
0R5
0R6
0R7
0R9
0R15
0R16
0R17
0R19
RGMII_INT
RGMII_RESET
SGMII_INT
GBE_MDC_1
GBE_MDIO_1
SGMII_RESET
RGMII_TXCLK
RGMII_TXCTL
RGMII_TXDATA_3
RGMII_TXDATA_2
RGMII_TXDATA_1
RGMII_TXDATA_0
RGMII_RXCLK
RGMII_RXCTL
RGMII_RXDATA_3
RGMII_RXDATA_2
RGMII_RXDATA_1
RGMII_RXDATA_0
GND
PRPC008DAAN-RC
GND
TP1
RGMII_PPS
GND
SGMII_PPS
GND
SMB_CLK
SMB_DAT
SMB_CLK
SMB_DAT
0R4
0R3
0R13
0R14
SGMII_PPS
RGMII_AUXTS
SGMII_AUXTS
4
SGMII_AUXTS
1
2
3
J4
61300411121
GND
PHY1 Signals
PHY2 Signals
PHY1_GPIO_1
PHY1_GPIO_0
PHY1_LED_1
RGMII_AUXTS
RGMII_PPS
1
5 4 3 2
J6
142-0701-201
GND
4
PHY1_CLK_OUT
1
2
3
J5
61300411121
GND
PHY2_GPIO_1
PHY2_GPIO_0
PHY2_LED_1
1
5 4 3 2
J7
142-0701-201
GND
PHY2_CLK_OUT
TP9
TP8
SGMII1_SFP_MDC
SGMII1_SFP_MDIO
GBE_MDC_0
GBE_MDIO_0
PET3_R_D_P
PET3_R_D_N
PET2_R_D_P
PET2_R_D_N
PET1_R_D_P
PET1_R_D_N
PET0_R_D_P
PET0_R_D_N
PER0_C_D_P
PER0_C_D_N
PER1_C_D_P
PER1_C_D_N
PER2_C_D_P
PER2_C_D_N
PER3_C_D_P
PER3_C_D_N
PCIE_REFCLK_D_P
PCIE_REFCLK_D_N
PERST_N
RGMII_RESET
SGMII_RESET
GBE_MDC_0
TP2
GBE_MDC_0
GBE_MDIO_0
GBE_MDIO_0
0
R1
0
R2
0
R10
0
R11
0R242
0R243
0
R47
0
R50
0R54
0R56
0
R48
0
R51
0R55
0R57
PET_0_2_P
PET_0_2_N
PER_0_2_P PER_0_2_N
0
R27
0R31
20.0k
R8
20.0k
8R1
20.0kR58 20.0kR59
1.0kR22
1.0kR23
+V3.3A
X1_PRSNT_N
0
R249
C134
10uF 0.1uF
C135
+V3.3A_RVP
GND
0R25
0R26
0R29
0R30
0.1uFC78
0.1uFC79
C80 0.1uF
0.1uFC81
0R33
0R36
0R40
0R41
0R44
0R45
0R52
0R53
0R34
0R32
0R35
0R37
SI_P
SI_N
GND
TX_D -> SI (input to '67)
SI_P
SI_N
TX_D -> SI (input to '67)
C30 0
C31 0
C32 0
C33 0
CAD NOTE:
3 PAD, PLACE CLOSE TO
EDGE CONNECTOR
CAD NOTE:
3 PAD, PLACE CLOSE TO
EDGE CONNECTOR
CAD NOTE:
3 PAD, PLACE CLOSE TO
EDGE CONNECTOR
Figure 4-3. Schematic : PCIe Host Interface
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1
7
GND
PHY1_CLK
PHY1_TD_A_P
PHY1_TD_A_N
PHY1_TD_B_P
PHY1_TD_C_P
PHY1_TD_D_P
PHY1_TD_D_N
PHY1_TD_B_N
PHY1_TD_C_N
GND
PHY1_LED_0
PHY1_LED_2
PHY1_LED_0
PHY1_LED_1
PHY1_LED_2
PHY1_GPIO_0
PHY1_GPIO_1
1%
PHY1_GPIO_0
2.49k
R115
1%
R105
2.49k
1%
2.49k
R116
1%
R106
2.49k
1%
2.49k
R117
1%
R107
2.49k
1%
2.49k
R118
1%
R108
2.49k
1%
2.49k
R119
GND
P1_VCC_VDDIO
10uF
C5
16V
0.01uF
C17
GND
10uF
C9
16V
0.01uF
C18
GND
10uF
C12
16V
0.01uF
C19
GND
2.2k
R123
P1_VCC_VDDIO
MDIO Address 0
GND
EARTH_GND
GND
2kV
1000pFC44
16V
0.1uF
C8
16V
0.1uF
C7
16V
0.1uF
C6
16V
0.1uF
C10
16V
0.1uF
C11
16V
0.1uF
C13
16V
0.1uF
C14
16V
0.1uF
C15
16V
0.1uF
C16
22pFC41
GND
10V
1uF
C21
10V
1uF
C20
10V
1uF
C22
10V
1uF
C23
10V
1uF
C24
10V
1uF
C25
10V
1uF
C26
10V
1uF
C27
10V
1uF
C28
R72 11.0k
Mode 1
Mode 1
Mode 3
Mode 2
Mode 1
Mode 1
Mode 1
Mode 1
8R9
1.0M
RGMII_TXDATA_0
RGMII_TXDATA_1
RGMII_TXDATA_2
RGMII_TXDATA_3
RGMII_RXDATA_0
RGMII_RXDATA_1
RGMII_RXDATA_2
RGMII_RXDATA_3
RGMII_TXCTL
RGMII_TXCLK
SGMII1_RX_D_N
SGMII1_RX_D_P
SGMII1_TX_D_N
SGMII1_TX_D_P
GBE_MDC_0
GBE_MDIO_0
PHY1_LED_1
P1_VCC_VDDIO
P1_VCC_VDDIO
RGMII_INT
ESD prodection
RGMII_RXDA
PHY1_RX_D2 TA_0
RGMII_RXCTL
1%
2.49k
R112
1%
R102
2.49k
1%
2.49k
R113
1%
2.49k
R114
GND
P1_VCC_VDDIO
R101
10.0k
R100
10.0k
R99
10.0k
1%
2.49k
R111
1%
2.49k
R110
PHY1_RX_D2
PHY1_RX_D3
PHY1_RX_D3
RGMII_RXDATA_1
For SGMII, add same resistor load to RXD0/1 as for RXD2/3
0R68
0R69
0R73
0R75
0R88
P1_VDD1P0_MDC P1_VCC_1.0V
0R67
P1_GPIO1_CLKOUT
0R78
0R80
P1_GPIO0_VDD1P0
0R77
P1_VCC_1.0V
0R89
P1_XI_SOP
P1_XO_SON
P1_VCC_VDDIO
0R85
0R87
P1_VDDIO_XO
P1_VCC_2.5V
P1_VCC_VDDIO
PHY1_CLK
0R79
P1_JTAGCLK_XI
P1_JTAGTMS_GPIO1 PHY1_GPIO_1
01R8
P1_VCC_1.0V
P1_JTAGTDI_JTAGTMS
P1_JTAGTDO_TXER
P1_VCC_1.0V
P1_VDD1P0_SD
P1_VDDIO_MDIO
0R64
060GBE_MDIO_0R
0R61
0R63
0R66
PHY1_GPIO_1 R222
PHY1_CLK_OUT
0R96
0.1uFC37
0.1uFC39
C34 0.1uF
C36 0.1uF
(Mode 1)
(Mode 1)
0R76
R83 2.20k
R86 2.20k
P1_SI_P
P1_SI_N
P1_SI_N
P1_SI_P
P1_CLKOUT_VDDIO
0R90
0R91
P1_MDC_SI_P
P1_MDIO_SI_N
0R92
0R94
P1_SO_N
P1_SO_P
P1_SO_N
P1_SO_P
PHY1_TX_D0
PHY1_TX_D1
R84 2.20k
GND
L1
742792062
L2
742792062
L3
742792062
VCC_VDDIO_PHY1 VCC_2.5V VCC_1.0V_PHY1
4.7pFC45
4.7pFC46
4.7pFC47
4.7pFC48
4.7pFC49
4.7pFC50
4.7pFC51
4.7pFC52
GND
GND
GND
GND
PHY1_TD_A_P
PHY1_TD_A_N
PHY1_TD_B_P
PHY1_TD_B_N
PHY1_TD_C_P
PHY1_TD_C_N
PHY1_TD_D_P
PHY1_TD_D_N
RGMII_RESET
GND
0R124
R121 10k
0
R122
P1_VCC_VDDIO P1_VCC_2.5V P1_VCC_1.0V
P1_VCC_VDDIO
RGMII_RESET_N
RGMII_RESET_N
6
VDD1P0 24
VDD1P0 31
VDD1P0 42
VDD1P0
13
VDDA1P8 48
VDDA1P8
3VDDA2P5
9VDDA2P5
19 VDDIO
30 VDDIO
41 VDDIO
2
TD_M_A
5
TD_M_B
8
TD_M_C
11
TD_M_D
1
TD_P_A
TD_P_B 4
7
TD_P_C
10
TD_P_D
20
JTAG_CLK
23
JTAG_TDI 21
JTAG_TDO
22
JTAG_TMS
28 TX_D0/SGMII_SIN
27 TX_D1/SGMII_SIP
26 TX_D2
25 TX_D3
44 INT/PWDN
43 RESET
18 CLK_OUT
29 GTX_CLK
16
MDC 17
MDIO
12
RBIAS
TX_CTRL
37
15 XI
14 XO
32 RX_CLK
RX_CTRL
38
33 RX_D0/SGMII_COP
34 RX_D1/SGMII_CON
35 RX_D2/SGMII_SOP
36 RX_D3/SGMII_SON
39 GPIO_0
40 GPIO_1
LED_0 47
LED_1 46
LED_2 45
49
GND
DP83867ERGZR
U1
1%
10.0k
R104R103
5.76k
0R38
0R39
0R42
0R43
J13
7781
EARTH_GND
Use maximum copper to connect EARTH_GND
D4
EARTH_GND
GND
PHY1_LED_13
0
PHY1_LED_2 R109
GND
Yellow LED - activity
200
R74
V3.3A_REG
PHY1_LED_0_Q
PHY1_LED_1 0R93
GND
200
R97
V3.3A_REG
PHY1_LED_1_Q
3
1
2
Q1
R71 0
V3.3A_REG
1.00k
R65
PHY1_LED_0_Q
PHY1_LED_1_Q
200
PHY1_LED_0
R82
MODE4 - invert LED ctrl
V3.3A_REG
GND
PHY1_LED_13
D2
D3
D1
PHY1_LED_1_Q PHY1_LED_0_Q
PHY1_LED_13
0
R70
GBE_MDC_0
GBE_MDIO_0
GBE_MDC_0
GBE_MDIO_0
3
1
2
Q2
3
1
2
Q3
3
1
2
Q5
GND
3
1
2
Q6
GBE_MDC_0
1 2
Y3
0R95
0R149
C90
18pF
C91
18pF GND
33pFC38
PHY1_XO
7R26 0 PHY1_XI
PHY1_CLK_OUT 0R268
0R266
0R224
0
1 2
Y5
0R223
0R225
C136
18pF
C137
18pF GND
PHY1_XO
PHY1_XI
XTAL for DP83867 XTAL for DP83869
PHY1_TD_A_P PHY1_TD_A_N
GND
PHY1_TD_D_N
PHY1_TD_C_NPHY1_TD_C_P
PHY1_TD_D_P
I/O1
1
GND
2
I/O2
3I/O3 4
I/O4 5
U2 ESDS314DBVR
PHY1_TD_B_P PHY1_TD_B_N
I/O1
1
2GND
I/O2
3I/O3 4
I/O4 5
U3 ESDS314DBVR
RGMII_RXCTL
RGMII_RXCLK
CD3
D3-
D3+
D2+
D2-
CD2
CD4
D4+
D4-
D1-
D1+
CD1
Yellow_CATHODE
Yellow_ANODE
Orange_CATHODE
Orange/Green_ANODE
MNT_1
Green_CATHODE
MNT_2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
J8
7499111615
100nF
C140
100nF
C141
100nF
C143
100nF
C142
GND
GND
GND
200R62
V3.3A_REG
D13
PHY1_TD_A_P
PHY1_TD_A_N
PHY1_TD_B_P
PHY1_TD_B_N
PHY1_TD_C_P
PHY1_TD_C_N
PHY1_TD_D_P
PHY1_TD_D_N
VDD
DP83867 = 1.0V
DP83869 = 1.1V
Figure 4-4. Schematic : DP83867 Ethernet PHY #1
www.ti.com Schematic, Board Layout, and Bill of Materials
SNLU317A – SEPTEMBER 2022 – REVISED MAY 2023
Submit Document Feedback
DP83867 Dual-Port TSN PCIe Application Interface Card 11
Copyright © 2023 Texas Instruments Incorporated

1
10uF
C53
16V
0.1uF
C54
16V
0.1uF
C55
16V
0.1uF
C56
10uF
C57
16V
0.1uF
C58
16V
0.1uF
C59
10uF
C60
16V
0.1uF
C61
16V
0.1uF
C62
16V
0.1uF
C63
16V
0.1uF
C64
16V
0.01uF
C65
16V
0.01uF
C66
16V
0.01uF
C67
10V
1uF
C68
10V
1uF
C69
10V
1uF
C70
10V
1uF
C71
10V
1uF
C72
10V
1uF
C73
10V
1uF
C74
10V
1uF
C75
10V
1uF
C76
GND GND GND
P2_VDDIO_XO
0R125
P2_VDD1P0_SD 0R127
0P2_VDDIO_MDIO R128
P2_VDD1P0_MDC
0129GBE_MDIO_1R0R130
0R131
P2_SI_N PHY2_TD_A_P
P2_SI_P PHY2_TD_A_N
SGMII2_TX_D_N PHY2_TD_B_P
SGMII2_TX_D_P PHY2_TD_B_N
PHY2_TD_C_P
PHY2_TD_C_N
P2_SO_N PHY2_TD_D_P
C83 0.1uF
P2_SO_P PHY2_TD_D_N
0.1uFC84 PHY2_RX_D0
GND
PHY2_RX_D1 R135 11.0k
SGMII2_RX_D_P 0.1uFC86 PHY2_RX_D2
SGMII2_RX_D_N 0.1uFC87
PHY2_RX_D3
P2_GPIO0_VDD1P1
PHY2_GPIO_0
P2_JTAGTDI_JTAGTMS
P2_JTAGTDO_TXER
0R136
P2_JTAGCLK_XI PHY2_CLK
0R138 9 0R13
P2_GPIO1_CLKOUT P2_JTAGTMS_GPIO1
PHY2_GPIO_1 PHY2_GPIO_1
R141 00R140
SGMII_INT
PHY2_LED_0
PHY2_LED_1
R142 2.20k PHY2_LED_2
GND R143 2.20k P2_MDC_SI_P 04R14
P2_MDIO_SI_N 06R14
R145 2.20k
PHY2_CLK 07 0R148
GND
P2_SI_N
GND 22pFC89 0R150
P2_SI_P
P2_XO_SON
P2_XI_SOP
MDIO Address 1 0R152
P2_SO_P 0R153
P2_SO_N 0R154
0R155
ESD prodection
R158
10.0k
R159
10.0k
R160
10.0k
R161
2.49k
R162
5.76k 10.0k
R163 R164
2.49k
R165
2.49k
R166
2.49k
R167
2.49k
Mode 2 PHY2_RX_D0
Mode 1 PHY2_RX_D2
Mode 3 PHY2_RX_D1
PHY2_RX_CTRL
(Mode 2)
(Mode 1) PHY2_RX_D3
R169
2.49k 2.49k
R170
2.49k
Mode 2 PHY2_LED_0
Mode 1 PHY2_LED_1
Mode 1 PHY2_LED_2
Mode 1 PHY2_GPIO_0
Mode 1 PHY2_GPIO_1
R171 R172
2.49k 2.49k
R173
2.49k
R174 R175
2.49k
R176
2.49k
R177
2.49k
R178
2.49k
GND
For SGMII, add same resistor load to RXD0/1 as for RXD2/3GND
R181
2.2k
GBE_MDIO_1
GBE_MDC_1
L4
742792062
VCC_VDDIO_PHY2 VCC_2.5V VCC_1.1V_PHY2
L5
742792062
L6
742792062
P2_VCC_VDDIO P2_VCC_2.5V P2_VCC_1.1V
P2_VCC_1.1V
P2_VCC_1.1V
P2_VCC_1.1V
P2_VCC_VDDIO
P2_VCC_VDDIO
P2_VCC_VDDIO P2_VCC_VDDIO
P2_VCC_VDDIO
P2_VCC_VDDIO
P2_VCC_1.1V
P2_VCC_VDDI
R14
O
P2_VCC_2.5V
4.7pFC93
4.7pFC94
4.7pFC95
4.7pFC96
4.7pFC97
4.7pFC98
4.7pFC99
4.7pFC100
GND
GND
GND
GND
PHY2_TD_A_P
PHY2_TD_A_N
PHY2_TD_B_P
PHY2_TD_B_N
PHY2_TD_C_P
PHY2_TD_C_N
PHY2_TD_D_P
PHY2_TD_D_N
SGMII_RESET
GND
0R183
R180 10k
0
R182
P2_VCC_VDDIO
SGMII_RESET_N
SGMII_RESET_N
18 CLK_OUT
GPIO_0
39
GPIO_1
40
GTX_CLK
29
INT/PWDN
44
20
JTAG_CLK
JTAG_TDI 23
JTAG_TDO 21
JTAG_TMS 22
LED_0 47
46
LED_1 45
LED_2
MDC 16
MDIO 17
PAD 49
RBIAS 12
RX_CLK
32 RX_CTRL
38
33 RX_D0/SGMII_COP
34 RX_D1/SGMII_CON
35 RX_D2/SGMII_SOP
36 RX_D3/SGMII_SON
2
TD_M_A
5
TD_M_B
8
TD_M_C
TD_M_D 11
1
TD_P_A
4
TD_P_B
7
TD_P_C
10
TD_P_D
37 TX_CTRL
28 TX_D0/SGMII_SIN
TX_D1/SGMII_SIP
27
TX_D2
26
TX_D3
25
VDD1P0 42
VDD1P0 31
24
VDD1P0
6
VDD1P0
48
VDDA1P8
VDDA1P8 13
3
9VDDA
VDDA
2
2
P
P
5
5
30
41 VDDI
VDDI
O
O
VDDIO
19
X_I
15
X_O
14
RESET
DP83867ERGZR
43
U6
0R46
0R49
0R203
0R231
GBE_MDC_1
GBE_MDIO_1
GBE_MDC_1
GBE_MDIO_1
EARTH_GND
GND
2kV
C42 1000pF
6R15
1.0M
D8
EARTH_GND
PHY2_LED_13
0
PHY2_LED_2 R157
GND
GND
Yellow LED - activity
200
R133
V3.3A_REG
PHY2_LED_0_Q
PHY2_LED_1 0R137
GND
200
R151
V3.3A_REG
PHY2_LED_1_Q
3
1
2
Q4
R132 0
V3.3A_REG
1.00k
R120
PHY2_LED_0_Q
PHY2_LED_1_Q
200
PHY2_LED_0
R134
MODE4 - invert LED ctrl
V3.3A_REG
GND
PHY2_LED_13
D6
D7
D5
PHY2_LED_1_Q
PHY2_LED_0_Q PHY2_LED_13
0
R126
3
1
2
Q7
3
1
2
Q8
3
1
2
Q9
3
1
2
Q10
GBE_MDC_1
P2_CLKOUT_VDDIO
PHY2_CLK_OUT 0R235
PHY2_CLK_OUT
1 2
Y4
0R240
0R245
2C13
18pF GND
18pF
C92
33pFC85
PHY2_TD_A_P
PHY2_TD_A_N
PHY2_TD_B_P
PHY2_TD_B_N
PHY2_TD_C_P
PHY2_TD_C_N
PHY2_TD_D_P
PHY2_TD_D_N
0R241
R270 0 PHY2_XI
0PHY2_XO R269
1 2
Y6
0R272
0R274
C138
18pF
C139
18pF GND
XTAL for DP83869
PHY2_XO
PHY2_XI
XTAL for DP83867
0R273
0R271
GND
PHY2_TD_A_P PHY2_TD_A_N
GND
PHY2_TD_D_N
PHY2_TD_C_NPHY2_TD_C_P
PHY2_TD_D_P
I/O1
1
GND
2
I/O2
3I/O3 4
I/O4 5
U4 ESDS314DBVR
PHY2_TD_B_P PHY2_TD_B_N
I/O1
1
GND
2
I/O2
3I/O3 4
I/O4 5
U5 ESDS314DBVR
PHY2_RX_CTRL
CD3
D3-
D3+
D2+
D2-
CD2
CD4
D4+
D4-
D1-
D1+
CD1
Yellow_CATHODE
Yellow_ANODE
Orange_CATHODE
Orange/Green_ANODE
MNT_1
MNT_2
Green_CATHODE
13
14
15
16
17
J9
7499111615
100nF
C144
GND
200R244
V3.3A_REG
100nF
C145
GND
100nF
C146
GND
100nF
C147
GND
D14
VDD
DP83867 = 1.0V
DP83869 = 1.1V
Figure 4-5. Schematic : DP83867 Ethernet PHY #2
Schematic, Board Layout, and Bill of Materials www.ti.com
12 DP83867 Dual-Port TSN PCIe Application Interface Card SNLU317A – SEPTEMBER 2022 – REVISED MAY 2023
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Copyright © 2023 Texas Instruments Incorporated

SFP_LOS
1
2Shi
Shi
e
e
l
l
d
d
3
4Shi
Shi
e
e
l
l
d
d
5
6Shi
Shi
e
e
l
l
d
d
7
Shield 8
Shield 9
Shield
Shield 10
11
Shield 12
Shield
MH1 MH5 MH5
M
M
M
H
H
H
2
3
4
M
M
M
M
H
H
H
H
1
2
3
4
MH6 MH6
MH7 MH7
MH8 MH8
H1
SFP_RS0
SFP_MD_0
1
3
5
6
4
2
7
9
10
8
12
11
14
13
16
15
18
17
20
19
J17
SGMII1_SFP_MDC
EARTH_SFP_GNDEARTH_SFP_GND
SGMII1_SFP_MDIO
SGMII1_SFP_RESET_N
SFP_TX_FAULT
GND GND
SGMII1_SFP_TX_D_P
SGMII1_SFP_TX_D_N
10.0k
R184
10.0k
R191
GND
10.0k
R185
10.0k
R192
10.0k
R186
10.0k
R193
10.0k
R187
10.0k
R194
10.0k
R188
10.0k
R195
10.0k
R189
10.0k
R196
10.0k
R190
10.0k
R197
SFP_LOS
SFP_RS0
SFP_RS1
SFP_RS1
SGMII1_SFP_INT_N
SGMII1_SFP_INT_N
SFP_TX_FAULT
SFP_MD_0
SGMII1_SFP_RESET_N
FXVCCT
FXVCCR
FX3V3
FXVCCT
FX3V3
1uH
L7
0
R198
0.01uF
C101 C102
0.1uF
GND
FXVCCR
L8
1uH
C103
0.01uF 0.1uF
C104
10uF
C105
GND
FX3V3
470
R199
21
Green
D9
GND
SGMII1_SFP_MDC
SGMII1_SFP_MDIO
R247 2.2k FX3V3
+V3.3A
EARTH_SFP_GNDGND
2kV
C133 1000pF
R248
1.0M
SGMII1_SFP_RX_D_P
SGMII1_SFP_RX_D_N
CAUTION NOTE: RX_D
and TX_D are swapped in the
E1/E2 board version.
Figure 4-6. Schematic : Ethernet Fiber interface
www.ti.com Schematic, Board Layout, and Bill of Materials
SNLU317A – SEPTEMBER 2022 – REVISED MAY 2023
Submit Document Feedback
DP83867 Dual-Port TSN PCIe Application Interface Card 13
Copyright © 2023 Texas Instruments Incorporated

VDDIO voltage selection PHY1 V3.3A_REG
+V3.3A
GND
0.1uF
C106
1
2
3
J19
61300311121
+V12A
J18_12
QPC02SXGN-RC 25V
10uF
C107
25V
C108
0.1uF 10V
22uF
C109
GND
R204 100k
GND
R205
309k
VOUT 4
1EN
VIN
2
GND 3
PG 7
8SS/TR
FB 6
VOUT 5
9
PAD
U11
TPS82140SILR
R206
100k
GND
50V
3300pF
C111
GND
GND
VCC_2.5V
316k
R209
4.7µF
10V
C112
10V
10µF
C113
100k
Power supply input for AIC stand-alone test
R210
GND
+V12A
1
2
J22
691210910002
VCC_1.0V_PHY1
66.5k
R211
10V
4.7µF
4C11
10V
22uF
C115
10V
22uF
C116
100k
R212
+V1.8A_VDDIO
GND
6.3V
C121
1uF
6.3V
1uF
C122
OUT 1
GND 2 EN
3
IN
4
DAP 5
U15
GND TLV70718PDQNT
GNDGND
+V1.8A
+V1.8A
GND 0.1uFC117 0.1uFC118
GND
0.1uFC120
+V1.8A
18pF
C119
R214 2.20k TP7
XIN TESTPOINT
PHY1_CLK
0R217
1XIN/CLK
2S0
3VDD
4VCTR
5
GND
6
VDDOUT 7
VDDOUT
8
Y3
9
Y2
GND 10
Y1 11
SCL/S2
12 SDA/S1
13
XOUT
14
U14
CDCEL913IPWRQ1
1 2
Y1
25MHz
GND
PHY2_CLK
18pF
C123
0R218
+V1.8A R219 2.20k
R220 2.20k
V3.3A_REG
VCC_VDDIO_PHY1
R221 2.20k
GND
+V1.8A
470
R200 470
R201
GND 0.1uFC124 6VDD 5
CLK_N
CLK_P 4
2
1 3
GND
Y2
GND
LMK6PA15625ADLFT
Green
21
D10 Green
21
D11
GND
J20_12
QPC02SXGN-RC
+V3.3A
GND
0.1u
C110
1
2
3
J21
61300311121
VDDIO voltage selection PHY2
Select +3V3A voltage source
V3.3A_REG +V3.3A +V3.3A_RVP
0
R226
0
R216
10V
10µF
C126
10µF
C125
10V
GND GND
+V3.3A
+V3.3A
+V3.3A
+V3.3A
6VDD
1G
2
1CLKIN
Y0 3
Y1 8
NC 5
NC 7
4
GND
LMK1C1102PWR
U16
0R227
0R228
0
R230
0
R229
PHY1_CLK
PHY2_CLK
GND
C127 0.1uF
GND
V1.8A L11 +
VCC_1.1V_PHY2
4.7µF
10V
C129
10V
22uF
C130
10V
22uF
C131
100k
R239
GND
+V3.3A
66.5k
R238
C128 10µF
6.8pF
C29
6.8pF
C35
6.8pF
C40
2.2uH
L9
2.2uH
L10
2.2uH
L12
EN
5
GND 2
SW 4 VIN
3
FB 1
6NC
U12
TLV62568ADRLR
EN
5
2
GND
SW 4 VIN
3
FB 1
NC
6
U13
TLV62568ADRLR
5EN
GND 2
SW 4
3VIN
FB 1
NC
6
U17
TLV62568ADRLR
IN
1
GND 2
ON
3
N/C
4
5
QOD
6
OUT
U18
TPS22919DCKR
VCC_VDDIO_PHY1
VCC_2.5V 0R179
0
R168
0.1uF
C43
GND
IN
1
2
GND
3ON
4N/C
5
QOD
OUT 6
U19
TPS22919DCKR
F
VCC_2.5V 0R208
0
R207
0.1uF
C77
GND
VCC_VDDIO_PHY2
0R232
0R233
0R234
0
R236
0R215
0R213
0R237
3
1
2
Q11
GNDGND
+V3.3A VCC_VDDIO_PHY2
470
R202
Green
21
D12
3
1
2
Q12
+V3.3A
GNDGND
+V1.8A
6.3V
C82
1uF
6.3V
1uF
C88
1
OUT
2
GND
3EN
IN
4
DAP 5
U20
GND TLV70718PDQNT
GNDGND
+V3.3A
+V1.8A_VDDIO
+V1.8A_VDDIO
GND
ToDo: Check solder paste / foot print to avoid shorts during soldering
VDD
DP83867 = 1.0V; R211=66.5k
DP83869 = 1.1V; R211=82.5k
VDD
DP83867 = 1.0V; R238=66.5k
DP83869 = 1.1V; R238=82.5k
This is the footprint
placeholder for LMK6CE
Figure 4-7. Schematic : Power, Clock and Configuration
Schematic, Board Layout, and Bill of Materials www.ti.com
14 DP83867 Dual-Port TSN PCIe Application Interface Card SNLU317A – SEPTEMBER 2022 – REVISED MAY 2023
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Copyright © 2023 Texas Instruments Incorporated

4.3 Bill of Materials
Table 4-1. Bill of Materials
Designator Qty Part Number Description Footprint
C1, C3, C107, C134 4 C3216X7R1E106M160AE CAP, CERM, 10 uF, 25 V, +/-
20%, X7R, 1206_190
1206_190
C2, C4, C108, C135 4 GRM155R71E104KE14D CAP, CERM, 0.1 uF, 25 V,
+/- 10%, X7R, 0402
0402
C5, C9, C12, C53, C57, C60 6 C3216X7R1V106M160AC CAP, CERM, 10 uF, 35 V, +/-
20%, X7R, 1206_190
1206_190
C6, C7, C8, C10, C11, C13, C14,
C15, C16, C37, C39, C43, C54,
C55, C56, C58, C59, C61, C62,
C63, C64, C77, C86, C87, C106,
C110, C117, C118, C120
29 GRM033C71C104KE14D CAP, CERM, 0.1 uF, 16 V,
+/- 10%, X5R, 0201
0201
C17, C18, C19, C65, C66, C67 6 885012205031 CAP, CERM, 0.01 uF, 16 V,
+/- 10%, X7R, 0402
0402
C20, C21, C22, C23, C24, C25,
C26, C27, C28, C68, C69, C70,
C71, C72, C73, C74, C75, C76
18 GRM033R61A105ME15D CAP, CERM, 1 uF, 10 V,+/-
20%, X5R, 0201
0201
C30, C31, C32, C33, R3, R4,
R5, R6, R7, R9, R12, R13, R14,
R15, R16, R17, R19, R26, R30,
R33, R34, R36, R37, R40, R41,
R42, R43, R70, R77, R78, R85,
R87, R88, R89, R124, R126, R136,
R140, R144, R146, R147, R148,
R168, R179, R183, R203, R207,
R208, R213, R215, R217, R218,
R224, R231, R232, R233, R234,
R236, R237, R241, R249, R268,
R273
63 CRCW02010000Z0ED RES, 0, 5%, 0.05 W, 0201 0201
C41, C89 2 GCM0335C1E220JD03D CAP, CERM, 22 pF, 25 V, +/-
5%, C0G/NP0, AEC-Q200
Grade 1, 0201
0201
C44 1 1812GC102KA1 CAP, CERM, 1000 pF, 2000
V, +/- 10%, X7R, 1812
1812
C45, C46, C47, C48, C49, C50,
C51, C52, C93, C94, C95, C96,
C97, C98, C99, C100
16 GRM0335C1H4R7CA01D CAP, CERM, 4.7 pF, 50 V,
+/- 5%, C0G/NP0, 0201
0201
C82, C88, C121, C122 4 GRM155R70J105MA12D CAP, CERM, 1 uF, 6.3 V, +/-
20%, X7R, 0402
0402
C109, C115, C116, C130, C131 5 C2012X7S1A226M125AC CAP, CERM, 22 uF, 10 V, +/-
20%, X7S, 0805
0805
C111 1 GRM1885C1H332JA01D CAP, CERM, 3300 pF, 50 V,
+/- 5%, C0G/NP0, 0603
0603
C112, C114, C129 3 LMK212B7475KG-T CAP, CERM, 4.7 uF, 10 V,
+/- 10%, X7R, 0805
0805
C113, C125, C128 3 C2012X7R1A106M125AC CAP, CERM, 10 uF, 10 V, +/-
20%, X7R, 0805
0805
C119, C123 2 GRM1555C1H180JA01D CAP, CERM, 18 pF, 50 V, +/-
5%, C0G/NP0, 0402
0402
C140, C141, C142, C143, C144,
C145, C146, C147
8 885012205086 100 nF ±10% 50 V Ceramic
Capacitor X7R 0402 (1005
Metric)
0402
D10, D11, D12 3 150060VS75000 LED, Green, SMD LED_0603
D13, D14 2 TPD1E1B04DPYR 1-Channel ESD Protection
Diode With Low
Dynamic Resistance and
Low Clamping Voltage,
DPY0002A (X1SON-2)
DPY0002A
www.ti.com Schematic, Board Layout, and Bill of Materials
SNLU317A – SEPTEMBER 2022 – REVISED MAY 2023
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Table 4-1. Bill of Materials (continued)
Designator Qty Part Number Description Footprint
FID1, FID2, FID3, FID4, FID5, FID6 6 N/A Fiducial mark. There is
nothing to buy or mount.
N/A
J1, J2, J3 3 PRPC008DAAN-RC Header, 2.54mm, 8x2, Gold,
TH
Header, 2.54mm, 8x2,
TH
J8, J9 2 7499111615 WE-RJ45 LAN Transformer
1000 Base-T
CONN_RJ45
J18_12, J20_12 2 QPC02SXGN-RC JUMPER
J19, J21 2 61300311121 Header, 2.54 mm, 3x1, Gold,
TH
Header, 2.54mm, 3x1,
TH
L1, L2, L3, L4, L5, L6 6 742792062 Ferrite Bead, 80 ohm @ 100
MHz, 0.5 A, 0805
0805
L9, L10, L12 3 SDER041H-2R2MS Inductor, 2.2 uH, 2.8 A,
0.045 ohm, SMD
4x4mm
LBL1 1 THT-14-423-10 Thermal Transfer Printable
Labels, 0.650" W x 0.200" H
- 10,000 per roll
PCB Label 0.650 x 0.200
inch
Q2, Q5, Q7, Q9, Q11, Q12 6 CSD13383F4 MOSFET, N-CH, 12 V, 2.9 A,
YJC0003A (PICOSTAR-3)
YJC0003A
R1, R2, R27, R31, R71, R109,
R132, R157, R242, R243
10 CRCW04020000Z0ED RES, 0, 5%, 0.063 W, AEC-
Q200 Grade 0, 0402
0402
R20 1 RC0201JR-7D1KL RES, 1.0 k, 5%, 0.05 W,
0201
0201
R21 1 RC0201JR-0751KL RES, 51 k, 5%, 0.05 W,
0201
0201
R22 1 CRCW04021K00JNED RES, 1.0 k, 5%, 0.063 W,
AEC-Q200 Grade 0, 0402
0402
R24, R28 2 RC0201JR-7D100RL RES, 100, 5%, 0.05 W, 0201 0201
R61, R63, R64, R66, R125, R127,
R128, R130
8 CRCW04020000Z0EDHP RES, 0, 0%, 0.2 W, AEC-
Q200 Grade 0, 0402
0402
R62, R82, R134, R151, R244 5 CRCW0402200RFKED RES, 200, 1%, 0.063 W,
AEC-Q200 Grade 0, 0402
0402
R72, R135 2 CRCW040211K0FKED RES, 11.0 k, 1%, 0.063 W,
AEC-Q200 Grade 0, 0402
0402
R83, R86, R142, R145, R214,
R219, R220, R221
8 CRCW02012K20FKED RES, 2.20 k, 1%, 0.05 W,
0201
0201
R98 1 CRCW20101M00JNEF RES, 1.0 M, 5%, 0.75 W,
AEC-Q200 Grade 0, 2010
2010
R103, R162 2 CRCW04025K76FKED RES, 5.76 k, 1%, 0.063 W,
AEC-Q200 Grade 0, 0402
0402
R104, R159, R160, R163 4 CRCW040210K0FKED RES, 10.0 k, 1%, 0.063 W,
AEC-Q200 Grade 0, 0402
0402
R114, R115, R170, R171, R173,
R174
6 CRCW04022K49FKED RES, 2.49 k, 1%, 0.063 W,
AEC-Q200 Grade 0, 0402
0402
R123 1 CRCW04022K20JNED RES, 2.2 k, 5%, 0.063 W,
AEC-Q200 Grade 0, 0402
0402
R200, R201, R202 3 CRCW0402470RJNED RES, 470, 5%, 0.063 W,
AEC-Q200 Grade 0, 0402
0402
R204, R206 2 CRCW0402100KFKED RES, 100 k, 1%, 0.063 W,
AEC-Q200 Grade 0, 0402
0402
R205 1 CRCW0402309KFKED RES, 309 k, 1%, 0.063 W,
AEC-Q200 Grade 0, 0402
0402
R209 1 CRCW0603316KFKEA RES, 316 k, 1%, 0.1 W,
AEC-Q200 Grade 0, 0603
0603
R210, R212, R239 3 CRCW0603100KFKEA RES, 100 k, 1%, 0.1 W,
AEC-Q200 Grade 0, 0603
0603
Schematic, Board Layout, and Bill of Materials www.ti.com
16 DP83867 Dual-Port TSN PCIe Application Interface Card SNLU317A – SEPTEMBER 2022 – REVISED MAY 2023
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Table 4-1. Bill of Materials (continued)
Designator Qty Part Number Description Footprint
R211, R238 2 CRCW060366K5FKEA RES, 66.5 k, 1%, 0.1 W,
AEC-Q200 Grade 0, 0603
0603
R216 1 CRCW08050000Z0EAHP RES, 0, 5%, 0.333 W, AEC-
Q200 Grade 0, 0805
0805
U1 1 DP83867ERGZR Robust, High Immunity,
Small Form Factor
10/100/1000 Ethernet
Physical Layer Transceiver
VQFN48
U6 1 DP83867ERGZR Gigabit Ethernet PHY
Customized for Harsh
Industrial Environments
with SGMII, RGZ0048B
(VQFN-48)
RGZ0048B
U11 1 TPS82140SILR 17 V Input 2 A
Synchronous Step-Down
Converter MicroSiP Module
With Integrated Inductor,
SIL0008D (uSIP-8)
SIL0008D
U12, U13, U17 3 TLV62568ADRLR 1-A High Efficiency
Synchronous Buck
Converter with Forced PWM
Feature, DRL0006A (SOT-
OTHER-6)
DRL0006A
U14 1 CDCEL913IPWRQ1 Automotive Catalog
Programmable 1-PLL VCXO
Clock Synthesizer with
1.8-V LVCMOS Outputs,
PW0014A (TSSOP-14)
PW0014A
U15, U20 2 TLV70718PDQNT Single Output Low Noise
LDO, 200 mA, Fixed 1.8 V
Output, 2 to 5.5 V Input, 4-
pin X2SON (DQN), -40 to 85
degC, Green (RoHS & no
Sb/Br)
DQN0004A
U18, U19 2 TPS22919DCKR 5.5-V, 1.5-A, 100-mohm
Load Switch with Output
Discharge, DCK0006A
(SOT-SC70-6)
DCK0006A
Y1 1 445I23D25M00000 Crystal, 25 MHz, 20 ppm, 18
pF, SMD
Body 5x3.2mm
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SNLU317A – SEPTEMBER 2022 – REVISED MAY 2023
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5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (September 2022) to Revision A (May 2023) Page
• Deleted TI Confidential NDA banner.................................................................................................................. 1
• Changed board images in Overview section...................................................................................................... 2
• Changed Board Layout figures...........................................................................................................................8
• Changed schematics........................................................................................................................................ 10
• Changed Table 4-1 in Bill of Materials section..................................................................................................15
Revision History www.ti.com
18 DP83867 Dual-Port TSN PCIe Application Interface Card SNLU317A – SEPTEMBER 2022 – REVISED MAY 2023
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STANDARD TERMS FOR EVALUATION MODULES
1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or
documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance
with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License
Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by
neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have
been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications
or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control
techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.
User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)
business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.
2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit
User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty
period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or
replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be
warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
WARNING
Evaluation Kits are intended solely for use by technically qualified,
professional electronics experts who are familiar with the dangers
and application risks associated with handling electrical mechanical
components, systems, and subsystems.
User shall operate the Evaluation Kit within TI’s recommended
guidelines and any applicable legal or environmental requirements
as well as reasonable and customary safeguards. Failure to set up
and/or operate the Evaluation Kit within TI’s recommended
guidelines may result in personal injury or death or property
damage. Proper set up entails following TI’s instructions for
electrical ratings of interface circuits such as input, output and
electrical loads.
NOTE:
EXPOSURE TO ELECTROSTATIC DISCHARGE (ESD) MAY CAUSE DEGREDATION OR FAILURE OF THE EVALUATION
KIT; TI RECOMMENDS STORAGE OF THE EVALUATION KIT IN A PROTECTIVE ESD BAG.

www.ti.com
2
3Regulatory Notices:
3.1 United States
3.1.1 Notice applicable to EVMs not FCC-Approved:
FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software
associated with the kit to determine whether to incorporate such items in a finished product and software developers to write
software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or
otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition
that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.
Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must
operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2 For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•Reorient or relocate the receiving antenna.
•Increase the separation between the equipment and receiver.
•Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
•Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1 For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.