Texas Instruments DP83867E User manual

User's Guide
DP83867 Dual-Port TSN PCIe Application Interface Card
ABSTRACT
This user's guide describes the design, setup, and function of the DP83867 Dual-Port TSN PCIe Application
Interface Card (AIC). The PCIe AIC supports two Ethernet ports with 1000/100/10 Mb/s and is compliant with the
IEEE 802.3 standard. This reference design supports SGMII for MAC connections.
The AIC card can be interfaced to the Intel Tiger Lake H IoT and Alder Lake S reference design through the
PCIe interface.
Table of Contents
1 Introduction.............................................................................................................................................................................2
1.1 Overview............................................................................................................................................................................ 2
1.2 Hardware Features............................................................................................................................................................ 3
1.3 Software Features..............................................................................................................................................................3
1.4 Block Diagram....................................................................................................................................................................4
2 Board Overview...................................................................................................................................................................... 5
2.1 Components.......................................................................................................................................................................5
2.2 PCIe Header Signals..........................................................................................................................................................6
3 Quick Start...............................................................................................................................................................................7
4 Schematic, Board Layout, and Bill of Materials...................................................................................................................8
4.1 Board Layout .....................................................................................................................................................................8
4.2 Schematic........................................................................................................................................................................ 10
4.3 Bill of Materials.................................................................................................................................................................15
5 Revision History................................................................................................................................................................... 18
Trademarks
All trademarks are the property of their respective owners.
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1 Introduction
1.1 Overview
Figure 1-1. DP83867 Dual-Port TSN PCIe Application Interface Card (Top View)
Figure 1-2. DP83867 Dual-Port TSN PCIe Application Interface Card (Bottom View)
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The DP83867 Dual-Port TSN PCIe Application Interface Card plugs into the Intel Tiger Lake or Alder Lake
reference design through the PCIe interface connector. This is an easy way to evaluate the functionality of the
DP83867 Ethernet PHY with the Intel CPU reference design.
Note that the PCIe interface connector is used only as a form factor and uses proprietary interface signal
assignment as given by the Intel reference design. The PCIe form factor carries the SGMII signaling for two
Ethernet ports, MDIO/MDC, power supply and control signals.
The AIC supports MDIO access via dedicated a SMI interface over the PCIe interface. The two DP83867 PHYs
use different MDIO addresses to be addressed via the common interface.
For easy testing and development purpose, the AIC card supports several pin headers for signal probing.
The AIC uses the two RJ45 jack LEDs to show PHY link and speed indication with one LED, and PHY data
transfer activity with the second LED.
Note
The AIC card supports resistor and capacitor mounting options to deploy DP83869 Ethernet PHY
instead of DP83867 on each Ethernet interface port by using the same PHY footprint on the PCB.
1.2 Hardware Features
DP83867 Dual-Port TSN PCIe Application Interface Card features:
• Two DP83867 Gbit Ethernet PHYs
• Two port SGMII MAC interface
• Common serial management interface (SMI) with MDIO/MDC signals to access both DP83867 Ethernet
PHYs
• Two RJ45 jack connector with integrated magnetics
• Two LEDs in each RJ45 jack giving status information for different PHY operation modes
• On-board power generation for all PHYs, sourced by 5 V power supply through the PCIe connector
1.3 Software Features
• All Ethernet PHY MDIO registers can be accessed via PCIe interface.
– DP83867 on Ethernet port 1 has MDIO address #0
– DP83867 on Ethernet port 2 has MDIO address #1
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1.4 Block Diagram
Intel Host Platform
DP83867 Dual-Port TSN PCIe Application Interface Card
DP83867TGL-H
SGMII_INT
SGMII_MDC
SGMII_MDIO
SGMII_RESET
SGMII_AUXTX
SGMII_PPS
SGMII_INT
SGMII_MDC
SGMII_MDIO
SGMII_RESET
SGMII_AUXTX
SGMII_PPS
SGMII TX P/N
SGMII RX P/N
MDIO
MDC
RESET_N
INT_N (OD)
AUXTX / GPIO
PPS / GPIO
XTAL1
XTAL2
MDI[3:0]
GPIO
Port 2
RJ45
SFP Connector
DP83867
SGMII TX P/N
SGMII RX P/N
MDIO
MDC
RESET_N
INT_N (OD)
AUXTX / GPIO
PPS / GPIO
XTAL1
XTAL2
MDI[3:0]
GPIO
Port 1
RJ45
PCIe
x4
RGMII HDR
RGMII TX[3:0]
RGMII RX[3:0]
2x8 HDR
2x8 HDR
TGL-U
SGMII_INT
SGMII_MDC
SGMII_MDIO
SGMII_RESET
SGMII_AUXTX
SGMII_PPS
SGMII_INT
SGMII_MDC
SGMII_MDIO
SGMII_RESET
SGMII_AUXTX
SGMII_PPS
ADL
SGMII_INT
SGMII_MDC
SGMII_MDIO
SGMII_RESET
SGMII_AUXTX
SGMII_PPS
SGMII 2 TX
SGMII 2 RX
SMB_SDA/MDIO
SMB_SCL/MDC
PLT_RST
SGMII 1 TX
SGMII 1 RX
SGMII_INT
SGMII_MDC
SGMII_MDIO
SGMII_RESET
SGMII_AUXTX
SGMII_PPS
SGMII 1 TX
SGMII 1 RX
SMB_SDA/MDIO
SMB_SCL/MDC
PLT_RST
PET/
PER0
PET/
PER1
SGMII 2 TX
SGMII 2 RX
SMB_SDA/MDIO
SMB_SCL/MDC
PLT_RST
SGMII 1 TX
SGMII 1 RX
Figure 1-3. Block Diagram
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2 Board Overview
2.1 Components
Figure 2-1 below gives a quick overview of the AIC board. The marked sections are described in the Table 2-1.
Figure 2-1. Connectors, Jumpers and LEDs
Table 2-1. Component Table
Section Description
1 RJ45 with integrated magnetic G-Bit network connection Port 1 / TSN_0
2 RJ45 with integrated magnetic G-Bit network connection Port 2 / TSN_1
3 DP83867 PHY1 for Port 1
4 DP83867 PHY2 for Port 2
5 25 MHz clock generation for both PHYs
6 Signal connector MISC0 for validation
7 Signal connector MISC1 for validation
8 Signal connector RGMII interface (optional)
9 PCIe interface
10 Power indicator LEDs.
• D10: 3.3V indicator
• D11: VDDIO indicator PHY1
• D12: VDDIO indicator PHY2
• D9: 3.3V indicator for optional SFP+ module
11 VDDIO voltage selector jumper pin-header
• J19: PHY 1
– Pin 1-2: 3.3V
– Pin 2-3: 1.8V (default)
12 VDDIO voltage selector jumper pin-header
• J21: PHY 1
– Pin 1-2: 3.3V
– Pin 2-3: 1.8V (default)
13 Shield/Earth GND for testing.
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2.2 PCIe Header Signals
Please refer to the schematics in section Section 4.2 for the PCIe signal assignment and description. The signal
assignment is following the signal layout of the Intel host platform.
2.2.1 MISC0 Signal Header
The MSIC0 signal header is for debug purpose.
Table 2-2. MISC0 Signal Header for PHY1
Pin Number Signal Description
1 MDC PHY1
3 MDIO PHY1
5 Interrupt PHY1
7 AUXTS PHY1 (Start-of-Frame time stamp)
9 PPS PHY1 (not supported by AIC)
11 Reset PHY1
13, 15 Not connected
2, 4, 6, 8, 10, 12, 14, 16 GND
2.2.2 MISC1 Signal Header
The MSIC1 signal header is for debug purposes.
Table 2-3. MISC1 Signal Header for PHY2
Pin Number Signal Description
1 MDC PHY2
3 MDIO PHY2
5 Interrupt PHY2
7 AUXTS PHY2 (Start-of-Frame time stamp)
9 PPS PHY2 (not supported by AIC)
11 Reset PHY2
13, 15 Not connected
2, 4, 6, 8, 10, 12, 14, 16 GND
2.2.3 RGMII Signal Header
RGMII signal header for PHY1 can be used to connect PHY1 via separate cable connection.
Table 2-4. RGMII Signal Header for PHY1
Pin Number Signal Description
1 TXCLK
2 RXCLK
3 TXCTL
4 RXCTL
7 TXDATA_3
8 RXDATA_3
9 TXDATA_2
10 RXDATA_2
11 TXDATA_1
12 RXDATA_1
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Table 2-4. RGMII Signal Header for PHY1 (continued)
Pin Number Signal Description
13 TXDATA_0
14 RXDATA_0
5, 6, 15, 16 GND
3 Quick Start
1. Power down the Intel host platform (Intel Tiger Lake UP3, Tiger Lake H IoT or Alder Lake S).
2. Plug-in the DP83867 Dual-Port TSN PCIe Application Interface Card into the Intel host platform.
3. Power up the Intel host platform.
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4 Schematic, Board Layout, and Bill of Materials
4.1 Board Layout
Figure 4-1. Assembly Drawing Top Layer
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Figure 4-2. Assembly Drawing Bottom Layer
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4.2 Schematic
TP3
TP4
TP5
GND
+V3.3A_RVP
+V3.3A_AUX
+V12A
+V3.3A
+V1.8A
TP6
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
BOT
B11
TOP
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
EC1
A32
EDGE_CONN_PCIe-x4
GND GND
+V12A +V12A
+V3.3A_RVP
+V3.3A_RVP
+V3.3A_AUX
X1_PRSNT_N
PRSNT_N
PRSNT_N
SGMII1_TX_D_P
SGMII1_TX_D_N
SGMII2_TX_D_P
SGMII2_TX_D_N
0R12
51kR21
100R24
100R28 GND
SGMII1_RX_D_N
SGMII2_RX_D_P
SGMII2_RX_D_N
10uF
C1
0.1uF
C2
GND
1.0kR20
+V3.3A_AUX
C3
10uF 0.1uF
C4
GND
SGMII1_RX_D_P
SGMII1_SFP_RX_D_P
SGMII1_SFP_RX_D_N
SGMII1_SFP_TX_D_P
SGMII1_SFP_TX_D_N
12
3 4
5 6
7 8
9 10
11 12
13 14
15 16
J1
PRPC008DAAN-RC
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
J3
GND
GND
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
J2
PRPC008DAAN-RC
MISC0_HDR
MISC1_HDR
RGMII_HDR
0R5
0R6
0R7
0R9
0R15
0R16
0R17
0R19
RGMII_INT
RGMII_RESET
SGMII_INT
GBE_MDC_1
GBE_MDIO_1
SGMII_RESET
RGMII_TXCLK
RGMII_TXCTL
RGMII_TXDATA_3
RGMII_TXDATA_2
RGMII_TXDATA_1
RGMII_TXDATA_0
RGMII_RXCLK
RGMII_RXCTL
RGMII_RXDATA_3
RGMII_RXDATA_2
RGMII_RXDATA_1
RGMII_RXDATA_0
GND
PRPC008DAAN-RC
GND
TP1
RGMII_PPS
GND
SGMII_PPS
GND
SMB_CLK
SMB_DAT
SMB_CLK
SMB_DAT
0R4
0R3
0R13
0R14
SGMII_PPS
RGMII_AUXTS
SGMII_AUXTS
4
SGMII_AUXTS
1
2
3
J4
61300411121
GND
PHY1 Signals
PHY2 Signals
PHY1_GPIO_1
PHY1_GPIO_0
PHY1_LED_1
RGMII_AUXTS
RGMII_PPS
1
5 4 3 2
J6
142-0701-201
GND
4
PHY1_CLK_OUT
1
2
3
J5
61300411121
GND
PHY2_GPIO_1
PHY2_GPIO_0
PHY2_LED_1
1
5 4 3 2
J7
142-0701-201
GND
PHY2_CLK_OUT
TP9
TP8
SGMII1_SFP_MDC
SGMII1_SFP_MDIO
GBE_MDC_0
GBE_MDIO_0
PET3_R_D_P
PET3_R_D_N
PET2_R_D_P
PET2_R_D_N
PET1_R_D_P
PET1_R_D_N
PET0_R_D_P
PET0_R_D_N
PER0_C_D_P
PER0_C_D_N
PER1_C_D_P
PER1_C_D_N
PER2_C_D_P
PER2_C_D_N
PER3_C_D_P
PER3_C_D_N
PCIE_REFCLK_D_P
PCIE_REFCLK_D_N
PERST_N
RGMII_RESET
SGMII_RESET
GBE_MDC_0
TP2
GBE_MDC_0
GBE_MDIO_0
GBE_MDIO_0
0
R1
0
R2
0
R10
0
R11
0R242
0R243
0
R47
0
R50
0R54
0R56
0
R48
0
R51
0R55
0R57
PET_0_2_P
PET_0_2_N
PER_0_2_P PER_0_2_N
0
R27
0R31
20.0k
R8
20.0k
8R1
20.0kR58 20.0kR59
1.0kR22
1.0kR23
+V3.3A
X1_PRSNT_N
0
R249
C134
10uF 0.1uF
C135
+V3.3A_RVP
GND
0R25
0R26
0R29
0R30
0.1uFC78
0.1uFC79
C80 0.1uF
0.1uFC81
0R33
0R36
0R40
0R41
0R44
0R45
0R52
0R53
0R34
0R32
0R35
0R37
SI_P
SI_N
GND
TX_D -> SI (input to '67)
SI_P
SI_N
TX_D -> SI (input to '67)
C30 0
C31 0
C32 0
C33 0
CAD NOTE:
3 PAD, PLACE CLOSE TO
EDGE CONNECTOR
CAD NOTE:
3 PAD, PLACE CLOSE TO
EDGE CONNECTOR
CAD NOTE:
3 PAD, PLACE CLOSE TO
EDGE CONNECTOR
Figure 4-3. Schematic : PCIe Host Interface
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