Texas Instruments SimpleLink CC2652PSIP User manual

CC2652PSIP SimpleLink™ Multiprotocol 2.4-GHz Wireless System-in-Package
With Integrated Power Amplifier
1 Features
Wireless microcontroller
• Powerful 48-MHz Arm® Cortex®-M4F processor
• 352KB flash program memory
• 256KB of ROM for protocols and library functions
• 8KB of cache SRAM
• 80KB of ultra-low leakage SRAM with parity for
high-reliability operation
• Dynamic multiprotocol manager (DMM) driver
• Programmable radio includes support for 2-
(G)FSK, 4-(G)FSK, MSK, OOK, Bluetooth® 5.2
Low Energy, IEEE 802.15.4 PHY and MAC
• Supports over-the-air upgrade (OTA)
Ultra-low power sensor controller
• Autonomous MCU with 4KB of SRAM
• Sample, store, and process sensor data
• Fast wake-up for low-power operation
• Software defined peripherals; capacitive touch,
flow meter, LCD
Low power consumption
• MCU consumption:
– 3.5 mA active mode, CoreMark
– 74 μA/MHz running CoreMark
– 1 μA standby mode, RTC, 80KB RAM
– 160 nA shutdown mode, wake-up on pin
• Ultra low-power sensor controller consumption:
– 30.1 μA in 2 MHz mode
– 808 μA in 24 MHz mode
• Radio Consumption:
– 7.3 mA RX at 2.4 GHz
– 7.9 mA TX at 0 dBm
– 10.9 mA TX at +5 dBm
– 33 mA TX at +10 dBm
Wireless protocol support
•Thread, Zigbee®, Matter
•Bluetooth® 5.2 Low Energy
•SimpleLink™ TI 15.4-stack
• Proprietary systems
High performance radio
• -103 dBm sensitivity for Bluetooth® Low Energy
125-kbps LE Coded PHY
• Output power up to +10 dBm with temperature
compensation
Regulatory compliance
• Regulatory certification for compliance with
worldwide radio frequency:
– ETSI RED (Europe)
– ISED (Canada)
– FCC (USA)
MCU peripherals
• Digital peripherals can be routed to any of 30
GPIOs
• Four 32-bit or eight 16-bit general-purpose timers
• 12-bit ADC, 200 kSamples/s, 8 channels
• 8-bit DAC
• Two comparators
• Programmable current source
• Two UART, two SSI, I2C, I2S
• Real-time clock (RTC)
• Integrated temperature and battery monitor
Security enablers
• AES 128- and 256-bit cryptographic accelerator
• ECC and RSA public key hardware accelerator
• SHA2 Accelerator (full suite up to SHA-512)
• True random number generator (TRNG)
Development tools and software
•LP-CC2652RSIP Development Kit
•SimpleLink™ CC13xx and CC26xx Software
Development Kit (SDK)
•SmartRF™ Studio for simple radio configuration
• Sensor Controller Studio for building low-power
sensing applications
•SysConfig system configuration tool
Operating range
• On-chip buck DC/DC converter
• 1.8-V to 3.8-V single supply voltage
• Tj: -40 to +105°C
Package
• 7-mm × 7-mm MOT (30 GPIOs)
• RoHS-compliant package
CC2652PSIP
SWRS263A – FEBRUARY 2021 – REVISED JUNE 2022
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

2 Applications
• 2400 to 2480 MHz ISM and SRD systems 1
•Building automation
– Building security systems – motion detector,
electronic smart lock, door and window sensor,
garage door system, gateway
– HVAC – thermostat, wireless environmental
sensor, HVAC system controller, gateway
– Fire safety system – smoke and heat detector,
fire alarm control panel (FACP)
– Elevators and escalators – elevator main
control panel for elevators and escalators
•Industrial transport – asset tracking
•Factory automation and control
•Medical
•Communication equipment
–Wired networking – wireless LAN or Wi-Fi
access points, edge router , small business
router
•Personal electronics
–Portable electronics – RF smart remote control
–Home theater & entertainment – smart
speakers, smart display, set-top box
–Gaming – electronic and robotic toys
–Wearables (non-medical) – smart trackers,
smart clothing
3 Description
The SimpleLink™ CC2652PSIP is a System-in-Package (SiP) certified module, multiprotocol 2.4 GHz wireless
microcontroller (MCU) supporting Thread, Zigbee®, Bluetooth® 5.2 Low Energy, IEEE 802.15.4, IPv6-enabled
smart objects (6LoWPAN), proprietary systems, including the TI 15.4-Stack (2.4 GHz), and concurrent
multiprotocol through a Dynamic Multiprotocol Manager (DMM) driver. The device is optimized for low-power
wireless communication and advanced sensing in building security systems, HVAC, medical, wired networking,
portable electronics, home theater & entertainment, and connected peripherals markets. The highlighted
features of this device include:
• Small 7-mm x 7-mm certified system-in-package module 2.4GHz with integrated DCDC components, balun,
and crystal oscillators
• Wide flexibility of protocol stack support in the SimpleLink™ CC13xx and CC26xx Software Development Kit
(SDK).
• Coin-cell operation at +10 dBm with transmit current consumption of 33 mA.
• Longer battery life wireless applications with low standby current of 1 µA with full RAM retention.
• Industrial temperature ready with lowest standby current of 11 µA at 105 ⁰C.
• Advanced sensing with a programmable, autonomous ultra-low power Sensor Controller CPU with fast
wake-up capability. As an example, the sensor controller is capable of 1-Hz ADC sampling at 1 µA system
current.
• Low SER (Soft Error Rate) FIT (Failure-in-time) for long operation lifetime with no disruption for industrial
markets with always-on SRAM parity against corruption due to potential radiation events.
• Dedicated software controlled radio controller (Arm® Cortex®-M0) providing flexible low-power RF transceiver
capability to support multiple physical layers and RF standards.
• Excellent radio sensitivity and robustness (selectivity and blocking) performance for Bluetooth ® Low Energy
(-103 dBm for 125-kbps LE Coded PHY).
The CC2652PSIP device is part of the SimpleLink™ MCU platform, which consists of Wi-Fi®, Bluetooth Low
Energy, Thread, Zigbee, Sub-1 GHz MCUs, and host MCUs that all share a common, easy-to-use development
environment with a single core software development kit (SDK) and rich tool set. A one-time integration of the
SimpleLink™ platform enables you to add any combination of the portfolio’s devices into your design, allowing
100 percent code reuse when your design requirements change. For more information, visit SimpleLink™ MCU
platform.
Device Information
PART NUMBER(1) PACKAGE BODY SIZE (NOM)
CC2652PSIPMOTR QFM (73) 7.00 mm × 7.00 mm
(1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section
13, or see the TI website.
1See RF Core for additional details on supported protocol standards, modulation formats, and data rates.
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4 Functional Block Diagram
Figure 4-1 shows the functional block diagram of the CC2652PSIP module.
48-MHz
Crystal Oscillator
32.768-kHz
Crystal Oscillator
RF
Switch
RF
(50 ,
2.4 GHz)
GND
(1.8 V to 3.8 V) VDDS
User DIO_0-31
RESET_N
JTAG
(1.8 V to 3.8 V) VDDS_PU
CC2652P
DCDC
Passives
+5-dBm
IPC
+10-dBm
IPC
2.4 GHz
ANT
Figure 4-1. CC2652PSIP Block Diagram
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Figure 4-2 shows an overview of the CC2652PSIP hardware.
Figure 4-2. CC2652PSIP Hardware Overview
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 2
3 Description.......................................................................2
4 Functional Block Diagram.............................................. 3
5 Revision History.............................................................. 5
6 Device Comparison......................................................... 6
7 Terminal Configuration and Functions..........................7
7.1 Pin Diagram................................................................ 7
7.2 Signal Descriptions – SIP Package............................ 8
7.3 Connections for Unused Pins and Modules................9
8 Specifications................................................................ 10
8.1 Absolute Maximum Ratings...................................... 10
8.2 ESD Ratings............................................................. 10
8.3 Recommended Operating Conditions.......................10
8.4 Power Supply and Modules...................................... 10
8.5 Power Consumption - Power Modes.........................11
8.6 Power Consumption - Radio Modes......................... 12
8.7 Nonvolatile (Flash) Memory Characteristics............. 12
8.8 Thermal Resistance Characteristics......................... 12
8.9 RF Frequency Bands................................................ 13
8.10 Bluetooth Low Energy - Receive (RX).................... 13
8.11 Bluetooth Low Energy - Transmit (TX).................... 16
8.12 Zigbee and Thread - IEEE 802.15.4-2006 2.4
GHz (OQPSK DSSS1:8, 250 kbps) - RX.................... 17
8.13 Zigbee and Thread - IEEE 802.15.4-2006 2.4
GHz (OQPSK DSSS1:8, 250 kbps) - TX.....................18
8.14 Timing and Switching Characteristics..................... 18
8.15 Peripheral Characteristics.......................................23
8.16 Typical Characteristics............................................30
9 Detailed Description......................................................38
9.1 Overview................................................................... 38
9.2 System CPU............................................................. 38
9.3 Radio (RF Core)........................................................39
9.4 Memory..................................................................... 39
9.5 Sensor Controller...................................................... 41
9.6 Cryptography............................................................ 42
9.7 Timers....................................................................... 43
9.8 Serial Peripherals and I/O.........................................44
9.9 Battery and Temperature Monitor............................. 44
9.10 µDMA......................................................................44
9.11 Debug......................................................................44
9.12 Power Management................................................45
9.13 Clock Systems........................................................ 46
9.14 Network Processor..................................................46
9.15 Device Certification and Qualification..................... 47
9.16 Module Markings.....................................................49
9.17 End Product Labeling..............................................49
9.18 Manual Information to the End User....................... 49
10 Application, Implementation, and Layout................. 50
10.1 Application Information........................................... 50
10.2 Device Connection and Layout Fundamentals....... 51
10.3 PCB Layout Guidelines...........................................51
10.4 Reference Designs................................................. 55
11 Environmental Requirements and SMT
Specifications ...............................................................56
11.1 PCB Bending...........................................................56
11.2 Handling Environment.............................................56
11.3 Storage Condition................................................... 56
11.4 PCB Assembly Guide..............................................56
11.5 Baking Conditions................................................... 57
11.6 Soldering and Reflow Condition..............................58
12 Device and Documentation Support..........................59
12.1 Device Nomenclature..............................................59
12.2 Tools and Software................................................. 59
12.3 Documentation Support.......................................... 62
12.4 Support Resources................................................. 62
12.5 Trademarks.............................................................62
12.6 Electrostatic Discharge Caution..............................63
12.7 Glossary..................................................................63
13 Mechanical, Packaging, and Orderable
Information.................................................................... 64
13.1 Packaging Information............................................ 64
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (February 2021) to Revision A (May 2022) Page
• Updated numbering of sections, figures, and tables throughout the data sheet.................................................1
• Updated formatting throughout data sheet to match current documentation standards.....................................1
• Devices are now PRODUCTION DATA.............................................................................................................. 1
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6 Device Comparison
Device
RADIO SUPPORT
FLASH
(KB)
RAM +
Cache (KB) GPIO
PACKAGE SIZE
Sub-1 GHz Prop.
2.4 GHz Prop. Wireless M-Bus
Wi-SUN® Sidewalk
Bluetooth® LE ZigBee Thread
Multiprotocol
+20 dBm PA 4 x 4 mm VQFN (32) 5 x 5 mm VQFN (32) 5 x 5 mm VQFN (40) 7 x 7 mm VQFN (48)
CC1310 X X 32-128 16-20 + 8 10-30 X X X
CC1311R3 X X 352 32 + 8 22-30 X X
CC1311P3 X X X 352 32 + 8 26 X
CC1312R X X X 352 80 + 8 30 X
CC1312R7 X X X X X 704 144 + 8 30 X
CC1352R X X X X X X X X 352 80 + 8 28 X
CC1352P X X X X X X X X X 352 80 + 8 26 X
CC1352P7 X X X X X X X X X X 704 144 + 8 26 X
CC2640R2F X 128 20 + 8 10-31 X X X
CC2642R X 352 80 + 8 31 X
CC2642R-Q1 X 352 80 + 8 31 X
CC2651R3 X X X 352 32 + 8 23-31 X X
CC2651P3 X X X X 352 32 + 8 22-26 X X
CC2652R X X X X X 352 80 + 8 31 X
CC2652RB X X X X X 352 80 + 8 31 X
CC2652R7 X X X X X 704 144 + 8 31 X
CC2652P X X X X X X 352 80 + 8 26 X
CC2652P7 X X X X X X 704 144 + 8 26 X
Module
Antenna RADIO SUPPORT Certifications
FLASH
(KB)
RAM +
Cache (KB) GPIO
Package Size
External Integrated Bluetooth® LE ZigBee
+10 dBm PA
FCC/IC CE Japan 7 x 7 QFM (73) 7 x 7 QFM (59) 16.9 x 11.0 QFM (29)
CC2650MODA X X X X X X 128 20+8 15 X
CC2651R3SIPA X X X X X X 352 32 + 8 32 X
CC2652RSIP X X X X X 352 80 + 8 32 X
CC2652PSIP X X X X X X 352 80 + 8 30 X
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7 Terminal Configuration and Functions
7.1 Pin Diagram
CC2652PSIP
DIO_28
DIO_25
2
1
DIO_26
DIO_27
DIO_31 DIO_18 DIO_19 DIO_20 DIO_21
DIO_22 DIO_23
DIO_24
VDDS
VDDS_PU
DIO_4
DIO_1
DIO_2
GND RF GND GND
NC NC
3
4
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20 21 22 23
24
25
36
37
35
34
33
32
31
30
29
28
27
26
48 47 46 45 44 43 42 41 40 39
38
GND
nRESET
DIO_29
NC
GND
DIO_30
GND
GND
GND
GND
JTAG_TCKC
DIO_17
DIO_16
DIO_15
JTAG_TMSC
DIO_13
DIO_14
DIO_11
DIO_12
DIO_9
DIO_10
DIO_7
DIO_8
DIO_6
DIO_5
49
54
59
64
69
50
55
60
65
70
51
56
61
66
71
52
57
62
67
72
53
58
63
68
73
Figure 7-1. MOT (7-mm × 7-mm) Pinout, 0.5-mm Pitch (Top View)
The following I/O pins marked in Figure 7-1 in bold have high-drive capabilities:
• Pin 23, DIO_5
• Pin 24, DIO_6
• Pin 25, DIO_7
• Pin 34, JTAG_TMSC
• Pin 36, DIO_16
• Pin 37, DIO_17
The following I/O pins marked in Figure 7-1 in italics have analog capabilities:
• Pin 1, DIO_26
• Pin 2, DIO_27
• Pin 3, DIO_28
• Pin 7, DIO_29
• Pin 8, DIO_30
• Pin 44, DIO_23
• Pin 45, DIO_24
• Pin 48, DIO_25
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7.2 Signal Descriptions – SIP Package
Table 7-1. Signal Descriptions – SIP Package
PIN I/O TYPE DESCRIPTION
NAME NO.
DIO_1 21 I/O Digital GPIO
DIO_10 28 I/O Digital GPIO
DIO_11 29 I/O Digital GPIO
DIO_12 30 I/O Digital GPIO
DIO_13 31 I/O Digital GPIO
DIO_14 32 I/O Digital GPIO
DIO_15 33 I/O Digital GPIO
DIO_16 36 I/O Digital GPIO, JTAG_TDO, high-drive capability
DIO_17 37 I/O Digital GPIO, JTAG_TDI, high-drive capability
DIO_18 39 I/O Digital GPIO
DIO_19 40 I/O Digital GPIO
DIO_2 20 I/O Digital GPIO
DIO_20 41 I/O Digital GPIO
DIO_21 42 I/O Digital GPIO
DIO_22 43 I/O Digital GPIO
DIO_23 44 I/O Digital or Analog GPIO, analog capability
DIO_24 45 I/O Digital or Analog GPIO, analog capability
DIO_25 48 I/O Digital or Analog GPIO, analog capability
DIO_26 1 I/O Digital or Analog GPIO, analog capability
DIO_27 2 I/O Digital or Analog GPIO, analog capability
DIO_28 3 I/O Digital or Analog GPIO, analog capability
DIO_29 7 I/O Digital or Analog GPIO, analog capability
DIO_30 8 I/O Digital or Analog GPIO, analog capability
DIO_31(1) 38 I/O Digital Supports only peripheral functionality. Does not support general
purpose I/O functionality.
DIO_4 22 I/O Digital GPIO
DIO_5 23 I/O Digital GPIO, high-drive capability
DIO_6 24 I/O Digital GPIO, high-drive capability
DIO_7 25 I/O Digital GPIO, high-drive capability
DIO_8 26 I/O Digital GPIO
DIO_9 27 I/O Digital GPIO
GND 5 — — GND
GND 9 — — GND
GND 10 — — GND
GND 11 — — GND
GND 12 — — GND
GND 13 — — GND
GND 16 — — GND
GND 17 — — GND
GND 19 — — GND
GND 49-73 — — GND
NC 6 — — No Connect
NC 14 — — No Connect
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Table 7-1. Signal Descriptions – SIP Package (continued)
PIN I/O TYPE DESCRIPTION
NAME NO.
NC 15 — — No Connect
nRESET 4 I Digital Reset, active low. Internal pullup resistor to VDDS_PU
RF 18 — RF 50 ohm RF port
JTAG_TCKC 35 I Digital JTAG_TCKC
JTAG_TMSC 34 I/O Digital JTAG_TMSC, high-drive capability
VDDS 46 — Power 1.8-V to 3.8-V main SIP supply
VDDS_PU 47 — Power Power to reset internal pullup resistor
(1) PORT_ID = 0x00 is not supported. See the SimpleLink™ CC13x2, CC26x2 Wireless MCU Technical Reference Manual for further
details.
7.3 Connections for Unused Pins and Modules
Table 7-2. Connections for Unused Pins – SIP Package
FUNCTION SIGNAL NAME PIN NUMBER ACCEPTABLE PRACTICE(1) PREFERRED
PRACTICE(1)
GPIO DIO_n
1-3
7-8
20-33
36-45
48
NC or GND NC
No Connects NC 6, 14-15 NC NC
(1) NC = No connect
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN MAX UNIT
VDDS(3) Supply voltage –0.3 4.1 V
Voltage on any digital pin(4) (5) –0.3 VDDS + 0.3, max 4.1 V
Vin Voltage on ADC input
Voltage scaling enabled –0.3 VDDS
VVoltage scaling disabled, internal reference –0.3 1.49
Voltage scaling disabled, VDDS as reference –0.3 VDDS / 2.9
Input level, RF pin 5 dBm
Tstg Storage temperature –40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to ground, unless otherwise noted.
(3) VDDS_DCDC, VDDS2 and VDDS3 must be at the same potential as VDDS.
(4) Including analog capable DIOs.
(5) Injection current is not supported on any GPIO pin
8.2 ESD Ratings
VALUE UNIT
VESD Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS001(1) All pins ±1000 V
Charged device model (CDM), per JESD22-C101(2) All pins ±500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Operating junction temperature(1) –40 105 °C
Operating supply voltage (VDDS) 1.8 3.8 V
Rising supply voltage slew rate 0 100 mV/µs
Falling supply voltage slew rate 0 20 mV/µs
(1) For thermal resistance characteristics refer to Section 8.8.
8.4 Power Supply and Modules
over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
VDDS Power-on-Reset (POR) threshold 1.1 1.5 V
VDDS Brown-out Detector (BOD) Rising threshold 1.77 V
VDDS Brown-out Detector (BOD), before initial boot (1) Rising threshold 1.70 V
VDDS Brown-out Detector (BOD) Falling threshold 1.75 V
(1) Brown-out Detector is trimmed at initial boot, value is kept until device is reset by a POR reset or the nRESET pin
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8.5 Power Consumption - Power Modes
When measured on the CC2652xSIP-EM reference design with Tc = 25 °C, VDDS = 3.0 V with DC/DC enabled unless
otherwise noted.
PARAMETER TEST CONDITIONS TYP UNIT
Core Current Consumption
Icore
Reset and Shutdown Reset. nRESET pin asserted or VDDS below power-on-reset threshold(1) 30 µA
Shutdown. No clocks running, no retention 160 nA
Standby
without cache retention
RTC running, CPU, 80KB RAM and (partial) register retention.
RCOSC_LF 0.99 µA
RTC running, CPU, 80KB RAM and (partial) register retention
XOSC_LF 1.15 µA
Standby
with cache retention
RTC running, CPU, 80KB RAM and (partial) register retention.
RCOSC_LF 3.36 µA
RTC running, CPU, 80KB RAM and (partial) register retention.
XOSC_LF 3.47 µA
Idle Supply Systems and RAM powered
RCOSC_HF 708 µA
Active MCU running CoreMark at 48 MHz
RCOSC_HF 3.5 mA
Peripheral Current Consumption
Iperi
Peripheral power
domain Delta current with domain enabled 102
µA
Serial power domain Delta current with domain enabled 7.56
RF Core Delta current with power domain enabled,
clock enabled, RF core idle 221
µDMA Delta current with clock enabled, module is idle 67.1
Timers Delta current with clock enabled, module is idle(4) 85.1
I2C Delta current with clock enabled, module is idle 10.6
I2S Delta current with clock enabled, module is idle 27.6
SSI Delta current with clock enabled, module is idle 90.2
UART Delta current with clock enabled, module is idle(2) 175.9
CRYPTO (AES) Delta current with clock enabled, module is idle(3) 26.9
PKA Delta current with clock enabled, module is idle 88.9
TRNG Delta current with clock enabled, module is idle 37.4
Sensor Controller Engine Consumption
ISCE
Active mode 24 MHz, infinite loop 808 µA
Low-power mode 2 MHz, infinite loop 30.1
(1) CC2652xSIP integrates a 100 kΩ pull-up resistor on nRESET
(2) Only one UART running
(3) Only one SSI running
(4) Only one GPTimer running
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8.6 Power Consumption - Radio Modes
When measured on the CC2652xSIP-EM reference design with Tc = 25 °C, VDDS = 3.0 V with DC/DC enabled unless
otherwise noted.
High-power PA connected to VDDS unless otherwise noted.
PARAMETER TEST CONDITIONS TYP UNIT
Radio receive current 2440 MHz 7.3 mA
Radio transmit current
2.4 GHz PA (Bluetooth Low Energy)
0 dBm output power setting
2440 MHz 7.9 mA
+5 dBm output power setting
2440 MHz 10.9 mA
Radio transmit current
High-power PA, 10 dBm
configuration
+10 dBm output power setting
2440 MHz VDDR = 1.67 V 33.0 mA
8.7 Nonvolatile (Flash) Memory Characteristics
Over operating free-air temperature range and VDDS = 3.0 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Flash sector size 8 KB
Supported flash erase cycles before failure, full bank(1) (5) 30 k Cycles
Supported flash erase cycles before failure, single sector(2) 60 k Cycles
Maximum number of write operations per row before sector
erase(3) 83 Write Operations
Flash retention 105 °C 11.4 Years
Flash sector erase current Average delta current 9.7 mA
Flash sector erase time(4) Zero cycles 10 ms
30k cycles 4000 ms
Flash write current Average delta current, 4 bytes at a time 5.3 mA
Flash write time(4) 4 bytes at a time 21.6 µs
(1) A full bank erase is counted as a single erase cycle on each sector
(2) Up to 4 customer-designated sectors can be individually erased an additional 30k times beyond the baseline bank limitation of 30k
cycles
(3) Each wordline is 2048 bits (or 256 bytes) wide. This limitation corresponds to sequential memory writes of 4 (3.1) bytes minimum
per write over a whole wordline. If additional writes to the same wordline are required, a sector erase is required once the maximum
number of write operations per row is reached.
(4) This number is dependent on Flash aging and increases over time and erase cycles
(5) Aborting flash during erase or program modes is not a safe operation.
8.8 Thermal Resistance Characteristics
THERMAL METRIC(1)
PACKAGE
UNIT
MOT
(SIP)
73 PINS
RθJA Junction-to-ambient thermal resistance 48.7 °C/W(2)
RθJC(top) Junction-to-case (top) thermal resistance 12.4 °C/W(2)
RθJB Junction-to-board thermal resistance 32.2 °C/W(2)
ψJT Junction-to-top characterization parameter 0.40 °C/W(2)
ψJB Junction-to-board characterization parameter 32.0 °C/W(2)
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) °C/W = degrees Celsius per watt.
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8.9 RF Frequency Bands
Over operating free-air temperature range (unless otherwise noted).
PARAMETER MIN TYP MAX UNIT
Frequency bands 2360 2500 MHz
8.10 Bluetooth Low Energy - Receive (RX)
Measured on the CC2652xSIP-EM reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled and high power PA connected to VDDS unless otherwise noted.
All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is
measured at a dedicated antenna connection. All measurements are performed conducted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
125 kbps (LE Coded)
Receiver sensitivity Differential mode. BER = 10–3 –103 dBm
Receiver saturation Differential mode. BER = 10–3 >5 dBm
Frequency error tolerance Difference between the incoming carrier frequency and
the internally generated carrier frequency > (–300 / 300) kHz
Data rate error tolerance Difference between incoming data rate and the internally
generated data rate (37-byte packets) > (–320 / 240) ppm
Data rate error tolerance Difference between incoming data rate and the internally
generated data rate (255-byte packets) > (–100 / 100) ppm
Co-channel rejection(1) Wanted signal at –79 dBm, modulated interferer in
channel, BER = 10–3 –1.5 dB
Selectivity, ±1 MHz(1) Wanted signal at –79 dBm, modulated interferer at ±1
MHz, BER = 10–3 8 / 4.5(2) dB
Selectivity, ±2 MHz(1) Wanted signal at –79 dBm, modulated interferer at ±2
MHz, BER = 10–3 44 / 37(2) dB
Selectivity, ±3 MHz(1) Wanted signal at –79 dBm, modulated interferer at ±3
MHz, BER = 10–3 46 / 44(2) dB
Selectivity, ±4 MHz(1) Wanted signal at –79 dBm, modulated interferer at ±4
MHz, BER = 10–3 44 / 46(2) dB
Selectivity, ±6 MHz(1) Wanted signal at –79 dBm, modulated interferer at ±6
MHz, BER = 10–3 48 / 44(2) dB
Selectivity, ±7 MHz Wanted signal at –79 dBm, modulated interferer at ≥ ±7
MHz, BER = 10–3 51 / 45(2) dB
Selectivity, Image frequency(1) Wanted signal at –79 dBm, modulated interferer at image
frequency, BER = 10–3 37 dB
Selectivity, Image frequency ±1
MHz(1)
Note that Image frequency + 1 MHz is the Co- channel
–1 MHz. Wanted signal at –79 dBm, modulated interferer
at ±1 MHz from image frequency, BER = 10–3
4.5 / 44 (2) dB
500 kbps (LE Coded)
Receiver sensitivity Differential mode. BER = 10–3 –98 dBm
Receiver saturation Differential mode. BER = 10–3 > 5 dBm
Frequency error tolerance Difference between the incoming carrier frequency and
the internally generated carrier frequency > (–300 / 300) kHz
Data rate error tolerance Difference between incoming data rate and the internally
generated data rate (37-byte packets) > (–350 / 350) ppm
Data rate error tolerance Difference between incoming data rate and the internally
generated data rate (255-byte packets) > (–150 / 175) ppm
Co-channel rejection(1) Wanted signal at –72 dBm, modulated interferer in
channel, BER = 10–3 –3.5 dB
Selectivity, ±1 MHz(1) Wanted signal at –72 dBm, modulated interferer at ±1
MHz, BER = 10–3 8 / 4(2) dB
Selectivity, ±2 MHz(1) Wanted signal at –72 dBm, modulated interferer at ±2
MHz, BER = 10–3 43 / 35(2) dB
Selectivity, ±3 MHz(1) Wanted signal at –72 dBm, modulated interferer at ±3
MHz, BER = 10–3 46 / 46(2) dB
Selectivity, ±4 MHz(1) Wanted signal at –72 dBm, modulated interferer at ±4
MHz, BER = 10–3 45 / 47(2) dB
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Measured on the CC2652xSIP-EM reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled and high power PA connected to VDDS unless otherwise noted.
All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is
measured at a dedicated antenna connection. All measurements are performed conducted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Selectivity, ±6 MHz(1) Wanted signal at –72 dBm, modulated interferer at ≥ ±6
MHz, BER = 10–3 46 / 45(2) dB
Selectivity, ±7 MHz Wanted signal at –72 dBm, modulated interferer at ≥ ±7
MHz, BER = 10–3 49 / 45(2) dB
Selectivity, Image frequency(1) Wanted signal at –72 dBm, modulated interferer at image
frequency, BER = 10–3 35 dB
Selectivity, Image frequency ±1
MHz(1)
Note that Image frequency + 1 MHz is the Co- channel
–1 MHz. Wanted signal at –72 dBm, modulated interferer
at ±1 MHz from image frequency, BER = 10–3
4 / 46(2) dB
1 Mbps (LE 1M)
Receiver sensitivity Differential mode. BER = 10–3 –96 dBm
Receiver saturation Differential mode. BER = 10–3 > 5 dBm
Frequency error tolerance Difference between the incoming carrier frequency and
the internally generated carrier frequency > (–350 / 350) kHz
Data rate error tolerance Difference between incoming data rate and the internally
generated data rate (37-byte packets) > (–650 / 750) ppm
Co-channel rejection(1) Wanted signal at –67 dBm, modulated interferer in
channel, BER = 10–3 –6 dB
Selectivity, ±1 MHz(1) Wanted signal at –67 dBm, modulated interferer at ±1
MHz, BER = 10–3 7 / 4(2) dB
Selectivity, ±2 MHz(1) Wanted signal at –67 dBm, modulated interferer at ±2
MHz,BER = 10–3 39 / 33(2) dB
Selectivity, ±3 MHz(1) Wanted signal at –67 dBm, modulated interferer at ±3
MHz, BER = 10–3 36 / 40(2) dB
Selectivity, ±4 MHz(1) Wanted signal at –67 dBm, modulated interferer at ±4
MHz, BER = 10–3 36 / 45(2) dB
Selectivity, ±5 MHz or more(1) Wanted signal at –67 dBm, modulated interferer at ≥ ±5
MHz, BER = 10–3 40 dB
Selectivity, image frequency(1) Wanted signal at –67 dBm, modulated interferer at image
frequency, BER = 10–3 33 dB
Selectivity, image frequency
±1 MHz(1)
Note that Image frequency + 1 MHz is the Co- channel
–1 MHz. Wanted signal at –67 dBm, modulated interferer
at ±1 MHz from image frequency, BER = 10–3
4 / 41(2) dB
Out-of-band blocking(3) 30 MHz to 2000 MHz –10 dBm
Out-of-band blocking 2003 MHz to 2399 MHz –18 dBm
Out-of-band blocking 2484 MHz to 2997 MHz –12 dBm
Out-of-band blocking 3000 MHz to 12.75 GHz –2 dBm
Intermodulation
Wanted signal at 2402 MHz, –64 dBm. Two interferers
at 2405 and 2408 MHz respectively, at the given power
level
–42 dBm
Spurious emissions,
30 to 1000 MHz(4) Measurement in a 50-Ω single-ended load. < –59 dBm
Spurious emissions,
1 to 12.75 GHz(4) Measurement in a 50-Ω single-ended load. < –47 dBm
RSSI dynamic range 70 dB
RSSI accuracy ±4 dB
2 Mbps (LE 2M)
Receiver sensitivity Differential mode. Measured at SMA connector, BER =
10–3 –90 dBm
Receiver saturation Differential mode. Measured at SMA connector, BER =
10–3 > 5 dBm
Frequency error tolerance Difference between the incoming carrier frequency and
the internally generated carrier frequency > (–500 / 500) kHz
Data rate error tolerance Difference between incoming data rate and the internally
generated data rate (37-byte packets) > (–700 / 750) ppm
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Measured on the CC2652xSIP-EM reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled and high power PA connected to VDDS unless otherwise noted.
All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is
measured at a dedicated antenna connection. All measurements are performed conducted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Co-channel rejection(1) Wanted signal at –67 dBm, modulated interferer in
channel,BER = 10–3 –7 dB
Selectivity, ±2 MHz(1) Wanted signal at –67 dBm, modulated interferer at ±2
MHz, Image frequency is at –2 MHz, BER = 10–3 8 / 4(2) dB
Selectivity, ±4 MHz(1) Wanted signal at –67 dBm, modulated interferer at ±4
MHz, BER = 10–3 36 / 34(2) dB
Selectivity, ±6 MHz(1) Wanted signal at –67 dBm, modulated interferer at ±6
MHz, BER = 10–3 37 / 36(2) dB
Selectivity, image frequency(1) Wanted signal at –67 dBm, modulated interferer at image
frequency, BER = 10–3 4 dB
Selectivity, image frequency
±2 MHz(1)
Note that Image frequency + 2 MHz is the Co-channel.
Wanted signal at –67 dBm, modulated interferer at ±2
MHz from image frequency, BER = 10–3
–7 / 36(2) dB
Out-of-band blocking(3) 30 MHz to 2000 MHz –16 dBm
Out-of-band blocking 2003 MHz to 2399 MHz –21 dBm
Out-of-band blocking 2484 MHz to 2997 MHz –15 dBm
Out-of-band blocking 3000 MHz to 12.75 GHz –12 dBm
Intermodulation
Wanted signal at 2402 MHz, –64 dBm. Two interferers
at 2408 and 2414 MHz respectively, at the given power
level
–38 dBm
(1) Numbers given as I/C dB
(2) X / Y, where X is +N MHz and Y is –N MHz
(3) Excluding one exception at Fwanted / 2, per Bluetooth Specification
(4) Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2
(Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan)
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8.11 Bluetooth Low Energy - Transmit (TX)
Measured on the CC2652xSIP-EM reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled and high power PA connected to VDDS unless otherwise noted.
All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is
measured at a dedicated antenna connection. All measurements are performed conducted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
General Parameters
Max output power,
high power PA, 10
dBm configuration(1) (2)
Differential mode, delivered to a single-ended 50 Ω load through a balun 10.5 dBm
Output power
programmable range
high power PA, 10
dBm configuration
Differential mode, delivered to a single-ended 50 Ω load through a balun 5 dB
Max output power,
regular PA Differential mode, delivered to a single-ended 50 Ω load through a balun 5 dBm
Output power
programmable range,
regular PA
Differential mode, delivered to a single-ended 50 Ω load through a balun 26 dB
Spurious emissions and harmonics
Spurious emissions,
high-power PA, 10
dBm configuration(2)
f < 1 GHz, outside restricted bands
+10 dBm setting
< -36 dBm
f < 1 GHz, restricted bands ETSI < -54 dBm
f < 1 GHz, restricted bands FCC < -55 dBm
f > 1 GHz, including harmonics -41 dBm
Harmonics,
high-power PA, 10
dBm configuration(1)
Second harmonic < -42 dBm
Third harmonic < -42 dBm
Spurious emissions,
regular PA
f < 1 GHz, outside restricted bands
+5 dBm setting
< –36 dBm
f < 1 GHz, restricted bands ETSI < –54 dBm
f < 1 GHz, restricted bands FCC < –55 dBm
f > 1 GHz, including harmonics < –42 dBm
Harmonics,
regular PA
Second harmonic < -42 dBm
Third harmonic < -42 dBm
(1) To meet the FCC 15.247 Part 15 (US) harmonic requirement at full output power, the max allowable antenna gain is 1.9 dBi. Output
power is limited to 9 dBm when using a max antenna gain of 3.3 dBi.
(2) To meet the ETSI EN 300 328 (Europe) 10 dBm/MHz Power Spectral Density (PSD) requirement, output power is limited to 7 dBm and
6dBm when using a max antenna gain of 1.9 dBi and 3.3 dBi, respectively.
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8.12 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - RX
Measured on the CC2652xSIP-EM reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled and high power PA connected to VDDS unless otherwise noted.
All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is
measured at a dedicated antenna connection. All measurements are performed conducted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
General Parameters
Receiver sensitivity PER = 1% –98 dBm
Receiver saturation PER = 1% > 5 dBm
Adjacent channel rejection Wanted signal at –82 dBm, modulated interferer at ±5 MHz,
PER = 1% 36 dB
Alternate channel rejection Wanted signal at –82 dBm, modulated interferer at ±10 MHz,
PER = 1% 57 dB
Channel rejection, ±15 MHz or more
Wanted signal at –82 dBm, undesired signal is IEEE
802.15.4 modulated channel, stepped through all channels
2405 to 2480 MHz, PER = 1%
59 dB
Blocking and desensitization,
5 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the sensitivity level),
CW jammer, PER = 1% 57 dB
Blocking and desensitization,
10 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the sensitivity level),
CW jammer, PER = 1% 62 dB
Blocking and desensitization,
20 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the sensitivity level),
CW jammer, PER = 1% 62 dB
Blocking and desensitization,
50 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the sensitivity level),
CW jammer, PER = 1% 65 dB
Blocking and desensitization,
–5 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the sensitivity level),
CW jammer, PER = 1% 59 dB
Blocking and desensitization,
–10 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the sensitivity level),
CW jammer, PER = 1% 59 dB
Blocking and desensitization,
–20 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the sensitivity level),
CW jammer, PER = 1% 63 dB
Blocking and desensitization,
–50 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the sensitivity level),
CW jammer, PER = 1% 65 dB
Spurious emissions, 30 MHz to 1000
MHz Measurement in a 50-Ω single-ended load –66 dBm
Spurious emissions, 1 GHz to 12.75
GHz Measurement in a 50-Ω single-ended load –53 dBm
Frequency error tolerance Difference between the incoming carrier frequency and the
internally generated carrier frequency > 350 ppm
Symbol rate error tolerance Difference between incoming symbol rate and the internally
generated symbol rate > 1000 ppm
RSSI dynamic range 95 dB
RSSI accuracy ±4 dB
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8.13 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - TX
Measured on the CC2652xSIP-EM reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled and high power PA connected to VDDS unless otherwise noted.
All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is
measured at a dedicated antenna connection. All measurements are performed conducted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
General Parameters
Max output power, high
power PA, 10 dBm
configuration(1) (2)
Differential mode, delivered to a single-ended 50-Ω load through a balun 10.0 dBm
Output power
programmable range,
high power PA, 10 dBm
configuration
Differential mode, delivered to a single-ended 50-Ω load through a balun 5 dB
Max output power,
regular PA (3) Differential mode, delivered to a single-ended 50-Ω load through a balun 5 dBm
Output power
programmable range,
regular PA
Differential mode, delivered to a single-ended 50-Ω load through a balun 26 dB
Spurious emissions and harmonics
Spurious emissions,
high-power PA, 10 dBm
configuration(1)
f < 1 GHz, outside restricted
bands
+10 dBm setting
< -36 dBm
f < 1 GHz, restricted bands ETSI < -47 dBm
f < 1 GHz, restricted bands FCC < -55 dBm
f > 1 GHz, including harmonics -42 dBm
Harmonics,
high-power PA, 10 dBm
configuration
Second harmonic < -42 dBm
Third harmonic < -42 dBm
Spurious emissions,
regular PA (3)
f < 1 GHz, outside restricted
bands
+5 dBm setting
< -36 dBm
f < 1 GHz, restricted bands ETSI < -47 dBm
f < 1 GHz, restricted bands FCC < -55 dBm
f > 1 GHz, including harmonics < –42 dBm
Harmonics,
regular PA (3)
Second harmonic < -42 dBm
Third harmonic < -42 dBm
IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps)
Error vector magnitude,
high power PA, 10 dBm
configuration
+10 dBm setting 2 %
Error vector magnitude,
Regular PA +5 dBm setting 2 %
(1) For FCC 15.247 Part 15 (US) Channel 16 is disabled and not available for use.
(2) To meet the ETSI EN 300 328 (Europe) 10dBm/MHz Power Spectral Density (PSD) requirement, output power is limited to 7 dBm and
6 dBm when using a max antenna gain of 1.9 dBi and 3.3 dBi, respectively.
(3) To meet the FCC 15.247 Part 15 (US) Band Edge requirement, Channel 16 is reduced by 3 dBm.
8.14 Timing and Switching Characteristics
8.14.1 Reset Timing
PARAMETER MIN TYP MAX UNIT
nRESET low duration 1 µs
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8.14.2 Wakeup Timing
Measured over operating free-air temperature with VDDS = 3.0 V (unless otherwise noted). The times listed here do not
include software overhead.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
MCU, Reset to Active(1) 850 - 4000 µs
MCU, Shutdown to Active(1) 850 - 4000 µs
MCU, Standby to Active 165 µs
MCU, Active to Standby 36 µs
MCU, Idle to Active 14 µs
(1) The wakeup time is dependent on remaining charge on VDDR capacitor when starting the device, and thus how long the device has
been in Reset or Shutdown before starting up again.
8.14.3 Clock Specifications
8.14.3.1 48 MHz Crystal Oscillator (XOSC_HF)
Measured on a CC2652xSIP-EM reference design with integrated 48 MHz crystal including parameters based on external
manufacturer's crystal specification at Tc = 25 °C, VDDS = 3.0 V at initial time, unless otherwise noted.
MIN TYP MAX UNIT
Crystal frequency 48 MHz
Start-up time(1) 200 µs
Initial crystal frequency tolerance(2) -16 18 ppm
Crystal aging at 10 years(2) -4 2 ppm/year
(1) Start-up time using the TI-provided power driver. Start-up time may increase if driver is not used.
(2) External manufacturer's crystal specification
8.14.3.2 48 MHz RC Oscillator (RCOSC_HF)
Measured on a CC2652xSIP-EM reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN TYP MAX UNIT
Frequency 48 MHz
Uncalibrated frequency accuracy ±1 %
Calibrated frequency accuracy(1) ±0.25 %
Start-up time 5 µs
(1) Accuracy relative to the calibration source (XOSC_HF)
8.14.3.3 2 MHz RC Oscillator (RCOSC_MF)
Measured on a CC2652xSIP-EM reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN TYP MAX UNIT
Calibrated frequency 2 MHz
Start-up time 5 µs
8.14.3.4 32.768 kHz Crystal Oscillator (XOSC_LF)
Measured on a CC2652xSIP-EM reference design with integrated 32.768 kHz crystal including parameters based on external
manufacturer's crystal specification at Tc = 25 °C, VDDS = 3.0 V at initial time, unless otherwise noted.
MIN TYP MAX UNIT
Crystal frequency 32.768 kHz
Initial crystal frequency tolerance(1) -20 20 ppm
Crystal aging at 1st year(1) -3 3 ppm/year
(1) External manufacturer's crystal specification
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8.14.3.5 32 kHz RC Oscillator (RCOSC_LF)
Measured on a CC2652xSIP-EM reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN TYP MAX UNIT
Calibrated frequency 32.8 (1) kHz
Temperature coefficient. 50 ppm/°C
(1) When using RCOSC_LF as source for the low frequency system clock (SCLK_LF), the accuracy of the SCLK_LF-derived Real Time
Clock (RTC) can be improved by measuring RCOSC_LF relative to XOSC_HF and compensating for the RTC tick speed. This
functionality is available through the TI-provided Power driver.
8.14.4 Synchronous Serial Interface (SSI) Characteristics
8.14.4.1 Synchronous Serial Interface (SSI) Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
NO. PARAMETER MIN TYP MAX UNIT
S1 tclk_per SSIClk cycle time 12 65024 System Clocks (2)
S2(1) tclk_high SSIClk high time 0.5 tclk_per
S3(1) tclk_low SSIClk low time 0.5 tclk_per
(1) Refer to SSI timing diagrams Figure 8-1, Figure 8-2, and Figure 8-3.
(2) When using the TI-provided Power driver, the SSI system clock is always 48 MHz.
SSIClk
SSIFss
SSITx
SSIRx MSB LSB
S2
S3
S1
4 to 16 bits
Figure 8-1. SSI Timing for TI Frame Format (FRF = 01), Single Transfer Timing Measurement
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