Texas Instruments SimpleLink CC3200MOD User manual

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CC3200MOD
SWRS166 –DECEMBER 2014
CC3200MOD SimpleLink™ Wi-Fi
®
and Internet-of-Things Module Solution, a Single-Chip
Wireless MCU
1 Module Overview
1.1 Features
1– TCP/IP Stack
• The CC3200MOD is a Wi-Fi Module that Consists
of the CC3200R1M2RGC Single-Chip Wireless • 8 Simultaneous TCP, UDP, or RAW Sockets
MCU. This Fully Integrated Module Includes all • 2 Simultaneous TLS v1.2 or SSL 3.0
Required Clocks, SPI Flash, and Passives. Sockets
• Modular FCC, IC, and CE Certifications Save – Powerful Crypto Engine for Fast, Secured
Customer Effort, Time, and Money WLAN Connections With 256-Bit Encryption
• Wi-Fi CERTIFIED™ Modules, With Ability to – Station, Access Point, and Wi-Fi Direct™ Modes
Request Certificate Transfer for Wi-Fi Alliance – WPA2 Personal and Enterprise Security
Members – SimpleLink Connection Manager for Managing
• 1.27-mm Pitch LGA Package for Easy Assembly Wi-Fi Security States
and Low-Cost PCB Design – TX Power
• 17 dBm at 1 DSSS
• Applications Microcontroller Subsystem • 17.25 dBm at 11 CCK
– ARM Cortex-M4 Core at 80 MHz • 13.5 dBm at 54 OFDM
– Embedded Memory Options – RX Sensitivity
• Integrated Serial • –94.7 dBm at 1 DSSS
• RAM (up to 256KB) • –87 dBm at 11 CCK
• Peripheral Drivers in ROM • –73 dBm at 54 OFDM
– Hardware Crypto Engine for Advanced – Application Throughput
Hardware Security Including • UDP: 16 Mbps
• AES, DES, and 3DES • TCP: 13 Mbps
• SHA and MD5 • Power-Management Subsystem
• CRC and Checksum – Integrated DC-DC Converter With a Wide-
– 8-Bit, Fast, Parallel Camera Interface Supply Voltage:
– 1 Multichannel Audio Serial Port (McASP) • VBAT: 2.3 to 3.6 V
Interface With Support for I2S Format – Low-Power Consumption at 3.6 V
– 1 SD (MMC) Interface • Hibernate With Real-Time Clock (RTC):
– 32-Channel Micro Direct Memory Access 7μA
(μDMA) • Low-Power Deep Sleep: <275 μA
– 2 Universal Asynchronous • RX Traffic: 59 mA at 54 OFDM
Receivers/Transmitters (UARTs) • TX Traffic: 229 mA at 54 OFDM
– 2 Serial Peripheral Interfaces (SPIs) – Additional Integrated Components
– 1 Inter-integrated Circuit (I2C) • 40.0-MHz Crystal
– 4 General-Purpose Timers (GPTs) • 32.768-kHz Crystal (RTC)
– 16-Bit Pulse-Width Modulation (PWM) Mode • 8-Mbit SPI Serial Flash RF Filter and
– 1 Watchdog Timer Module Passive Components
– 4-Channel 12-Bit Analog-to-Digital Converters – Package and Operating Conditions
(ADCs) • 1.27-mm Pitch, 63-Pin, 20.5-mm ×
– Up to 25 Individually Programmable GPIO Pins 17.5 mm LGA Package for Easy Assembly
• Wi-Fi Network Processor Subsystem and Low-Cost PCB Design
– 802.11b/g/n Radio, Baseband, and Medium • Operating Temperature Range: –20°C to
Access Control 70°C
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

CC3200MOD
SWRS166 –DECEMBER 2014 www.ti.com
1.2 Applications
• Internet of Things (IoT) • Internet Gateway
• Cloud Connectivity • Industrial Control
• Home Automation • Smart Plug and Metering
• Home Appliances • Wireless Audio
• Access Control • IP Network Sensor Nodes
• Security Systems • Wearables
• Smart Energy
1.3 Description
Start your design with the industry’s first programmable FCC, IC, CE, and Wi-Fi Certified Wireless
microcontroller (MCU) module with built-in Wi-Fi connectivity. Created for the Internet of Things (IoT), the
SimpleLink CC3200MOD is a wireless MCU module that integrates an ARM Cortex-M4 MCU, allowing
customers to develop an entire application with a single device. With on-chip Wi-Fi, Internet, and robust
security protocols, no prior Wi-Fi experience is required for faster development. The CC3200MOD
integrates all required system-level hardware components including clocks, SPI flash, RF switch, and
passives into an LGA package for easy assembly and low-cost PCB design. The CC3200MOD is provided
as a complete platform solution including software, sample applications, tools, user and programming
guides, reference designs, and the TI E2E™ support community
The applications MCU subsystem contains an industry-standard ARM Cortex-M4 core running at 80 MHz.
The device includes a wide variety of peripherals, including a fast parallel camera interface, I2S, SD/MMC,
UART, SPI, I2C, and four-channel ADC. The CC3200 family includes flexible embedded RAM for code
and data; ROM with external serial flash bootloader and peripheral drivers; and SPI flash for Wi-Fi network
processor service packs, Wi-Fi certificates, and credentials.
The Wi-Fi network processor subsystem features a Wi-Fi Internet-on-a-chip™ and contains an additional
dedicated ARM MCU that completely off-loads the applications MCU. This subsystem includes an 802.11
b/g/n radio, baseband, and MAC with a powerful crypto engine for fast, secure Internet connections with
256-bit encryption. The CC3200MOD supports station, access point, and Wi-Fi Direct™ modes. The
device also supports WPA2 personal and enterprise security and WPS 2.0. The Wi-Fi Internet-on-a-chip
includes embedded TCP/IP and TLS/SSL stacks, HTTP server, and multiple Internet protocols. The
power-management subsystem includes integrated DC-DC converters supporting a wide range of supply
voltages. This subsystem enables low-power consumption modes, such as the hibernate with RTC mode
requiring less than 7 μA of current.
Table 1-1. Module Information(1)
PART NUMBER PACKAGE BODY SIZE
CC3200MODR1M2AMOB MOB (63) 20.5 mm × 17.5 mm
(1) For more information, see Section 9,Mechanical Packaging and Orderable Information.
2Module Overview Copyright © 2014, Texas Instruments Incorporated
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CC3200MOD
VCC
GPIO &
Peripheral
Interfaces RF Filter
Serial
Flash
8Mbit
Pull-up
resistors
CC3200R1M2RGC
Power
Inductors
Caps
32-KHz
Crystal 40-MHz
Crystal
CC3200MOD
www.ti.com SWRS166 –DECEMBER 2014
1.4 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the CC3200MOD module.
(1) For 3200MOD module pin multiplexing details, refer to CC3200R device datasheet (literature number: SWAS032)
Figure 1-1. CC3200MOD Module Functional Block Diagram
Copyright © 2014, Texas Instruments Incorporated Module Overview 3
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ARM Cortex-M4 80 MHz Processor
ARM Processor (Wi-Fi Network Processor)
Wi-Fi Baseband
Wi-Fi MAC
Wi-Fi Radio
Wi-Fi Driver
Supplicant
TCP/IP
TLS/SSL
Internet Protocols
User Application
Embedded Wi-Fi
Embedded Internet
CC3200MOD
SWRS166 –DECEMBER 2014 www.ti.com
Figure 1-2. CC3200 Hardware Overview
Figure 1-3. CC3200 Software Overview
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Table of Contents
1 Module Overview ........................................ 15.3 ARM Cortex-M4 Processor Core Subsystem....... 42
1.1 Features .............................................. 15.4 CC3200 Device Encryption ......................... 43
1.2 Applications........................................... 25.5 Wi-Fi Network Processor Subsystem............... 44
1.3 Description............................................ 25.6 Power-Management Subsystem .................... 45
1.4 Functional Block Diagram ............................ 35.7 Low-Power Operating Mode ........................ 45
2 Revision History ......................................... 65.8 Memory.............................................. 46
3 Terminal Configuration and Functions.............. 75.9 Boot Modes.......................................... 48
3.1 CC3200MOD Pin Diagram ........................... 76 Applications, Implementation, and Layout ....... 51
3.2 Pin Attributes ......................................... 86.1 Reference Schematics .............................. 51
3.3 Pin Attributes and Pin Multiplexing.................. 10 6.2 Bill of Materials...................................... 52
3.4 Recommended Pin Multiplexing Configurations .... 19 6.3 Layout Recommendations .......................... 52
3.5 Drive Strength and Reset States for Analog-Digital 7 Environmental Requirements and
Multiplexed Pins..................................... 22 Specifications........................................... 56
3.6 Pad State After Application of Power To Chip But 7.1 Temperature......................................... 56
Prior To Reset Release ............................. 22 7.2 Handling Environment .............................. 56
4 Specifications........................................... 23 7.3 Storage Condition ................................... 56
4.1 Absolute Maximum Ratings......................... 23 7.4 Baking Conditions................................... 56
4.2 Handling Ratings.................................... 23 7.5 Soldering and Reflow Condition .................... 56
4.3 Power-On Hours .................................... 23 8 Product and Documentation Support.............. 58
4.4 Recommended Operating Conditions............... 23 8.1 Development Support ............................... 58
4.5 Brown-Out and Black-Out........................... 24 8.2 Device Nomenclature ............................... 58
4.6 Electrical Characteristics (3.3 V, 25°C) ............. 25 8.3 Community Resources.............................. 59
4.7 Thermal Resistance Characteristics for MOB 8.4 Trademarks.......................................... 59
Package ............................................. 26 8.5 Electrostatic Discharge Caution..................... 59
4.8 Reset Requirement ................................. 26 8.6 Export Control Notice ............................... 59
4.9 Current Consumption ............................... 27 8.7 Glossary............................................. 59
4.10 WLAN RF Characteristics........................... 30 9 Mechanical Packaging and Orderable
4.11 Timing Characteristics............................... 31 Information .............................................. 60
5 Detailed Description ................................... 42 9.1 Mechanical Drawing................................. 60
5.1 Overview ............................................ 42 9.2 Package Option ..................................... 61
5.2 Functional Block Diagram........................... 42
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SWRS166 –DECEMBER 2014 www.ti.com
2 Revision History
DATE REVISION NOTES
November 2014 * Initial release.
6Revision History Copyright © 2014, Texas Instruments Incorporated
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44
45
46
47
48
49
50
51
52
53
54
27
26
25
24
23
22
21
20
19
18
17
28 29 30 31 3332 34 35 36 37 38 39 40 41 42 43
16 15 14 13 1112 10 9 8 7 6 5 4 3 2 1
63
59
55
62 61
60
57 56
58
GND
ANTSEL2
ANTSEL1
SOP1
SOP2
JTAG_TMS
JTAG_TCK
NC
GPIO28
JTAG_TDO
NC
GND
NC NC
NC
JTAG_TDI
GPIO22
GPIO13
GPIO12 GPIO17 GPIO16
GPIO15
GPIO14
GPIO11
GPIO10
GND
GND
GPIO0
NC
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GND NC
GND
RF_BG
GND
NC SOP0
nRESET
VBAT_DCDC_ANA
VBAT_DCDC_PA
GND
VDD_ANA2
VBAT_DCDC_DIG_IO
NC
GPIO30
GND
GND
GND
GND
GND
GND
GND
GND
GND
CC3200MOD
CC3200MOD
www.ti.com SWRS166 –DECEMBER 2014
3 Terminal Configuration and Functions
3.1 CC3200MOD Pin Diagram
Figure 3-1 shows the pin diagram for the CC3200MOD.
Figure 3-1. CC3200MOD Pin Diagram (Bottom View)
NOTE
Figure 3-1 shows the approximate location of pins on the module. For the actual mechanical
diagram refer to Section 9.
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SWRS166 –DECEMBER 2014 www.ti.com
3.2 Pin Attributes
Table 3-1 lists the pin descriptions of the CC3200MOD module. "DEVICE PIN NO" refers to the pin
number of the QFN part CC3200. This is stated here because the QFN pin is referred to in the SDK.
Table 3-1. Pin Attributes
MODULE MODULE PIN NAME TYPE DEVICE PIN NO MODULE PIN DESCRIPTION
PIN NO.
1 GND - Ground
2 GND - Ground
3 GPIO10 I/O 1 GPIO(1)
4 GPIO11 I/O 2 GPIO(1)
5 GPIO14 I/O 5 GPIO(1)
6 GPIO15 I/O 6 GPIO(1)
7 GPIO16 I/O 7 GPIO(1)
8 GPIO17 I/O 8 GPIO(1)
9 GPIO12 I/O 3 GPIO(1)
10 GPIO13 I/O 4 GPIO(1)
11 GPIO22 I/O 15 GPIO(1)
12 JTAG_TDI I/O 16 GPIO(1)
13 NC - 13 Reserved for TI
14 NC - 14 Reserved for TI
15 NC - 11 Reserved for TI
16 GND - Ground
17 NC - 12 Reserved for TI
18 JTAG_TDO I/O 17 GPIO(1)
19 GPIO28 I/O 18 GPIO(1)
20 NC - 23 Unused. Do not connect.
21 JTAG_TCK I/O 19 JTAG TCK input. Needs 100-kΩpulldown resistor to ground.(1)
22 JTAG_TMS I/O 20 JTAG TMS input. Leave unconnected if not used on product.(1)
23 SOP2 - 21 Add 2.7-kΩpulldown resistor to ground needed for functional
mode. Add option to pullup required for entering the UART load
mode for flashing.
24 SOP1 - 34 Reserved. Do not connect.
25 ANTSEL1 I/O 29 Antenna selection control(1)
26 ANTSEL2 I/O 30 Antenna selection control(1)
27 GND - Ground
28 GND - Ground
29 NC - 27, 28 Reserved for TI
30 GND - Ground
31 RF_BG I/O 31 2.4-GHz RF input/output
32 GND - Ground
33 NC - 38 Reserved for TI
34 SOP0 - 35 Optional 10-kΩpullup if user chooses to use SWD debug mode
instead of 4-wire JTAG
35 nRESET I 32 Power on reset. Does not require external RC circuit
36 VBAT_DCDC_ANA - 37 Power supply for the device, can be connected to battery (2.3 V
to 3.6 V)
37 VBAT_DCDC_PA - 39 Power supply for the device, can be connected to battery (2.3 V
to 3.6 V)
38 GND - Ground
(1) For pin multiplexing details, refer to CC3200R device data sheet
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Table 3-1. Pin Attributes (continued)
MODULE MODULE PIN NAME TYPE DEVICE PIN NO MODULE PIN DESCRIPTION
PIN NO.
39 NC - 47 Leave unconnected
40 VBAT_DCDC_DIG_IO - 10, 44, 54 Power supply for the device, can be connected to battery (2.3 V
to 3.6 V)
41 NC - 25, 36, 48 Reserved for TI
42 GPIO30 I/O 53 GPIO(1)
43 GND - Ground
44 GPIO0 I/O 50 GPIO(1)
45 NC - 51 Reserved for TI
46 GPIO1 I/O 55 GPIO(1)
47 GPIO2 I/O 57 GPIO(1)
48 GPIO3 I/O 58 GPIO(1)
49 GPIO4 I/O 59 GPIO(1)
50 GPIO5 I/O 60 GPIO(1)
51 GPIO6 I/O 61 GPIO(1)
52 GPIO7 I/O 62 GPIO(1)
53 GPIO8 I/O 63 GPIO(1)
54 GPIO9 I/O 64 GPIO(1)
55 GND - Thermal Ground
56 GND - Thermal Ground
57 GND - Thermal Ground
58 GND - Thermal Ground
59 GND - Thermal Ground
60 GND - Thermal Ground
61 GND - Thermal Ground
62 GND - Thermal Ground
63 GND - Thermal Ground
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3.3 Pin Attributes and Pin Multiplexing
The module makes extensive use of pin multiplexing to accommodate the large number of peripheral
functions in the smallest possible package. To achieve this configuration, pin multiplexing is controlled
using a combination of hardware configuration (at module reset) and register control.
The board and software designers are responsible for the proper pin multiplexing configuration. Hardware
does not ensure that the proper pin multiplexing options are selected for the peripherals or interface mode
used. Table 3-2 describes the general pin attributes and presents an overview of pin multiplexing. All pin
multiplexing options are configurable using the pin mux registers. The following special considerations
apply:
• All I/Os support drive strengths of 2, 4, and 6 mA. Drive strength is configurable individually for each
pin.
• All I/Os support 10-μA pullups and pulldowns.
• These pulls are not active and all of the I/Os remain floating while the device is in Hibernate state.
• The VIO and VBAT supply must be tied together at all times.
• All digital I/Os are nonfail-safe.
NOTE
If an external device drives a positive voltage to the signal pads and the CC3200MOD is not
powered, DC current is drawn from the other device. If the drive strength of the external
device is adequate, an unintentional wakeup and boot of the CC3200MOD can occur. To
prevent current draw, TI recommends any one of the following:
• All devices interfaced to the CC3200MOD must be powered from the same power rail as
the chip.
• Use level-shifters between the module and any external devices fed from other
independent rails.
• The nRESET pin of the CC3200MOD must be held low until the VBAT supply to the
module is driven and stable
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Table 3-2. Pin Multiplexing
General Pin Attributes Function Pad States
Pin Alias Use Select as Config Muxed Dig. Pin Mux Config Dig. Pin Signal Name Signal Signal LPDS(1) Hib(2) nRESET = 0
Wakeup Addl with Reg Mux Description Direction
Source Analog JTAG Config
Mux Mode
Value
General-Purpose
0 GPIO10 I/O Hi-Z
I/O
1 I2C_SCL I2C Clock O Hi-Z
(Open
Drain)
GPIO_PAD_CONFIG_1
GPIO10 I/O No No No 0 Hi-Z Hi-Z
3 GT_PWM06 Pulse-Width O Hi-Z
(0x4402 E0C8) Modulated O/P
7 UART1_TX UART TX Data O 1
6 SDCARD_CLK SD Card Clock O 0
12 GT_CCP01 Timer Capture Port I Hi-Z
General-Purpose
0 GPIO11 I/O Hi-Z
I/O
1 I2C_SDA I2C Data I/O Hi-Z
(Open
Drain)
3 GT_PWM07 Pulse-Width O Hi-Z
Modulated O/P
GPIO_PAD_CONFIG_1 4 pXCLK (XVCLK) Free Clock To O 0
GPIO11 I/O Yes No No 1 Hi-Z Hi-Z
Parallel Camera
(0x4402 E0CC) 6 SDCARD_CMD SD Card I/O Hi-Z
Command Line
7 UART1_RX UART RX Data I Hi-Z
12 GT_CCP02 Timer Capture Port I Hi-Z
13 McAFSX I2S Audio Port O Hi-Z
Frame Sync
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Table 3-2. Pin Multiplexing (continued)
General Pin Attributes Function Pad States
Pin Alias Use Select as Config Muxed Dig. Pin Mux Config Dig. Pin Signal Name Signal Signal LPDS(1) Hib(2) nRESET = 0
Wakeup Addl with Reg Mux Description Direction
Source Analog JTAG Config
Mux Mode
Value
General Purpose
0 GPIO12 I/O Hi-Z
I/O
3 McACLK I2S Audio Port O Hi-Z
Clock O
4 pVS (VSYNC) Parallel Camera I Hi-Z
GPIO_PAD_CONFIG_1 Vertical Sync
GPIO12 I/O No No No 2 Hi-Z Hi-Z
(0x4402 E0D0) 5 I2C_SCL I2C Clock I/O Hi-Z
(Open
Drain)
7 UART0_TX UART0 TX Data O 1
12 GT_CCP03 Timer Capture Port I Hi-Z
General-Purpose
0 GPIO13 I/O
I/O
5 I2C_SDA I2C Data I/O
(Open
GPIO_PAD_CONFIG_1 Drain)
GPIO13 I/O Yes No No 3 Hi-Z Hi-Z Hi-Z
(0x4402 E0D4) 4 pHS (HSYNC) Parallel Camera I
Horizontal Sync
7 UART0_RX UART0 RX Data I
12 GT_CCP04 Timer Capture Port I
General-Purpose
0 GPIO14 I/O
I/O
5 I2C_SCL I2C Clock I/O
(Open
GPIO_PAD_CONFIG_1 Drain)
GPIO14 I/O No No 4 Hi-Z Hi-Z Hi-Z
(0x4402 E0D8) 7 GSPI_CLK General SPI Clock I/O
4 pDATA8 Parallel Camera I
(CAM_D4) Data Bit 4
12 GT_CCP05 Timer Capture Port I
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Table 3-2. Pin Multiplexing (continued)
General Pin Attributes Function Pad States
Pin Alias Use Select as Config Muxed Dig. Pin Mux Config Dig. Pin Signal Name Signal Signal LPDS(1) Hib(2) nRESET = 0
Wakeup Addl with Reg Mux Description Direction
Source Analog JTAG Config
Mux Mode
Value
General-Purpose
0 GPIO15 I/O
I/O
5 I2C_SDA I2C Data I/O
(Open
Drain) Hi-Z Hi-Z
GPIO_PAD_CONFIG_1 7 GSPI_MISO General SPI MISO I/O
GPIO15 I/O No No 5 Hi-Z
(0x4402 E0DC) 4 pDATA9 Parallel Camera I
(CAM_D5) Data Bit 5
13 GT_CCP06 Timer Capture Port I
8 SDCARD_ SD Card Data I/O
DATA0 Hi-Z
General-Purpose
0 GPIO16 I/O Hi-Z
I/O Hi-Z
7 GSPI_MOSI General SPI MOSI I/O Hi-Z
GPIO_PAD_CONFIG_1 Hi-Z Hi-Z
GPIO16 I/O No No 6 4 pDATA10 Parallel Camera I Hi-Z
(0x4402 E0E0) (CAM_D6) Data Bit 6
5 UART1_TX UART1 TX Data O 1
13 GT_CCP07 Timer Capture Port I Hi-Z
8 SDCARD_CLK SD Card Clock O O
General-Purpose
0 GPIO17 I/O
I/O
5 UART1_RX UART1 RX Data I Hi-Z Hi-Z
GPIO_PAD_CONFIG_1 7 GSPI_CS General SPI Chip I/O
Wake-Up
GPIO17 I/O No No 7 Select Hi-Z
Source (0x4402 E0E4) 4 pDATA11 Parallel Camera I
(CAM_D7) Data Bit 7
8 SDCARD_ SD Card I/O
CMD Command Line
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Table 3-2. Pin Multiplexing (continued)
General Pin Attributes Function Pad States
Pin Alias Use Select as Config Muxed Dig. Pin Mux Config Dig. Pin Signal Name Signal Signal LPDS(1) Hib(2) nRESET = 0
Wakeup Addl with Reg Mux Description Direction
Source Analog JTAG Config
Mux Mode
Value
General-Purpose
0 GPIO22 I/O Hi-Z
I/O
GPIO_PAD_CONFIG_2
GPIO22 I/O No No No 2 7 McAFSX I2S Audio Port O Hi-Z Hi-Z Hi-Z
(0x4402 E0F8) Frame Sync
5 GT_CCP04 Timer Capture Port I
JTAG TDI. Reset
1 TDI I
Default Pinout. Hi-Z
General-Purpose
MUXed 0 GPIO23 I/O
GPIO_PAD_CONFIG_2 I/O
with
TDI I/O No No 3 Hi-Z Hi-Z
JTAG 2 UART1_TX UART1 TX Data O 1
(0x4402 E0FC)
TDI 9 I2C_SCL I2C Clock I/O Hi-Z
(Open
Drain)
JTAG TDO. Reset
1 TDO O
Default Pinout.
0 GPIO24 General-Purpose I/O
I/O
5 PWM0 Pulse Width O
MUXed Modulated O/P
GPIO_PAD_CONFIG_
Wake-Up with
TDO I/O No 24 2 UART1_RX UART1 RX Data I Hi-Z Hi-Z Hi-Z
Source JTAG (0x4402 E100) 9 I2C_SDA I2C Data I/O
TDO (Open
Drain)
4 GT_CCP06 Timer Capture Port I
6 McAFSX I2S Audio Port O
Frame Sync
GPIO_PAD_CONFIG_ General-Purpose
GPIO28 I/O No 28 0 GPIO28 I/O Hi-Z Hi-Z Hi-Z
I/O
(0x4402 E110) JTAG/SWD TCK
MUXed 1 TCK Reset Default I
with Pinout
TCK I/O No No JTAG/ Hi-Z Hi-Z Hi-Z
SWD- 8 GT_PWM03 Pulse Width O
TCK Modulated O/P
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Table 3-2. Pin Multiplexing (continued)
General Pin Attributes Function Pad States
Pin Alias Use Select as Config Muxed Dig. Pin Mux Config Dig. Pin Signal Name Signal Signal LPDS(1) Hib(2) nRESET = 0
Wakeup Addl with Reg Mux Description Direction
Source Analog JTAG Config
Mux Mode
Value
JATG/SWD TMS
MUXed 1 TMS Reset Default
with GPIO_PAD_CONFIG_ Pinout
TMS I/O No No JTAG/ 29 I/O Hi-Z Hi-Z Hi-Z
SWD- (0x4402 E114) 0 GPIO29 General-Purpose
TMSC I/O
General-Purpose
0 GPIO25 O Hi-Z
I/O
9 GT_PWM02 Pulse Width O Hi-Z
Modulated O/P
GPIO_PAD_CONFIG_ 2 McAFSX I2S Audio Port O Hi-Z Driven
SOP2 O Only No No No 25 Hi-Z
Frame Sync Low
(0x4402 E104) See (5) TCXO_EN Enable to Optional O O
External 40-MHz
TCXO
See (6) SOP2 Sense-On-Power 2 I
User config GPIO_PAD_CONFIG_2
not Antenna Selection
ANTSEL1 O Only No No 6 0 ANTSEL1(3) O Hi-Z Hi-Z Hi-Z
required Control
(0x4402 E108)
(8)
User config GPIO_PAD_CONFIG_2
not Antenna Selection
ANTSEL2 O Only No No 7 0 ANTSEL2(3) O Hi-Z Hi-Z Hi-Z
required Control
(0x4402 E10C)
(8)
Config
SOP1 N/A N/A N/A N/A SOP1 Sense On Power 1
Sense
Config
SOP0 N/A N/A N/A N/A SOP0 Sense On Power 0
Sense
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Table 3-2. Pin Multiplexing (continued)
General Pin Attributes Function Pad States
Pin Alias Use Select as Config Muxed Dig. Pin Mux Config Dig. Pin Signal Name Signal Signal LPDS(1) Hib(2) nRESET = 0
Wakeup Addl with Reg Mux Description Direction
Source Analog JTAG Config
Mux Mode
Value
General-Purpose
0 GPIO0 I/O Hi-Z Hi-Z Hi-Z
I/O
12 UART0_CTS UART0 Clear To I Hi-Z Hi-Z Hi-Z
Send Input (Active
Low)
6 McAXR1 I2S Audio Port I/O Hi-Z
Data 1 (RX/TX)
7 GT_CCP00 Timer Capture Port I Hi-Z
User config
not GPIO_PAD_CONFIG_0 9 GSPI_CS General SPI Chip I/O Hi-Z
GPIO0 I/O No No
required (0x4402 E0A0) Select
(8) 10 UART1_RTS UART1 Request O 1
To Send O (Active
Low)
3 UART0_RTS UART0 Request O 1
To Send O (Active
Low)
4 McAXR0 I2S Audio Port I/O Hi-Z
Data 0 (RX/TX)
General-Purpose
0 GPIO30 I/O Hi-Z Hi-Z Hi-Z
I/O
9 UART0_TX UART0 TX Data O 1
User config 2 McACLK I2S Audio Port O Hi-Z
GPIO_PAD_CONFIG_3
not Clock O
GPIO30 I/O No No 0
required (0x4402 E118) 3 McAFSX I2S Audio Port O Hi-Z
(8) Frame Sync
4 GT_CCP05 Timer Capture Port I Hi-Z
7 GSPI_MISO General SPI MISO I/O Hi-Z
General-Purpose
0 GPIO1 I/O Hi-Z Hi-Z Hi-Z
I/O
3 UART0_TX UART0 TX Data O 1
GPIO_PAD_CONFIG_1 4 pCLK (PIXCLK) Pixel Clock From I Hi-Z
GPIO1 I/O No No No (0x4402 E0A4) Parallel Camera
Sensor
6 UART1_TX UART1 TX Data O 1
7 GT_CCP01 Timer Capture Port I Hi-Z
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Table 3-2. Pin Multiplexing (continued)
General Pin Attributes Function Pad States
Pin Alias Use Select as Config Muxed Dig. Pin Mux Config Dig. Pin Signal Name Signal Signal LPDS(1) Hib(2) nRESET = 0
Wakeup Addl with Reg Mux Description Direction
Source Analog JTAG Config
Mux Mode
Value
ADC Channel 0
See (5) ADC_CH0 I
Input (1.5V max)
Analog
Input 0 GPIO2 General-Purpose I/O Hi-Z
(up to Wake-Up GPIO_PAD_CONFIG_2 I/O
GPIO2 See (10) No Hi-Z Hi-Z
1.8 V)/ Source (0x4402 E0A8) 3 UART0_RX UART0 RX Data I Hi-Z
Digital 6 UART1_RX UART1 RXt Data I Hi-Z
I/O 7 GT_CCP02 Timer Capture Port I Hi-Z
ADC Channel 1
See (5) ADC_CH1 I
Input (1.5V max)
Analog
Input 0 GPIO3 General-Purpose I/O Hi-Z
(up to GPIO_PAD_CONFIG_3 I/O
GPIO3 No See (10) No Hi-Z Hi-Z
1.8 V)/ (0x4402 E0AC) 6 UART1_TX UART1 TX Data O 1
Digital
I/O 4 pDATA7 Parallel Camera I Hi-Z
(CAM_D3) Data Bit 3
ADC Channel 2
See (5) ADC_CH2 I
Input (1.5V max)
Analog
Input 0 GPIO4 General-Purpose I/O Hi-Z
(up to Wake-up GPIO_PAD_CONFIG_4 I/O
GPIO4 See (10) No Hi-Z Hi-Z
1.8 V)/ Source (0x4402 E0B0) 6 UART1_RX UART1 RX Data I Hi-Z
Digital
I/O 4 pDATA6 Parallel Camera I Hi-Z
(CAM_D2) Data Bit 2
ADC Channel 3
See (5) ADC_CH3 I
Input (1.5V max)
Analog 0 GPIO5 General-Purpose I/O Hi-Z
Input I/O
(up to GPIO_PAD_CONFIG_5
GPIO5 No See (10) No 4 pDATA5 Parallel Camera I Hi-Z Hi-Z Hi-Z
1.8 V)/ (0x4402 E0B4) (CAM_D1) Data Bit 1
Digital 6 McAXR1 I2S Audio Port I/O Hi-Z
I/O Data 1 (RX/TX)
7 GT_CCP05 Timer Capture Port I Hi-Z
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Table 3-2. Pin Multiplexing (continued)
General Pin Attributes Function Pad States
Pin Alias Use Select as Config Muxed Dig. Pin Mux Config Dig. Pin Signal Name Signal Signal LPDS(1) Hib(2) nRESET = 0
Wakeup Addl with Reg Mux Description Direction
Source Analog JTAG Config
Mux Mode
Value
General-Purpose
0 GPIO6 I/O Hi-Z
I/O
5 UART0_RTS UART0 Request O 1
To Send O (Active
Low)
4 pDATA4 Parallel Camera I Hi-Z
(CAM_D0) Data Bit 0
GPIO_PAD_CONFIG_6
GPIO6 No No No No Hi-Z Hi-Z
(0x4402 E0B8) 3 UART1_CTS UART1 Clear To I Hi-Z
Send Input (Active
Low)
6 UART0_CTS UART0 Clear To I Hi-Z
Send Input (Active
Low)
7 GT_CCP06 Timer Capture Port I Hi-Z
General-Purpose
0 GPIO7 I/O Hi-Z
I/O
13 McACLKX I2S Audio Port O Hi-Z
Clock O
3 UART1_RTS UART1 Request O 1
GPIO_PAD_CONFIG_7
GPIO7 I/O No No No To Send O (Active Hi-Z Hi-Z
(0x4402 E0BC) Low)
10 UART0_RTS UART0 Request O 1
To Send O (Active
Low)
11 UART0_TX UART0 TX Data O 1
General-Purpose
0 GPIO8 I/O
I/O
6 SDCARD_IRQ Interrupt from SD I
Card (Future
GPIO_PAD_CONFIG_8
GPIO8 I/O No No No Hi-Z Hi-Z Hi-Z
support)
(0x4402 E0C0) 7 McAFSX I2S Audio Port O
Frame Sync
12 GT_CCP06 Timer Capture Port I
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Table 3-2. Pin Multiplexing (continued)
General Pin Attributes Function Pad States
Pin Alias Use Select as Config Muxed Dig. Pin Mux Config Dig. Pin Signal Name Signal Signal LPDS(1) Hib(2) nRESET = 0
Wakeup Addl with Reg Mux Description Direction
Source Analog JTAG Config
Mux Mode
Value
General-Purpose
0 GPIO9 I/O
I/O
3 GT_PWM05 Pulse Width O
Modulated O/P
GPIO_PAD_CONFIG_9
GPIO9 I/O No No No 6 SDCARD_ SD Cad Data I/O Hi-Z Hi-Z Hi-Z
(0x4402 E0C4) DATA0
7 McAXR0 I2S Audio Port I/O
Data (Rx/Tx)
12 GT_CCP00 Timer Capture Port I
(1) LPDS mode: The state of unused GPIOs in LPDS is input with 500-kΩpulldown. For all used GPIOs , the user can enable internal pulls, which would hold them in a valid state.
(2) Hibernate mode: The CC3200 device leaves the digital pins in a Hi-Z state without any internal pulls when the device enters hibernate state. This can cause glitches on output lines unless
held at valid levels by external resistors.
(3) To minimize leakage in some serial flash vendors during LPDS, TI recommends the user application always enable internal weak pulldowns on FLASH_SPI_DATA and FLASH_SPI_CLK
pins.
(4) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During
hibernate low-power mode, the pin is in a high impedance state but pulled down for SOP mode to disable TCXO. Because of SOP functionality, the pin must be used as output only.
(5) For details on proper use, see Drive Strength and Reset States for Analog-Digital Multiplexed Pins.
(6) This pin is one of three that must have a passive pullup or pulldown resistor on board to configure the chip hardware power-up mode. For this reason, the pin must be output only when
used for digital functions.
(7) This pin is reserved for WLAN antenna selection, controlling an external RF switch that multiplexes the RF pin of the CC3200 module between two antennas. These pins should not be
used for other functionalities in general.
(8) Device firmware automatically enables the digital path during ROM boot.
(9) This pin is shared by the ADC inputs and digital I/O pad cells. Important: The ADC inputs are tolerant up to 1.8 V. On the other hand, the digital pads can tolerate up to 3.6 V. Hence, care
must be taken to prevent accidental damage to the ADC inputs. TI recommends that the output buffer(s) of the digital I/Os corresponding to the desired ADC channel be disabled first (that
is, converted to high-impedance state), and thereafter the respective pass switches (S7, S8, S9, S10) should be enabled (see Drive Strength and Reset States for Analog-Digital
Multiplexed Pins).
(10) Requires user configuration to enable the ADC channel analog switch. (The switch is off by default.) The digital I/O is always connected and must be made Hi-Z before enabling the ADC
switch.
3.4 Recommended Pin Multiplexing Configurations
Table 3-3 lists the recommended pin multiplexing configurations.
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Table 3-3. Recommended Pin Multiplexing Configurations
CC3200 Recommended Pinout Grouping Use – Examples(1)
Home Wifi Audio ++ Sensor-Tag Home Wifi Audio ++ WiFi Remote Sensor Door- Industrial Industrial Industrial GPIOs
Security High- Industrial Security Toys Industrial w/ 7x7 Lock Fire- Home Home Home
end Toys keypad and Alarm Toys Appliances Appliances Appliances"
audio w/o Cam Smart-Plug
External 32 External 32 External
kHz(2) kHz (2) TCXO 40
MHZ (-40 to
+85°C)
Cam + I2S I2S (Tx & Rx) I2S (Tx & Rx) Cam + I2S I2S (Tx & Rx) I2S (Tx & Rx) I2S (Tx or Rx) 4 Ch ADC + 3 Ch ADC + 2 Ch ADC +
(Tx or Rx) + + 1 Ch ADC + + 2 Ch ADC + (Tx or Rx) + + 1 Ch ADC + + 1 Ch ADC + + 2 Ch ADC + 1x 4wire 2wire UART + 2wire UART +
I2C + SPI + 1x 4wire 2wire UART + I2C + SWD + 2x 2wire UART (Tx 2 wire UART UART + 1x SPI + I2C + I2C + SWD +
SWD + UART + 1x SPI + I2C + UART-Tx + UART + 1bit Only) I2C + + SPI + I2C + 2wire UART + SWD + 3 3 PWM + 11
UART-Tx + 2wire UART + SWD + 2 (App Logger) SD Card + SWD + 15 3 PMW + 3 SPI + I2C + PWM + 9 GPIO + 5
(App Logger) 1bit SD Card PMW + 6 4 GPIO + SPI + I2C + GPIO + 1 GPIO with SWD + 1 GPIO + 2 GPIO with
2 GPIO + + SPI + I2C + GPIO + 3 1PWM + *4 SWD + 4 PWM + 1 Wake-From- PWM + 6 GPIO with Wake-From-
1PWM + *4 SWD + 3 GPIO with overlaid GPIO + 1 GPIO with Hib + 5 GPIO GPIO + 1 Wake-From- Hib
overlaid GPIO + 1 Wake-From- wakeup from PWM + 1 Wake-From- SWD + GPIO with Hib
wakeup from PWM + 1 Hib HIB GPIO with Hib Wake-From-
Hib GPIO with Wake-From- Hib Enable
Wake-From- Hib for Ext 40
Hib MHz TCXO
Pin Pinout #11 Pinout #10 Pinout #9 Pinout #8 Pinout #7 Pinout #6 Pinout #5 Pinout #4 Pinout #3 Pinout #2 Pinout #1
GPIO_30 GSPI-MISO MCASP- MCASP- GPIO_30 GPIO_30 GPIO_30 GPIO_30 UART0-TX GPIO_30 UART0-TX GPIO_30
ACLKX ACLKX
GPIO_31 GSPI-CLK McASP-AFSX McASP-D0 GPIO_31 McASP-AFSX McASP-AFSX McASP-AFSX UART0-RX GPIO_31 UART0-RX GPIO_31
GPIO_0 GSPI-CS McASP-D1 McASP-D1 McASP-D1 McASP-D1 McASP-D1 McASP-D1 UART0-CTS GPIO_0 GPIO_0 GPIO_0
(Rx)
GPIO_1 pCLK UART0-TX UART0-TX PIXCLK UART0-TX UART0-TX UART0-TX GPIO-1 UART0-TX GPIO_1 GPIO_1
(PIXCLK)
GPIO_2 (wake) GPIO2 UART0-RX UART0-RX (wake) GPIO2 UART0-RX GPIO_2 UART0-RX ADC-0 UART0-RX (wake) (wake)
GPIO_2 GPIO_2
GPIO_3 pDATA7 (D3) UART1-TX ADC-CH1 pDATA7 (D3) UART1-TX GPIO_3 ADC-1 ADC-1 ADC-1 ADC-1 GPIO_3
GPIO_4 pDATA6 (D2) UART1-RX (wake) pDATA6 (D2) UART1-RX GPIO_4 (wake) ADC-2 ADC-2 (wake) (wake)
GPIO_4 GPIO_4 GPIO_4 GPIO_4
GPIO_5 pDATA5 (D1) ADC-3 ADC-3 pDATA5 (D1) ADC-3 ADC-3 ADC-3 ADC-3 ADC-3 ADC-3 GPIO_5
GPIO_6 pDATA4 (D0) UART1-CTS GPIO_6 pDATA4 (D0) GPIO_6 GPIO_6 GPIO_6 UART0-RTS GPIO_6 GPIO_6 GPIO_6
GPIO_7 McASP- UART1-RTS GPIO_7 McASP- McASP- McASP- McASP- GPIO_7 GPIO_7 GPIO_7 GPIO_7
ACLKX ACLKX ACLKX ACLKX ACLKX
(1) Pins marked "wake" can be configured to wake up the chip from HIBERNATE or LPDS state. In the current silicon revision, any wake pin can trigger wake up from HIBERNATE. The
wakeup monitor in the hibernate control module logically ORs these pins applying a selection mask. However, wakeup from LPDS state can be triggered only by one of the wakeup pins
that can be configured before entering LPDS. The core digital wakeup monitor use a mux to select one of these pins to monitor.
(2) The device supports the feeding of an external 32.768-kHz clock. This configuration frees one pin (32K_XTAL_N) to use in output-only mode with a 100K pullup.
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