Texas Instruments ESD224 User manual

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ESD224 Evaluation Module User's Guide
User's Guide
SLVUBE1A–February 2018–Revised April 2018
ESD224 Evaluation Module User's Guide
This user's guide describes the characteristics, operation, and use of the ESD224EVM evaluation module
(EVM). This EVM includes four ESD224’s, two to test the characteristics of the ESD224 and two in HDMI
pass-through mode. One ESD224 is used to measure bandwidth, one ESD224 is used to measure the
clamping voltage during an IEC61000-4-2 ESD strike and two ESD224's are configured to pass-through
HDMI 2.0 signals using an HDMI Type A female and male header. This user's guide includes setup
instructions, schematic diagrams, a bill of materials, and a printed-circuit board layout drawing of the EVM.
Trademarks
1 Introduction
Texas Instrument’s ESD224 evaluation module helps designers evaluate the operation and performance
of the ESD224 device. The ESD224 is a quad-channel ESD protection device in a small DQA package
which offers IEC61000-4-2 Level 4 compliant ESD protection. The 0.5-pF line capacitance is suitable for
high speed applications. The ESD224 is characterized for operation over an ambient air temperature
range of –40°C to 125°C.
The EVM contains four ESD224’s, two for electrical characterization of the device and two sitting on the
TMDS Data and Clock Lines with an HDMI female header on one side and a HDMI male header on the
other. The HDMI 2.0 pass-through portion of the board can be snapped off to be used by itself. This
allows the EVM to be connected to an HDMI port via a HDMI cable and pass HDMI 2.0 signals through.
The other portion of the board allows the device to be characterized.
Table 1. EVM Configuration
Reference Designator TI Part Number Configuration
U1 ESD224 S-Parameters
U2 ESD224 ESD Clamping waveforms
U3 – U4 ESD224 HDMI 2.0 Pass-Through
2 Definitions
Contact Discharge — a method of testing in which the electrode of the ESD simulator is held in contact
with the device-under-test (DUT).
Air Discharge — a method of testing in which the charged electrode of the ESD simulator approaches
the DUT, and a spark to the DUT actuates the discharge.
ESD simulator — a device that generates IEC61000-4-2 compliance ESD waveforms shown in Figure 1
with adjustable ranges shown in Table 2 and Table 3.
IEC61000-4-2 has 4 classes of protection levels. Classes 1 – 4 are shown in Table 2. Stress tests
should be incrementally tested to level 4 as shown in Table 3 until the point of failure. If the DUT
does not fail at 8 kV, testing can continue in 2 kV increments until failure.
Table 2. IEC61000-4-2 Test Levels
Contact Discharge Air Discharge
Class Test Voltage [± kV] Class Test Voltage [± kV]
1212
2424

Current (A)
Time (ns)
15
10
5
10 %
90 %
I
p
I
p
I
30
I
60
I
p
10 20 30 40 50 60 70 80 90 100
10 %
I
p
t
r
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Table 2. IEC61000-4-2 Test Levels (continued)
Contact Discharge Air Discharge
Class Test Voltage [± kV] Class Test Voltage [± kV]
3638
4 8 4 15
Table 3. Waveform Parameters in Contact Discharge Mode
Stress Level Step Simulator Voltage
[kV] Ipeak ±15% [A] Rise Time ±25% [nS] Current at 30ns ±30% [A] Current at 60ns ±30% [A]
1 2 7.5 0.8 4 2
2 4 15 0.8 8 4
3 6 22.5 0.8 12 6
4 8 30 0.8 16 8
Figure 1. Ideal Contact Discharge Waveform of the Output Current of the ESD Simulator at 4 kV
3 Setup
This section describes the intended use of the EVM. A generalized outline of the procedure given in IEC-
61000-4-2 is described here. IEC-61000-4-2 should be referred to for a more specific testing outline. Basic
configurations for collecting S-parameters, Eye Diagrams, and ESD clamping waveforms are outlined as
well.
3.1 U1 - S-Parameters 4-Port Measurement
ESD224 (U1) is configured with 4 SMA (J1 – J4) connectors to allow 4-port analysis with a vector network
analyzer. Connect Port 1 to J1, Port 2 to J2, Port 3 to J3, and Port 4 to J4. This configuration allows for
the following terminology in 4 port analysis:
• S11: Return loss
• S21: Insertion loss
• S31: Near end cross talk

ESD Simulator
DUT or System
Power and Ground Connection
Horizontal Coupling
Plane (HCP)
To the Wall
Ground
Non-conducting Table
Insulation 470 K
470 K
Ground Reference Plane
Typical Position for
Direct Discharge
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• S41: Far end cross talk
3.2 U2 - ESD Clamping waveforms
One ESD224 (U2) also has two SMB (J5, J6) connectors for capturing clamping waveforms with an
oscilloscope during an ESD strike. Caution must be taken when capturing clamping waveforms during an
ESD event so as not to damage the oscilloscope
3.2.1 ESD Tests
The ESD224 device provides an ultra-low clamping voltage during an ESD event. The pass-through
capabilities of this board allow it to be connected to a system and then do the system level ESD testing.
3.2.1.1 Test Method and Set-Up
An example test setup is shown in Figure 2. Details of the testing table and ground planes can be found in
the IEC 61000-4-2 test procedure. Contact and air-gap discharge are tested using the same simulator with
the same discharge waveform. While the simulator is in direct contact with the test point during contact, it
is not during air-gap.
Figure 2. System Level ESD Test Setup
3.2.1.2 Oscilloscope setup
Without a proper procedure, capturing ESD clamping waveforms exposes the oscilloscope to potential
voltages higher than the rating of the equipment. Proper methodology can mitigate any risk in this
operation.
Recommended equipment:
• Minimum of 1GHz bandwidth oscilloscope.
• 1 10X 50Ωattenuator and one 150 Ωresistor (the resistor is already factory installed at R1 and R2).
• 50 Ωshielded SMB cables.
Procedure
In order to protect the oscilloscope, attenuation of the measured signal is required. Here is the procedure
for testing channel 1 of U2:
1. Using one 10X attenuator:
• Attach two 10X attenuator to the oscilloscope.
• Attach the 50 Ωshielded SMB cable between J5 and the attenuator.

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• Set the scope attenuation factor to 40X.
• Set the oscilloscope to trigger on a positive edge for (+) ESD and a negative edge for (–) ESD
strikes. The magnitude should be set to 20 V.
• Following IEC 61000-4-2, strike contact ESD to TP1.
Recommended settings for the time axis is 20 ns/div and for the voltage axis is 10 V division.
The voltage levels of the ESD applied to TP1 should not exceed +/– 8 kV when capturing clamping
waveforms.
If the clamping waveform for channel two is desired, follow the same procedure except connecting the
oscilloscope to J6 and striking TP3.
For best performance of this test, connect the IC, that the ESD224 is suppose to be protecting, to TP2 or
TP4 and then strike and see the waveform. This will show the clamping waveform when another device is
connected because the ESD224 limits the current seen by this IC during an ESD event.
3.2.1.3 Evaluation of Test Results
After ESD testing, perform normal operation testing to see if device has broken or not.
3.3 U3 and U4 - HDMI
At the top of the EVM there are two HDMI connectors, a male and a female. Two ESD224's (U3 and U4)
are placed between those connectors, on the TMDS data and TMDS clock lines, to provide ESD
protection for any devices connected downstream of the board. This board can be connected into a
system to pass HDMI 2.0 content, from an HDMI source to a display for example, in order to verify HDMI
2.0 compliance. However, due to the losses from the male and the female HDMI connectors, it is not
recommended to use this EVM board to run the standard HDMI 2.0 compliance tests. This EVM board is
intended for functional and ESD testing only. For running HDMI 2.0 compliance tests, it is recommended
to place ESD224s directly on the system board built specifically for such a purpose. Please note that this
EVM board was attached to the TPD158RGZEVM to run HDMI 2.0 compliance tests and the results
confirmed the HDMI 2.0 compliance with margin.
4 Board Layout
This section provides the ESD224EVM board layout. ESD224EVM is a 2-layer board of FR-408HR at
0.062” thickness. Layers 2, 3, and 4 are simple ground planes and not shown here.

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Figure 3. 3D Board Image

Board Layout www.ti.com
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Figure 4. ESD224EVM Top Layer

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Figure 5. ESD224EVM Bottom Layer

GND
GND
GND GND
GND
GND
GND
GND
GND
GND1
GND1
GND1
GND1
GND1
GND1
GND1
C_D2_P
C_D2_N
C_D1_P
C_D1_N
C_D0_P
C_D0_N
C_CLK_P
C_CLK_N
S_D2_P
S_D2_N
S_D1_P
S_D1_N
S_D0_P
S_D0_N
S_CLK_P
S_CLK_N
S1 S2
S3 S4
IO1_C
1
IO2_C
2
GND 3
IO3_C
4
IO4_C
5IO4_S 6
IO3_S 7
GND 8
IO2_S 9
IO1_S 10
ESD224DQAR
U1
IO1_C
1
IO2_C
2
GND 3
IO3_C
4
IO4_C
5IO4_S 6
IO3_S 7
GND 8
IO2_S 9
IO1_S 10
ESD224DQAR
U2
IO1_C
1
IO2_C
2
GND 3
IO3_C
4
IO4_C
5IO4_S 6
IO3_S 7
GND 8
IO2_S 9
IO1_S 10
ESD224DQAR
U3
IO1_C
1
IO2_C
2
GND 3
IO3_C
4
IO4_C
5IO4_S 6
IO3_S 7
GND 8
IO2_S 9
IO1_S 10
ESD224DQAR
U4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 21
J9
S 1 S 3 S 4
S 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
J8
1
2 3 4 5
J5
1
2 3 4 5
J1
1
2 3 4 5
J2
1
2 3 4 5
J3
1
2 3 4 5
J4
1
2 3 4 5
J6
TP1
TP2
TP3
TP4 150
R1
150
R2
J7
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5 Schematics and Bill of Materials
5.1 Schematics
Figure 6. ESD224EVM Schematic
Table 4. Bill of Materials
Count RefDes Description Part Number MFR
4 U1,U2,U3,U4 IC, 4-channel ESD
solution ESD224 TI
4 J1, J2, J3, J4 Connector, End Launch
SMA 50 Ohm, TH 142-0761-881 Cinch Connectivity
2 J5, J6 Connector, SMB, Vertical
RCP 0-4GHz, 50Ohm, TH 47151-0001 Cinch Connectivity
1 J7 Standard Banana Jack,
Insulated, Black 6092 Keystone
1 J8 Receptacle, HDMI,
0.5mm, 19 Pos, R/A,
Gold, SMT
47151-0001 Molex
1 J9 HDMI Type A Plug, 1 mm,
Black, TH HDA-M-CN01 Bosscon
2 R1, R2 Resistor, 150, 1%, 0.1 W,
AEC-Q200 Grade 0, 0603 CRCW0603150RFKEA Vishay-Dale

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6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BE
CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL OR
INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THE
EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY OR
IMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED.
7. USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLY
WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGAL
THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
8. Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR
REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING,
OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF
USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TI
MORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS
OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDED
HEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR IN
CONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAR
EVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE
CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9. Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated