Texas Instruments LMK05318EVM User manual

LMK05318EVM
User's Guide
Literature Number: SNAU236A
June 2018–Revised December 2018

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Table of Contents
Contents
Preface ........................................................................................................................................ 5
1 EVM Quick Start................................................................................................................... 7
1.1 Device Revision Identification .......................................................................................... 8
1.2 Default EVM Configuration.............................................................................................. 8
2 Device Under Test .............................................................................................................. 10
2.1 Device Start-Up Modes ................................................................................................ 10
3 EVM Configuration ............................................................................................................. 11
3.1 Power Supply ........................................................................................................... 13
3.2 Logic Inputs and Outputs.............................................................................................. 15
3.3 XO Input ................................................................................................................. 18
3.4 Reference Clock Inputs ............................................................................................... 20
3.5 Clock Outputs ........................................................................................................... 20
3.6 Status Outputs and LEDs.............................................................................................. 21
4 EVM Schematics ................................................................................................................ 22
5 EVM Layouts...................................................................................................................... 33
6 EVM Bill of Materials........................................................................................................... 45
Appendix A Software .................................................................................................................. 51
A.1 Software Installation (One-Time).................................................................................... 51
A.2 TICS Pro Usage for LMK05318 ..................................................................................... 51
Revision History.......................................................................................................................... 52

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List of Figures
List of Figures
1 LMK05318EVM With Default Jumper and DIP Switch Settings ....................................................... 6
2 Key Components - EVM Top Side ...................................................................................... 12
3 Key Components - EVM Bottom Side ................................................................................... 13
4 Default Power Jumper Configuration .................................................................................... 14
5 XO Input Interface (1 of 2) - 48.0048-MHz Oscillator and SMA Ports .............................................. 19
6 XO Input Interface (2 of 2) - LMK61E2 Oscillator ..................................................................... 20
7 Clock Input Interface - PRIREF (Similar for SECREF)................................................................ 20
8 Clock Output Interface - OUT0 (Similar for OUT1-OUT7) ............................................................ 21
9 Schematic 1 - Power Supplies............................................................................................ 22
10 Schematic 2 - Power Distribution ........................................................................................ 23
11 Schematic 3 - DC-DC Regulator ......................................................................................... 24
12 Schematic 4 - LMK05318 and XO Input Interfaces.................................................................... 25
13 Schematic 5 - Clock Input Interfaces .................................................................................... 26
14 Schematic 6 - Clock Output Interfaces (OUT0 to OUT3) ............................................................. 27
15 Schematic 7 - Clock Outputs (OUT4 to OUT7) ........................................................................ 28
16 Schematic 8 - Logic I/O Interfaces....................................................................................... 29
17 Schematic 9 - USB MCU and I2C/SPI Jumper Block.................................................................. 30
18 Schematic 10 - LMK61E2 Oscillator..................................................................................... 31
19 Schematic 11 - DUT Test Socket ........................................................................................ 32
20 Top Composite View....................................................................................................... 33
21 Top Solder Mask ........................................................................................................... 34
22 Layer 1 (Top Side) - Clock I/Os, Logic, and Power Routing, Ground Fill........................................... 35
23 Layer 2 - Ground Plane ................................................................................................... 36
24 Layer 3 - Logic Routing, Ground Fill..................................................................................... 37
25 Layer 4 - Power Routing, Ground Fill.................................................................................... 38
26 Layer 5 - Power and Ground Planes .................................................................................... 39
27 Layer 6 - Logic Routing, Ground Fill..................................................................................... 40
28 Layer 7 - Ground Plane ................................................................................................... 41
29 Layer 8 (Bottom Side, View From Top) - Logic and Power Routing, Ground Fill.................................. 42
30 Bottom Solder Mask ....................................................................................................... 43
31 Bottom Composite View................................................................................................... 44

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List of Tables
List of Tables
1 Default Jumper and DIP Switch Settings ................................................................................ 7
2 Device Revision IDs......................................................................................................... 8
3 Default Configuration - EEPROM Start-Up Modes ..................................................................... 9
4 Device Start-Up Modes.................................................................................................... 10
5 Key EVM Components .................................................................................................... 11
6 Suggested DUT Power Configurations.................................................................................. 14
7 Suggested XO Power Configurations.................................................................................... 15
8 Logic Pin Mapping Tables................................................................................................. 15
9 Logic Pin Descriptions - EEPROM + I2C Mode (HW_SW_CTRL = 0) .............................................. 16
10 Logic Pin Descriptions - EEPROM + SPI Mode (HW_SW_CTRL = Float) ........................................ 17
11 Logic Pin Descriptions - ROM + I2C Mode (HW_SW_CTRL = 1).................................................... 18
12 Bill of Materials ............................................................................................................. 45

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Preface
Preface
SNAU236A–June 2018–Revised December 2018
Introduction
Overview
The LMK05318EVM is an evaluation module for the LMK05318 Network Clock Generator and
Synchronizer. The EVM can be used for device evaluation, compliance testing, and system prototyping.
The LMK05318 integrates two Analog PLLs (APLL) and one Digital PLL (DPLL) with programmable loop
bandwidth. The EVM includes SMA connectors for clock inputs, oscillator inputs, and clock outputs to
interface the device with 50-Ωtest equipment. The onboard XO allows the LMK05318 to be evaluated in
free-running, locked, or holdover mode of operation. The EVM can be configured through the onboard
USB microcontroller (MCU) interface using a PC with TI's TICS Pro software graphical user interface
(GUI). TICS Pro can be used to program the LMK05318 registers and on-chip EEPROM, which enables a
custom clock configuration on power up.
Trademarks
All trademarks are the property of their respective owners.
Features
• LMK05318 DUT:
– DPLL with programmable loop bandwidth for input jitter and wander attenuation
– Two Analog PLLs (APLLs) for flexible low-jitter clock generation
– Two clock inputs supporting hitless switching and holdover
– Eight differential clock outputs, or combination of differential and up to eight LVCMOS clocks
– On-chip EEPROM for custom start-up clocks
• SMA ports for clock input, oscillator inputs, and clock outputs
• Onboard oscillator options: 48.0048-MHz XO and LMK61E2 (I2C-programmable)
• USB MCU interface for I2C/SPI and GPIO pin control using TICS Pro GUI
• Status LEDs for power supplies and device status indicators
What is Included
• LMK05318EVM
• Mini-USB cable
What is Needed
• Windows PC with TICS Pro Software GUI
• Test Equipment
– DC power supply (5 V, 1 A)
– Real-time oscilloscope
– Source signal analyzer
– Precision frequency counter
– Signal generator / reference clock

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Introduction
Figure 1. LMK05318EVM With Default Jumper and DIP Switch Settings

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LMK05318EVM User's Guide
User's Guide
SNAU236A–June 2018–Revised December 2018
LMK05318EVM User's Guide
1 EVM Quick Start
This quick start guide can be followed to evaluate the LMK05318 DUT with the default EVM and device
configurations summarized in Section 1.2 and Table 3.
1. Verify the EVM default jumper and DIP switch settings shown in Figure 1 and Table 1:
Table 1. Default Jumper and DIP Switch Settings
CATEGORY REF DES POSITION DESCRIPTION
Power
JP1 Tie pins 1-2 DUT VDD = 3.3 V from LDO1
JP2 Tie pins 1-2 DUT VDDO = 1.8 V from LDO2
JP3 Tie pins 1-2 LDO3 IN powered from VIN1 external supply
JP4 Tie pins 1-2 1.8 V selected as LDO2 output voltage
JP16 Tie pins 1-2 VDDGPIO = 3.3 V
JP17 Tie pins 1-2 XO VCC = 3.3 V from LDO3
JP21 Tie pins 2-3 LMK61E2 VCC = GND (Powered off)
JP22 Tie pins 2-3 DC-DC Regulator VIN = GND (Powered off)
JP23 Tie pins 2-3
Communication JP20 Tie pins 1-2, 3-4,
11-12, and 13-14 DUT I2C connected to MCU
S9 S9[1:2] = OFF LMK61E2 I2C not connected to MCU
DUT Control
Pins
JP18 Tie pins 2-3 REFSEL = 0: PRIREF selected if using Manual Pin mode
JP19 Tie pins 2-3 HW_SW_CTRL = 0: EEPROM+I2C Start-up Mode selected
S2 S2[1:3] = OFF
S2[4] = ON STATUS0 = Hi-Z: Output state shown on D7. Pin not connected to MCU.
S3 S3[1:3] = OFF
S3[4] = ON STATUS1/FDEC = Hi-Z: Output state shown on D8. Pin not connected to MCU.
S5 S5[1] = ON
S5[2:3] = OFF GPIO0/SYNCN = 1: SYNC deasserted. Pin not connected from MCU.
S6 S6[1] = OFF
S6[2:3] = ON GPIO1/SCS = 0: I2C slave address = 0x64. Pin connected to MCU.
S7 S7[1] = OFF
S7[2:3] = ON GPIO2/SDO/FINC = 0: Not used by default. Pin connected to MCU.
DUT Loop Filter
Pins
S1 S1[1] = ON
S1[2:4] = OFF LF1 = 0.47 μF
S10 S10[1] = ON
S10[2] = OFF LF2 = 0.1 μF
2. Connect +5 V from an external DC power supply (1-A limit) across the VIN1 and GND terminals of
header J1 (pins 1 and 4).
3. Toggle switch S4 (PDN/RESET) to reinitialize the DUT registers from on-chip EEPROM, if needed.
4. Check that the LEDs D7 and D8 are both ON if there is no valid clock input on PRIREF or SECREF.
This indicates that the DPLL is not locked and that the DPLL holdover is active.
a. When the DPLL is not locked, the clock outputs will free-run and track the frequency stability and
accuracy of the XO (Y1).
5. Connect an external 25-MHz single-ended clock input to either the PRIREF or SECREF SMA port to

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lock the DPLL.
6. Check that the LEDs D7 and D8 are both OFF after a valid clock input is detected. This indicates the
that DPLL is locked and that the DPLL holdover is not active.
a. When the DPLL is locked, the output clocks should track the frequency accuracy of the clock input.
7. Check for any clock outputs on the OUT[0:7] SMA ports. TI recommends the following best practices
when making noise-sensitive performance measurements:
a. Use an appropriate balun to interface a differential output clock to the single-ended input of an RF
test equipment (phase noise or spectrum analyzer).
b. Properly terminate any active output clock trace by placing a 0-Ωload on the SMA port to minimize
noise due to reflections. Otherwise, disable any unused outputs by register programming.
NOTE: OUT7_P/N traces are DC-coupled to its SMA ports to allow evaluation of low-frequency
outputs (like 1 PPS) as well as LVCMOS or HCSL output types. Add an external DC blocking
cap between the OUT7 port and the input of any test equipment that cannot tolerate DC
bias.
8. Connect the USB cable from connector J35 to the PC and configure the device through the TICS Pro
software to program the LMK05318 through the USB interface.
a. See Appendix A for TICS Pro installation and usage.
TICS Pro uses the "USB2ANY" API software driver to control the USB MCU interfaces (I2C/SPI and Logic
pins) on the EVM. TICS Pro can be used to access the device registers and program the device EEPROM
for a different start-up configuration.
1.1 Device Revision Identification
Pre-production devices may have been distributed to customers as engineering sample parts or mounted
on pre-release EVMs. If a pre-production device or EVM is detected, TI recommends that the user replace
the pre-production device with a production device or EVM when available. Production samples and EVMs
can be ordered from product folder or requested through your local TI Field Sales representative.
The user can read the Device Revision ID (REVID) Register R3 to find the device revision in the TICS Pro
GUI or other serial host interface. See Table 2.
Table 2. Device Revision IDs
REVID REGISTER R3 VALUE DEVICE REVISION COMMENT
0x00 Pre-production device TI recommends to replace with a production device or EVM,
or contact TI Field Sales for technical support.
0x11 Production device Okay to use.
1.2 Default EVM Configuration
• Power Supplies:
– VIN1: 5 V (External supply to onboard LDO regulators)
– DUT VDD: 3.3 V from LDO1 (U3)
– DUT VDDO: 1.8 V from LDO2 (U3)
– XO: 3.3 V from LDO3 (U4)
– VDDGPIO: 3.3 V from VDD
• LMK05318 DUT (U5):
– Clock Inputs:
• PRIREF and SECREF: DC-coupled from SMA ports
– Clock Outputs:
• OUT[0:6]: AC-coupled to SMA ports
• OUT7: DC-coupled to SMA ports

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• Oscillators onboard:
– XO (Y1), Default: 48.0048 MHz, 3.3 V, LVCMOS, low-jitter, ±25-ppm stability
– XO (U10), Alternate: LMK61E2, 10 to 1000 MHz (I2C-programmable), 3.3 V, Differential, low-jitter,
±50-ppm stability
NOTE: The EEPROM image of the LMK05318 was custom programmed to demonstrate the default
configuration in Table 3, which is different from the EEPROM image of generic factory-
programmed devices.
(1) Clock input frequency thresholds (ppm) are relative to the frequency accuracy of the XO input.
Table 3. Default Configuration - EEPROM Start-Up Modes
DEVICE START-UP MODE EEPROM + I2C MODE
(HW_SW_CTRL = 0) EEPROM + SPI MODE (HW_SW_CTRL = Float)
HW_SW_CTRL (JP19)
Jumper Setting Tie pins 2-3 Tie pins 2-4 (open)
MCU I2C/SPI (JP20)
Jumper Settings Tie pins 1-2, 3-4, 11-12 and 13-14 MCU I2C interface to DUT Tie pins 7-8, 9-10, 11-12, and 13-14 MCU SPI interface to DUT
GPIO1/SCS (S6)
Jumper Settings S6[1] = OFF, S6[2:3] = ON GPIO1 = 0: I2C Address = 0x64h S6[1] = OFF, S6[2:3] = ON SPI SCS input to MCU
GPIO2/SDO/FINC (S7)
Jumper Settings S7[1] = OFF, S7[2:3] = ON Not used by default S7[1] = OFF, S7[2:3] = ON SPI SDO output to MCU
XO Input 48.0048-MHz DIFF or LVCMOS
(On-chip termination disabled)
PRIREF and SECREF Clock Inputs 25-MHz DIFF or LVCMOS
(On-chip termination disabled)
DPLL Clock Input Assignment PRIREF, SECREF
(Highest to lowest priority order)
DPLL Clock Input Selection Manual Fallback mode with Pin Select
PLL Mode DPLL Mode with APLL2 disabled
DPLL Loop Bandwidth 100 Hz
DPLL TDC Frequency 25 MHz
APLL1 VCO Frequency 2500 MHz
APLL2 VCO Frequency n/a (APLL2 disabled)
OUT[0:1] Output 156.25 MHz AC-LVPECL (from APLL1)
OUT[2:3] Output 156.25 MHz AC-LVPECL (from APLL1)
OUT[4] Output 156.25 MHz AC-LVPECL (from APLL1)
OUT[5] Output 156.25 MHz AC-LVPECL (from APLL1)
OUT[6] Output 156.25 MHz AC-LVPECL (from APLL1)
OUT[7] Output 156.25 MHz HCSL (from APLL1)
(On-chip termination disabled)
PRIREF and SECREF
Frequency Detector Thresholds (1) Not Enabled
PRIREF and SECREF
Window Detector Thresholds 33.6 ns (Early) < Valid REF Input Period < 46.4 ns (Late)
DPLL Frequency Lock
Detector Thresholds DPLL Locked < 1 ppm, DPLL Unlocked > 10 ppm
STATUS0 Output DPLL Loss of Lock (active high)
STATUS1 Output DPLL Holdover Active (active high)

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2 Device Under Test
The evaluation module is shipped with the LMK05318 DUT (U5) soldered down. The pin 1 position of the
48-pin QFN package is indicated by a dot symbol in top silkscreen. Alternatively, the U5 can be
unmounted and a test socket (XU1) can be populated. See for the socket part number. TI recommends
populating the socket with the hinge on the left-hand side (towards OUT[0:3] ports) and the latch on the
right-hand side.
2.1 Device Start-Up Modes
The LMK05318 can start-up in one of three modes depending on the 3-level input level sampled on the
HW_SW_CTRL pin upon power-on reset (POR). The start-up modes are listed in Table 4 and determine
the following:
1. The memory bank (EEPROM or ROM) used to initialize the registers upon start-up.
2. The serial interface (I2C or SPI) used for register access.
3. The logic pin definitions.
The I2C or SPI interface allows for register access to configure the device after start-up and monitor its
status. The register map configurations are the same for I2C and SPI.
See Section 3.2 for detailed descriptions of the logic pins for each start-up mode.
(1) The input levels on these pins are sampled only during POR.
(2) FINC and FDEC pin controls are only available when DCO mode and GPIO pin control are enabled by registers.
Table 4. Device Start-Up Modes
HW_SW_CTRL(1)
INPUT LEVEL START-UP MODE MODE DESCRIPTION
0EEPROM + I2C
(Soft pin mode)
Registers are initialized from EEPROM, and I2C interface is enabled with slave
address 11001xxb. Logic pins:
• SDA/SDI, SCL/SCK: I2C Data, I2C Clock
• GPIO0/SYNCN: Output Sync (active low)
• GPIO1/SCS(1): I2C Address LSB Select (Low = 00b, Float = 01b, High = 10b)
• GPIO2/SDO/FINC(2): DPLL DCO Frequency Increment (active high)
• STATUS1/FDEC(2): DPLL DCO Frequency Decrement (active high), or Status
output
Float
(VIM)EEPROM + SPI (Soft pin mode)
Registers are initialized from EEPROM, and SPI interface is enabled. Logic pins:
• SDA/SDI, SCL/SCK: SPI Data In (SDI), SPI Clock (SCK)
• GPIO0/SYNCN: Output Sync (active low)
• GPIO1/SCS: SPI Chip Select (SCS)
• GPIO2/SDO/FINC: SPI Data Out (SDO)
1ROM + I2C
(Hard pin mode)
Registers are initialized from the ROM page selected by GPIO pins, and I2C interface
is enabled with the 7-bit slave address of 0x64. Logic pins:
• SDA/SDI, SCL/SCK: I2C Data, I2C Clock
• GPIO[2:0](1): ROM page select at POR
• After POR, GPIO2/SDO/FINC and STATUS1/FDEC pins can function the same
as for HW_SW_CTRL = 0 if enabled by registers.
TI suggests to use the EEPROM mode when either of the following is true:
• A single custom start-up frequency configuration is required from a single OPN.
• A host device is able to program the registers (and EEPROM, if needed) with a new configuration after
power-up through I2C or SPI. SPI is not supported by ROM mode.

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NOTE: To ensure proper start-up into EEPROM + SPI Mode, the HW_SW_CTRL, STATUS0, and
STATUS1/FDEC pins must all be floating or biased to VIM (0.8-V typical) before the PDN pin
is pulled high. These three pins momentarily operate as 3-level inputs and get sampled at
the low-to-high transition of PDN to determine the device start-up mode during POR. If any of
these pins are connected to a host device (MCU or FPGA), TI recommends using external
biasing resistors on each pin (10-kΩpullup to 3.3 V with 3.3-kΩpulldown to GND) to set the
inputs to VIM during POR. After power-up, the STATUS pins can operate as LVCMOS
outputs and overdrive the external resistor bias for normal status operation.
3 EVM Configuration
The LMK05318 is a highly configurable clock chip with multiple power domains, PLL domains, and clock
input and output domains. To support a wide range of LMK05318 use cases, the EVM was designed with
more flexibility and functionality than needed to implement the chip in a customer system application.
This section describes the power, logic, and clock input and output interfaces on the EVM, as well as how
to connect, set up, and operate the EVM.
An overview of some key components are shown in Table 5,Figure 2, and Figure 3.
Table 5. Key EVM Components
ITEM NO. REF DES DESCRIPTION
1 U5 LMK05318 DUT
2A VIN1 (terminal) or External Supply Input (+5 V using default configuration)
B J2 (SMA)
3
A Y1 or Y1: 48.0048-MHz XO (Default). Located on bottom side.
B J4/J5 or J4/J5: SMA Ports for External XO_P/N input clock.
Requires minor rework before first use (see Section 3.3.1).
C U10 U10: LMK61E2 Programmable OSC.
Requires minor rework before first use (see Section 3.3.3).
4 J6/J7 and J8/J9 SMA Ports for DUT Clock Inputs (PRIREF_P/N and SECREF_P/N)
5J12/J13, J14/J15,
J18/J19, J20/J21,
J24/25, J26/J27,
J30/J31, J32/J33 SMA Ports for DUT Clock Outputs (OUT0_P/N to OUT7_P/N)
6 S4 Toggle Switch for DUT Power-Down/Reset (PDN pin)
7 JP18 Jumper for DUT Clock Input Selection (REFSEL)
8 D7, D8 Status LEDs for DUT STATUS[0:1] pins
9 JP20 Jumpers Header for I2C/SPI interface (MCU to DUT)
10 J35 USB Port for MCU

OUT0_P
OUT0_N
OUT1_N
OUT1_P
OUT2_P
OUT2_N
OUT3_N
OUT3_P
OUT7_P
OUT7_N
OUT6_N
OUT6_P
OUT5_P
OUT5_N
OUT4_P
OUT4_N
PRIREF_P
PRIREF_N
SECREF_P
SECREF_N
2B
2A
3B
3C
1
4
55
6
7
8
9
10
VIN1
VIN2
1: LMK05318 DUT
2A: SMA Main Supply Input
2B: Terminal Main Supply Input
3B: SMA Ports for External XO
3C: Programmable XO
4: Reference Clock Inputs
5: Clock Outputs
6: PDN switch
7: Jumper for DPLL input sel.
8: Status LEDS
9: I2C/SPI Jumpers
10: USB port
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Figure 2. Key Components - EVM Top Side

3A
OUT0_P
OUT0_N
OUT1_N
OUT1_P
OUT2_P
OUT2_N
OUT3_N
OUT3_P
OUT7_P
OUT7_N
OUT6_N
OUT6_P
OUT5_P
OUT5_N
OUT4_P
OUT4_N
PRIREF_P
PRIREF_N
SECREF_P
SECREF_N
VIN1
VIN2
4
2B
2B: Terminal Main Supply Input
3A: 48.0048-MHz XO
4: Reference Clock Inputs
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Figure 3. Key Components - EVM Bottom Side
3.1 Power Supply
The LMK05318 has five core VDD supply pins that operate from 3.3 V ± 5% and six output VDDO supply
pins that operate from 1.8 V, 2.5 V, or 3.3 V ± 5%.
J1 is the main power terminal to the external power supply. Power SMA port VIN1 (J2) provides an
alternative connector style to apply power through coax cable.

5V
VDD: Select
3.3 V LDO1
LDO2 Output
Voltage (1.8 V)
VCCXO:
Select 3.3 V
from LDO3
VDDO:
Select LDO2
Out Voltage
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On the EVM, the default power configuration uses the onboard LDO regulators to power all VDD and
VDDO pins from an external 5-V supply input VIN1 to J1 (or J2). A Dual LDO regulator (U3) is used to
power the VDD and VDDO rails of the DUT and its peripheral circuitry. A separate LDO regulator (U4),
also supplied from VIN1, is used to power the onboard XO circuits.
NOTE: Not every power connection is used or required to operate the EVM. Other power
configurations are possible. See the power schematics in Figure 9,Figure 10, and Figure 11.
Figure 4 shows the default power jumper locations and settings.
Figure 4. Default Power Jumper Configuration
Table 6 shows the suggested power configurations for the DUT.
(1) The SMA ports J2 or J3 can be used to power VIN1 or VIN2, respectively, through a coaxial cable instead of using power cables
to J1.
Table 6. Suggested DUT Power Configurations
CONNECTION NAME
ONBOARD LDO REGULATORS
(DEFAULT) DIRECT EXTERNAL SUPPLIES
VDD = 3.3 V (LDO1)
VDDO = 1.8 / 2.5 / 3.3 V (LDO2) VDD = 3.3 V (EXT. VIN1) VDDO = 1.8 / 2.5 / 3.3 V (EXT. VIN2)
J1(1) PWR Pin 1 (VIN1): Connect to external 5-V supply
Pin 2 (VIN2): n/a
Pin 3 (VIN3): n/a
Pin 4 (GND): Connect to supply ground
Pin 1 (VIN1): Connect to external 3.3-V supply
Pin 2 (VIN2): Connect to external 1.8-V, 2.5-V,
or 3.3-V supply
Pin 3 (VIN3): n/a
Pin 4 (GND): Connect to supply ground
JP1 VDD Tie pins 1-2: Selects 3.3 V from LDO1 to VDD
Plane Tie pins 2-3:
Selects ext. 3.3V supply from VIN1 to VDD
Plane
JP2 VDDO Tie pins 1-2: Selects LDO2 output to VDDO
Plane Tie pins 2-3: Selects ext. supply from VIN2 to VDDO Plane
JP4 VOUT2 Tie pins 1-2: LDO2 out = 1.8 V (default) Tie pins 3-4: LDO2 out = 2.5 V
Tie pins 5-6: LDO2 out = 3.3 V n/a

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Table 7 shows the suggested power configurations for the onboard XO circuits.
Table 7. Suggested XO Power Configurations
CONNECTION NAME ONBOARD LDO REGULATOR
(DEFAULT) DIRECT EXTERNAL SUPPLY
LDO3 = 3.3 V (VIN3) VCCXO or VCCLMK6 = 3.3 V
J1 PWR Pin 1 (VIN1): Connect to external 5-V supply
Pin 2 (VIN2): n/a
Pin 3 (VIN3): n/a
Pin 4 (GND): Connect to supply ground n/a
JP3 LDO3 IN Tie pins 1-2: Selects 5 V from VIN1 to LDO3 IN n/a
JP17 VCCXO Tie pins 1-2: Select 3.3 V from LDO3 Pin 1 (LDO3): Open
Pin 2 (VCCXO): Connect to external 3.3-V
supply
Pin 3 (GND): Connect to external supply ground
JP21 VCCLMK6 Tie pins 1-2: Selects 3.3 V from LDO3 Pin 1 (LDO3): Open
Pin 2 (VCCLMK6): Connect to external 3.3-V
supply
Pin 3 (GND): Connect to external supply ground
NOTE: Disconnect the power and signal paths from any XO circuit that is not used for a given
configuration to avoid unwanted noise coupling.
3.2 Logic Inputs and Outputs
The logic I/O pins of the DUT support different functions depending on the device start-up mode chosen
by the HW_SW_CTRL input level upon POR. The STATUS[0:1] pins are programmable and can be used
to monitor a variety of different device statuses.
The default logic input pin states are determined by onboard pullup or pulldown resistors, but some input
pins can be driven to high or low state by the MCU output or DIP switch control. The MCU can be
controlled from a PC running TICS Pro software to program the device registers through I2C or SPI and
also drive the DUT logic inputs.
See Table 8 for the logic pin mapping tables for the device start-up modes.
Table 8. Logic Pin Mapping Tables
HW_SW_CTRL
(JP19) START-UP MODE LOGIC PIN MAPPING TABLE
0
(Tie pins 2-3) EEPROM + I2C (Default) See Table 9
Float
(Tie pins 2-4) EEPROM + SPI See Table 10
1
(Tie pins 1-2) ROM + I2C See Table 11
Logic pins not listed in Table 10 or Table 11 are the same as described in Table 9.

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Table 9. Logic Pin Descriptions - EEPROM + I2C Mode (HW_SW_CTRL = 0)
PIN NAME (TYPE) DESCRIPTION
PDN
(2-level input)
Chip Power-Down/Reset (active low)
When PDN rises to 1, the digital control block triggers the internal POR sequence, initializes all the registers
and logic pins for the start-up mode selected by the HW_SW_CTRL input level, restores all the internal
circuits including the serial interface to their initial state, and begins normal operation.
This pin is pulled high through an external pullup resistor, but can be pulled down by pushing toggle switch
S4.
PDN STATE S4 CHIP STATE
0 Pushed Power-down/reset state: Serial interface disabled
1 (Default) Released Normal operation
SDA/SDI
(Open-drain input)
I2C Data (SDA)
The I2C interface between the DUT and MCU connects through two jumpers on JP20.
Tie JP20 pins 1-2 (SDA) and pins 3-4 (SCL) to connect the MCU and DUT to allow register programming
through I2C. Remove jumpers from JP20 pins 7-8 and pins 9-10 so the MCU SPI SCK and SDI pins are not
connected simultaneously.
Also, it is possible to use the EVM to program an off-board LMK05318 DUT by removing the I2C jumpers
from JP20, and connecting the MCU side (JP20 pins 1, 3, and 5) to the SDA, SCL, and GND lines of the
DUT on the target board. The MCU side of JP20 has external I2C pullup resistors to 3.3 V, which is derived
a dedicated regulator powered off the USB port 5-V supply.
SCL/SCK
(Open-drain input) I2C Clock (SCL)
See SDA/SDI pin description above. Red LED (D12) will turn ON during I2C activity.
GPIO0/SYNCN
(2-level input)
Output Synchronization (active low)
GPIO0 (SYNCN) can be used to mute the output clocks and trigger output divider synchronization (SYNC) if
the divider SYNC bits are enabled by registers. Alternatively, SYNC can be triggered through register
programming instead of using this pin.
This pin is set through a 3-position DIP switch (S5). When S5[2] = ON (default), the pin is connected to the
MCU and can be driven 0 or 1 by software control. When S5[2] = OFF, the pullup or pulldown resistor switch
determines the GPIO0 state.
GPIO0 STATE S5 (0=OFF, 1=ON) OUTPUT SYNC STATE
0 S5[1:3] = 001 SYNC asserted: Outputs muted and output dividers held
in reset
1 (Default) S5[1:3] = 100 SYNC deasserted: Normal output operation
GPIO1/SCS
(3-level input)
I2C Slave Address LSB Select
GPIO1 is sampled on POR to configure the lower 2 bits of the 7-bit I2C address after start-up. The upper 5
bits of the I2C address are initialized from EEPROM (SLAVEADR[7:3] = 11001b).
This pin is set through a 3-position DIP switch (S6). When S6[2] = ON (default), the pin is connected to the
MCU and can be driven 0 or 1 by software control. When S6[2] = OFF, the pullup or pulldown resistor switch
determines the GPIO1 state.
GPIO1 STATE S6 (0=OFF, 1=ON) 7-BIT SLAVE ADDRESS
0 (Default) S6[1:3] = 001 1100100b (0x64h)
Float S6[1:3] = 000 1100101b (0x65h)
1 S6[1:3] = 100 1100111b (0x66h)
GPIO2/SDO/FINC
(2-level input)
DPLL DCO Mode Frequency Increment (FINC)
When DCO mode and GPIO pin control are enabled by registers, a high pulse on the FINC input will
increment the DCO numerator by the programmable frequency deviation (FDEV) step size to adjust its
frequency.
This pin is set through a 3-position DIP switch (S7). When S7[2] = ON (default), the pin is connected to the
MCU and can be pulsed by software control. Alternatively, FINC can be triggered through register
programming without using this pin. When S7[2] = OFF, the pullup or pulldown switch determines the state.
FINC STATE S7 (0=OFF, 1=ON) DPLL DCO NUMERATOR
0S7[1:3] = X1X
(MCU driven) No update
1 (Pulsed by MCU pin) Incremented

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Table 9. Logic Pin Descriptions - EEPROM + I2C Mode (HW_SW_CTRL = 0) (continued)
PIN NAME (TYPE) DESCRIPTION
REFSEL
(2-level inputs)
DPLL Reference Clock Input Selection
The REFSEL pin selects the DPLL reference clock input when Manual Input Select mode and HW Pin
Control mode are selected by register configuration. This pin is ignored when Auto Input Select mode or SW
Register Control mode is selected.
This pin is set through a 3-way jumper (J18). When JP18 pins 2-4 are tied, the REFSEL pin is connected to
the MCU and can be driven 0 or 1 by software control. Otherwise, the REFSEL state is determined by the
other JP18 options below.
REFSEL STATE JP18 DPLL REF INPUT
0 (Default) Tie pins 2-3 PRIREF
Float Open pin 2 Auto Select
1 Tie pins 1-2 SECREF
STATUS0,
STATUS1/FDEC
(Logic outputs)
Status Outputs
Each STATUS pin is a programmable status output that supports NMOS open-drain or 3.3-V LVCMOS
driver type. When S2[4] and S3[4] = ON, the output states of STATUS0 and STATUS1 are shown on active-
high LEDs D7 and D8, respectively. If STATUS0 or STATUS1 is configured as an open-drain driver, a 10-kΩ
pullup to VDDGPIO can be connected by setting S2[1] or S3[1] = ON.
DPLL DCO Mode Frequency Decrement (FDEC)
When DCO mode and GPIO pin control are enabled by registers, a high pulse on the FDEC input will
decrement the DCO numerator by the programmable frequency deviation (FDEV) step size to adjust its
frequency.
This pin is set through a 4-position DIP switch (S3). When S3[2] = ON, the pin is connected to the MCU and
can be pulsed by software control. Alternatively, FDEC can be triggered through register programming
without using this pin. When S3[2] = OFF, the pullup or pulldown switch determines the state.
FDEC STATE S3 (0=OFF, 1=ON) DPLL DCO NUMERATOR
0S3[1:3] = X1X
(MCU driven) No update
1 (Pulsed by MCU pin) Decremented
(1) Logic pins not listed in Table 10 are the same as described in Table 9.
(2) When HW_SW_CTRL = Float, STATUS[1:0] pins must not be pulled high or low externally during POR to ensure proper start-up
into EEPROM+SPI Mode.
Table 10. Logic Pin Descriptions - EEPROM + SPI Mode (HW_SW_CTRL = Float) (1) (2)
PIN NAME (TYPE) DESCRIPTION
SDA/SDI
(2-level input)
SPI Data In (SDI / SIMO)
The SPI interface between the DUT and MCU can be connected using four jumpers on JP20.
Tie JP20 pins 7-8 (SCL), pins 9-10 (SCL), pins 11-12 (SDO), and pins 13-14 (SCS) to connect the MCU and
DUT to allow register programming through SPI. Remove jumpers from JP20 pins 1-2 and pins 3-4, so the
MCU I2C pins are not connected simultaneously.
Also, it is possible to use the EVM to program an off-board LMK05318 DUT by removing the SPI jumpers
from JP20, and connecting the MCU side (JP20 pins 5, 7, 9, 11, and 13) to the GND, SCL, SDI, SDO, and
SCS lines of the DUT on the target board.
SCL/SCK
(2-level input) SPI Clock (SCK)
See SDA/SDI pin description above. Red LED (D12) will turn ON during SPI activity.
GPIO1/SCS
(2-level input) SPI Chip Select (SCS)
See SDA/SDI pin description above.
GPIO2/SDO/FINC
(2-level input) SPI Data Out (SDO / SOMI)
See SDA/SDI pin description above.
STATUS0,
STATUS1
(Logic outputs)
Status Outputs
Both STATUS pins must be allowed to float during POR to ensure proper start-up into EEPROM+SPI Mode.
This means S2[1:3] and S3[1:3] must all be switched OFF during POR.
Each STATUS pin is a programmable status output that supports NMOS open-drain or 3.3-V LVCMOS
driver type. However, the 3.3-V LVCMOS driver type is recommended because external pullup resistors
must be avoided on the STATUS pins during POR when using EEPROM+SPI Mode. When S2[4] and S3[4]
= ON, the output states of STATUS0 and STATUS1 are shown on active-high LEDs D7 and D8,
respectively.
Note that DCO pin control is not supported in EEPROM+SPI mode.

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(1) Logic pins not listed in Table 11 are the same as described in Table 9.
(2) In ROM + I2C Mode, the two I2C address LSBs are forced to 00b (address = 0x64h).
Table 11. Logic Pin Descriptions - ROM + I2C Mode (HW_SW_CTRL = 1)(1)(2)
PIN NAME (TYPE) DESCRIPTION
GPIO[2:0]
(2-level inputs)
GPIO[2:0] Function at POR: ROM Page Selection
GPIO[2:0] pins are sampled on POR to select the ROM page settings used to initialize the registers.
The GPIO[2:0] pins are controlled by S7, S6, and S5, respectively. To configure GPIO[2:0] pins through the
pullup or pulldown resistors only (disable MCU control), set S5[2], S6[2], and S7[2] to OFF. Then, GPIOx
can be pulled up by setting Sy[1] = ON and Sy[3] = OFF, or else pulled down by setting Sy[1] = OFF and
Sy[3] = ON.
GPIO2 Function after POR: DPLL DCO Mode Frequency Increment (FINC)
After POR, the GPIO2 pin can be operated as an FINC input in the same way described for EEPROM + I2C
mode (see the GPIO2/FINC description in Table 9).
GPIO[2:0] STATES ROM PAGE SELECT
000b (Default) ROM Page 0
001b ROM Page 1
010b ROM Page 2
... ...
110b ROM Page 6
111b ROM Page 7
STATUS0,
STATUS1/FDEC
(Logic outputs)
Status Outputs
STATUS[1:0] pins are individually programmable status outputs that support NMOS open-drain (requires
external pullup resistor) or 3.3-V LVCMOS driver type. The state of these pins is shown by D7 and D8 when
S2[4] and S3[4] are ON, respectively.
DPLL DCO Mode Frequency Decrement (FDEC)
After POR, the STATUS1 pin can be operated as an FDEC input in the same way described for EEPROM +
I2C mode (see the STATUS1/FDEC description in Table 9).
3.3 XO Input
The LMK05318 has an XO input (XO_P/N pins) to accept a reference clock for the Fractional-N APLLs.
The XO input determines the output frequency accuracy and stability in free-run or holdover modes. For
synchronization applications like SyncE or IEEE 1588, the XO input would typically be driven by a low-
frequency TCXO, OCXO, or external traceable clock that conforms to the frequency accuracy and
holdover stability requirements of the application. For DPLL mode, the XO frequency must have a non-
integer frequency relationship with the VCO1 frequency so APLL1 operates in Fractional mode. For APLL
only mode (DPLL not used), the XO frequency can have an integer relationship with the VCO1 and/or
VCO2 frequencies to avoid fractional spurs.
The XO input of the LMK05318 has programmable on-chip input termination and AC-coupled input biasing
options to support any clock interface type.
For flexibility, the EVM provides the three XO input options (use one at a time).
3.3.1 48.0048-MHz Oscillator (Default)
By default, the EVM is populated with a 48.0048-MHz, 3.3-V LVCMOS, low-jitter oscillator (Y1) to drive the
XO_P input of the DUT with the onboard termination and AC coupling. See Figure 5. Y1 can be used to
evaluate various frequency configurations. Y1 has multiple overlapped 4-pin SMD footprints (2.5×2.0,
3.2×2.5, 5×7, or 9×14-mm sizes) that allows the user to rework a different XO frequency/model after the
pre-installed component is carefully removed.
3.3.2 External Clock Input
Another option is to feed an external clock to the SMA ports (J5/J4) to drive the XO_P/N inputs
(differential) or XO_P input (single-ended). See Figure 5. This path can be connected to the XO_P/N input
pins by placing 0.1-µF capacitors on C81 and C82 and opening C80, C137, and C138. Y1 and U10 should
be powered down when using the external XO input path.

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NOTE: Disconnect the power and signal paths from any XO circuit that is not used for a given
configuration to avoid unwanted spurious noise on the board. Y1 can be powered down by
JP17 (Tie pins 2-3). U10 can be powered down by JP21 (Tie pins 2-3).
Figure 5. XO Input Interface (1 of 2) - 48.0048-MHz Oscillator and SMA Ports
3.3.3 LMK61E2 Programmable Oscillator
The last option is to use the other onboard LMK61E2 programmable oscillator (U10) to drive the XO_P/N
inputs. See Figure 6.
The differential output clock from U10 can be routed to the XO_P/N input pins with minimal rework by
placing 0.1-µF capacitors on C137 and C138, and opening C80, C81, and C82 (note: C137 shares a pad
with C80 and C81, and C138 shares a pad with C82). U10 can be powered by a clean 3.3-V supply from
LDO3 by tying JP21 pins 1-2.

1
2 3 4 5
J6
PRIREF_P
1
2 3 4 5
J7
PRIREF_N
SMA_PRI_P
SMA_PRI_N
0
C86
0
C87
0
R47
0
R46
0
R57
0
R56
49.9
R50
DNP 49.9
R52
DNP
C_PRI_P
C_PRI_N
R_PRI_P
R_PRI_N
100
R54
DNP
PRIREF_P
PRIREF_N
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U10 can be configured to output any other supported XO frequency by programming it through the I2C
interface of the MCU. To connect U10 to the I2C bus (shared with the DUT), set switches S9[1:2] to the
ON positions. The user can select the LMK61E2 device profile in TICS Pro, scan the I2C bus to detect
U10 at address 0x58, configure the output to a different frequency, and store the new configuration to the
LMK61E2's internal EEPROM if desired. After U10 has been programmed, set S9[1:2] to the OFF
positions to disconnect it from the I2C bus.
Figure 6. XO Input Interface (2 of 2) - LMK61E2 Oscillator
3.4 Reference Clock Inputs
The LMK05318 has two DPLL reference clock input pairs (PRIREF_P/N and SECREF_P/N) with
configurable input priority and input selection modes. The inputs have programmable input type,
termination, and biasing options to support any clock interface type.
External LVCMOS or Differential reference clock inputs can be applied to the SMA ports, labeled
PRIREF_P/N and SECREF_P/N. All SMA inputs are routed through 50-Ωsingle-ended traces and DC-
coupled to the corresponding PRIREF_P/N and SECREF_P/N pins of the DUT.
Figure 7. Clock Input Interface - PRIREF (Similar for SECREF)
3.5 Clock Outputs
The LMK05318 has eight clock output pairs (OUT[0:7]_P/N) that can be sourced from either APLL
domain.