Texas Instruments DAC8742H User manual

1
SLAU700A–June 2017–Revised November 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
DAC8742H Evaluation Module
User's Guide
SLAU700A–June 2017–Revised November 2017
DAC8742H Evaluation Module
This user's guide describes the characteristics, operation, and use of the DAC8742H evaluation board
(EVM). This user’s guide also discusses the proper setup and configuration of both software and
hardware, and reviews various aspects of program operation. A complete circuit description, schematic
diagram, and bill of materials are also included in this document.
Contents
1 Overview...................................................................................................................... 3
1.1 DAC8742HEVM Kit Contents ..................................................................................... 3
1.2 Related Documentation From Texas Instruments.............................................................. 3
2 DAC8742HEVM Hardware Setup ......................................................................................... 4
2.1 DAC8742H Hardware Theory of Operation ..................................................................... 4
2.2 USB2ANY Signal Definition ....................................................................................... 5
3 DAC8742HEVM Software Setup .......................................................................................... 6
3.1 Operating Systems for DAC8742HEVM Software.............................................................. 6
3.2 DAC8742H Software Installation ................................................................................. 6
4 DAC8742HEVM Hardware Overview ..................................................................................... 7
4.1 Electrostatic Discharge Warning.................................................................................. 7
4.2 Connecting the Hardware.......................................................................................... 7
4.3 DAC8742HEVM Power Configurations .......................................................................... 7
4.4 DAC8742H Reference Connection............................................................................... 8
4.5 Digital Inputs......................................................................................................... 8
4.6 Clock Configuration................................................................................................. 9
4.7 HART/PAFF Shunt Selection.................................................................................... 10
5 DAC8742HEVM Software Overview .................................................................................... 11
5.1 Starting the DAC8742HEVM Software ......................................................................... 11
5.2 DAC8742HEVM Software Features ............................................................................ 12
6 DAC8742HEVM Documentation ......................................................................................... 16
6.1 DAC8742HEVM Board Schematic.............................................................................. 17
6.2 DAC8742HEVM PCB Components Layout.................................................................... 18
6.3 DAC8742H Test Board Bill of Materials........................................................................ 19
List of Figures
1 DAC8742HEVM Hardware Setup ......................................................................................... 4
2 DAC8742H Test Board Block Diagram................................................................................... 4
3 Launching Software Setup ................................................................................................. 6
4 DAC8742HEVM GUI Location............................................................................................ 11
5 DAC8742HEVM GUI – Power On ....................................................................................... 11
6 DAC8742H EVM Software Page Selection............................................................................. 12
7 Low Level Configuration Page............................................................................................ 13
8 Low Level Configuration Page Available Options...................................................................... 13
9 High Level Configuration Page........................................................................................... 14
10 MODE Section.............................................................................................................. 15
11 DAC8742HEVM Digital Input Selection ................................................................................. 15
12 HART/PAFF Write/Read Control and Indicator Section............................................................... 16
13 DAC8742HEVM Board Schematic....................................................................................... 17

www.ti.com
2SLAU700A–June 2017–Revised November 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
DAC8742H Evaluation Module
14 DAC8742HEVM PCB Components Layout............................................................................. 18
List of Tables
1 Contents of DAC8742H Kit................................................................................................. 3
2 Related Documentation..................................................................................................... 3
3 J2 USB2ANY and Digital Signal Definition............................................................................... 5
4 Default Jumper Settings .................................................................................................... 7
5 DAC8742HEVM Power Supply Configuration ........................................................................... 7
6 DAC8742HEVM Reference Connection.................................................................................. 8
7 Digital Signal Definition ..................................................................................................... 8
8 J6 Digital Signal Definition.................................................................................................. 8
9 Clock Configuration.......................................................................................................... 9
10 XTAL1 and XTAL2 Configuration Settings ............................................................................... 9
11 Internal Mode Shunt Selection ........................................................................................... 10
12 External Filter Mode With Internal REF Shunt Selection ............................................................. 10
13 DAC8742H Test Board Bill of Materials................................................................................. 19
Trademarks
Microsoft, Windows are registered trademarks of Microsoft Corporation.
LabVIEW is a trademark of National Instruments Corporation.
All other trademarks are the property of their respective owners.

www.ti.com Overview
3
SLAU700A–June 2017–Revised November 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
DAC8742H Evaluation Module
1 Overview
This EVM features the DAC8742H device, which is a Highway Addressable Remote Transducer (HART),
FOUNDATION Fieldbus (FF), and Profibus process automation (PA) compliant low-power frequency-shift
keying (FSK) modem designed for industrial process control and industrial automation applications. The
device includes an integrated receive band-pass filter, flexible clocking options and can operate from a
1.8- to 5.5-V range. The wide temperature range, –55°C to 125°C, and low quiescent current make this
device an ideal candidate for smart transmitters, programmable-logic controller (PLC) I/O modules, and
other industrial process-control applications.
1.1 DAC8742HEVM Kit Contents
Table 1 details the contents of the kit. Contact the TI Product Information Center or visit the Texas
Instruments E2E Community (http://E2E.ti.com) if any component is missing. TI highly recommends that
the user verify the latest versions of the related software at the TI website, www.ti.com.
Table 1. Contents of DAC8742H Kit
Item Quantity
DAC8742HEVM PCB evaluation board 1
USB2ANY 1
1.2 Related Documentation From Texas Instruments
The following document provides information regarding Texas Instruments integrated circuits used in the
assembly of the DAC8742HEVM. This user's guide is available from the TI web site under literature
number SLAU700. Any letter appended to the literature number corresponds to the document revision that
is current at the time of the writing of this document. Newer revisions may be available from the TI web
site at http://www.ti.com/, or call the Texas Instruments Literature Response Center at [phone] or
the Product Information Center at [phone]. When ordering, identify the document by both title and
literature number.
Table 2. Related Documentation
Document Literature Number
DAC8742H data sheet SBAS856
USB2ANY SBOU136

(Optional)
External/Onboard REF
USB2ANY
Connection
(HART/PAFF)
TX/RX
Optional External Power
(AVDD/IOVDD)
DAC8742H
SPI
Power
Copyright © 2017, Texas Instruments Incorporated
DAC8742HEVM
USB Bus
from
Computer
(Optional) External
Power Source
LaunchPad
Connector
USB2ANY
Personal
Computer
(PC)
Copyright © 2017, Texas Instruments Incorporated
DAC8742HEVM Hardware Setup www.ti.com
4SLAU700A–June 2017–Revised November 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
DAC8742H Evaluation Module
2 DAC8742HEVM Hardware Setup
This section provides the overall system setup for the EVM. A PC runs software that communicates with
the USB2ANY platform, which generates the optional IOVDD or AVDD power and digital signals used to
communicate with the EVM board. Test point connections are included on the EVM board for external
power supplies. Figure 1 displays the DAC8742HEVM system setup.
Figure 1. DAC8742HEVM Hardware Setup
2.1 DAC8742H Hardware Theory of Operation
A block diagram of the DAC8742HEVM PCB board is displayed in Figure 2. The EVM board provides an
interface to optional external supplies, an external reference, and a USB2ANY connection for serial
peripheral interface (SPI) and universal asynchronous receiver and transmitter (UART) communication.
Figure 2. DAC8742H Test Board Block Diagram

www.ti.com DAC8742HEVM Hardware Setup
5
SLAU700A–June 2017–Revised November 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
DAC8742H Evaluation Module
2.2 USB2ANY Signal Definition
The DAC8742HEVM provides a hardware connector (J2) that connects to the USB2ANY interface board,
which can supply IOVDD and AVDD power and is responsible for providing the SPI or UART commands
sent from the PC GUI software. Optionally, provide the AVDD and IOVDD supply through an external
supply, and access all digital communication lines through their respective digital test points. This
information is provided in Table 3.
Table 3. J2 USB2ANY and Digital Signal Definition
Pin On J2 Signal Description
2 COM_SELECT Select between SPI or UART
4, 6, 8, 16, 27, 28 GND CS | general purpose I/O
12 CS_GPIO6 SPI, CS, or general purpose I/O
13 RXD_MISO UART RXD or SPI MISO
14 TXD_MOSI UART TXD or SPI MOSI
15 USB 3.3V 3.3-V USB power
18 SCLK_GPIO2 SPI SCLK or general purpose I/O
25 REF_EN DAC8742H reference enable
26 IF_SEL DAC8742H IF_SEL pin
29 BPF_EN General purpose I/O
30 RST DAC8742H rest Line

DAC8742HEVM Software Setup www.ti.com
6SLAU700A–June 2017–Revised November 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
DAC8742H Evaluation Module
3 DAC8742HEVM Software Setup
This section provides the procedures for software installation.
3.1 Operating Systems for DAC8742HEVM Software
The EVM software has been tested on the Microsoft®Windows®XP and Windows 7 operating systems
with the United States and European regional settings. The software should also be compatible with other
Windows operating systems.
3.2 DAC8742H Software Installation
The software is available through the EVM product folder on the TI website. Once the software is
downloaded onto the PC, navigate to the DAC8742HEVM folder, and run the setup.exe file, as shown in
Figure 3. When the software is launched, an installation dialog will open, and prompt the user to select an
installation directory. If left unchanged, the software location defaults to C:\Program Files (x86)
\DAC8742HEVM.
Figure 3. Launching Software Setup
The software installation will automatically copy the required LabVIEW™ software files and drivers to the
local machine.
NOTE: Verify that the USB2ANY is not connected before the software installation, as this may affect
file or driver installation.

www.ti.com DAC8742HEVM Hardware Overview
7
SLAU700A–June 2017–Revised November 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
DAC8742H Evaluation Module
4 DAC8742HEVM Hardware Overview
The subsequent sections provide detailed information on the EVM hardware, and jumper configuration
settings. Table 4 displays the default configurations of all jumper connections on the DAC8742HEVM.
Connect the USB extender cable from the USB2ANY to the PC.
Table 4. Default Jumper Settings
Jumper Position Description
JP1 Shunt on 1 – 2 HART: Connects to 3.6864-MHz external crystal
JP2 Shunt on 1 – 2 HART: Connects to 3.6864-MHz external crystal
JP4 Shunt on 2 – 3 Connects TS5N412PW device
JP5 Populate HART: Connects IOVDD to AVDD for single supply
operation
JP6 Shunt on 1 – 2 Connects IOVDD to USB2ANY 3.3-V supply
JP8 Populate HART: Connects to 0.022-µF load capacitor
JP9 Shunt on 2 – 3 HART: Connects to MOD_IN
JP10 Shunt on 2 – 3 HART: Connects to 2200 pF
JP11 Shunt on 1 – 2 HART: Connects to 2200 pF
JP14 Shunt on 2 – 3 CLK_CFG1 set to GND
JP16 Shunt on 5 – 6 HART: Connects to 680 pF
JP17 Populate CLK_CFG0 set to GND
JP20 Shunt on 1 – 2 /XEN set to GND
4.1 Electrostatic Discharge Warning
Many of the components on the DAC8742HEVM are susceptible to damage by electrostatic discharge
(ESD). Customers are advised to observe proper ESD handling precautions when unpacking and handling
the board, including the use of a grounded wrist strap at an approved ESD workstation.
4.2 Connecting the Hardware
To connect the USB2ANY to the EVM board, align and firmly connect the keyed ribbon connector to the
J2 connector. Verify the connection is snug, as loose connections may cause intermittent operation.
4.3 DAC8742HEVM Power Configurations
The DAC8742HEVM provides electrical connections to the device supply pins. The connectors and
optional configurations are shown in the Table 5.
Table 5. DAC8742HEVM Power Supply Configuration
Connector Connection Type Description
J3 AVDD terminal block Connects external supply to AVDD net
J4 IOVDD terminal block Connects external supply to IOVDD net
JP5 Shunt connection Connects AVDD to IOVDD
JP6 Shunt (1 – 2) Connects USB2ANY 3.3 V to IOVDD
Shunt (2 – 3) Connects IOVDD net to J4 terminal block
USB2ANY can supply IOVDD and AVDD by populating the JP6 shunt to position (1 – 2) and connecting
shunt J5.

DAC8742HEVM Hardware Overview www.ti.com
8SLAU700A–June 2017–Revised November 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
DAC8742H Evaluation Module
4.4 DAC8742H Reference Connection
The DAC8742HEVM connects to an optional external reference through the J5 terminal block, or it can be
supplied by the internal reference of the DAC8742H device (see Table 6).
Table 6. DAC8742HEVM Reference Connection
Connector Connection Type Description
J5 REF Terminal Block Connects external reference to REF net
JP7 Populate Connects external reference to REF net
4.5 Digital Inputs
The digital communication lines of the DAC8742H device can be accessed through the USB2ANY header
connection (J2) or the J6 header block, which are listed in Table 7 and Table 8, along with the digital input
signals of the DAC8742H device.
Table 7. Digital Signal Definition
Name Connector Description
JP13 IF_SEL (1 – 2) IOVDD: SPI mode
(2 – 3) GND: UART mode
JP15, JP17 CLK_CFG0 (JP15 – closed, JP17 – open): CLK_CFG0 set to IOVDD (JP15 – open, JP17 – closed): CLK_CFG0 set to GND
(JP15 – closed, JP17 – closed): CLK_CFG0 set to (0.5) IOVDD
JP14 CLK_CFG1 (1 – 2) CLK_CFG1 set to IOVDD
(2 – 3) CLK_CFG1 set to GND
JP20 /XEN (1 – 2) GND: external crystal
(2 – 3) IOVDD: external oscillator or internal oscillator required
JP19 REF_EN (1 – 2) GND: external reference
(2 – 3) IOVDD: internal reference
JP18 BPF_EN (1 – 2) GND: external bandpass required
(2 – 3) IOVDD: internal bandpass filter
Table 8. J6 Digital Signal Definition
Name Connector
J6-1 UART_OUT/SDO
J6-2 DUPLEX/SDI
J6-3 /UART_RTS/SCLK
J6-4 UART_IN/CS
J6-5 CD/IRQ
J6-6 /RST
J6-7 IOVDD
J6-8 GND
NOTE: Control the REF_EN, BPF_EN, and IF_SEL lines through the GUI.
The DAC8742H data sheet lists acceptable clock configurations, and they are also listed in Table 9 for
reference.

www.ti.com DAC8742HEVM Hardware Overview
9
SLAU700A–June 2017–Revised November 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
DAC8742H Evaluation Module
4.6 Clock Configuration
The DAC8742H device supports a variety of clocking options in order to provide system flexibility and
reduce overall current consumption in HART applications. The clocking options include: an internal
oscillator (HART mode only), an external crystal oscillator, or an external CMOS clock.
Configure clock selection via the XEN, CLK_CFG1, and CLK_CFG0 pins (see Table 9).
Table 9. Clock Configuration
XEN CLK_CFG1 CLK_CFG0 CLKO Description Mode
1 0 0 No output 3.6864-MHz CMOS clock connected at XTAL1
HART
1 0 1 No output 1.2288-MHz CMOS clock connected at XTAL1
1 1 0 No output Internal oscillator enabled
1 1 1 1.2288-MHz output Internal oscillator enabled, CLKO enabled
0 0 0 No output Crystal oscillator enabled
0 0 1 3.6864-MHz output 3.6864-MHz crystal oscillator, CLKO enabled
0 1 0 1.8432-MHz output 1.8432-MHz crystal oscillator, CLKO enabled
0 1 1 1.2288-MHz output 1.2288-MHz crystal oscillator, CLKO enabled
1 0 0.5 × IOVDD No output 4-MHz CMOS clock connected at XTAL1 FOUNDATION
Fieldbus and
PROFIBUS PA
1 1 0.5 × IOVDD No output 2-MHz CMOS clock connected at XTAL1
0 0 0.5 × IOVDD No output 4-MHz crystal oscillator
0 1 0.5 × IOVDD 4-MHz output 4-MHz crystal oscillator, CLKO enabled
The XTAL1 and XTAL2 pins of the DAC8742H device are also configurable through the JP1, JP2, and J1
jumpers (see Table 10).
Table 10. XTAL1 and XTAL2 Configuration Settings
Jumper Description
JP1 (1 – 2) 3.686-MHz crystal
(2 – 3) 4-MHz crystal
JP2 (1 – 2) 3686-MHz crystal
(2 – 3) 4-MHz crystal
J1 Optional CMOS clock connection

DAC8742HEVM Hardware Overview www.ti.com
10 SLAU700A–June 2017–Revised November 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
DAC8742H Evaluation Module
4.7 HART/PAFF Shunt Selection
The DAC8742HEVM includes various options in allowing the user to connect to an external filter or
external reference. Additionally, these external options can be bypassed as the DAC8742H device
includes an internal HART/PAFF filter, as well as an internal reference. The following configurations
display the jumper configurations required for external filter use or internal filter operation.
4.7.1 Internal Mode
Table 11 lists the internal mode shunt selection.
Table 11. Internal Mode Shunt Selection
Jumper Position Description
JP8 CLOSED/HART HART: Connects to 0.022-µF load capacitor
OPEN/PAFF
JP9 (1 – 2) HART/PAFF Connects MODINF to MOD_IN terminal block
J7
JP10 (1 – 2) PAFF HART: Connects to 2200 pF
(2 – 3) HART PAFF: Connects to 2700 pF
JP11 (1 – 2) HART HART: Connects to 2200 pF
(2 – 3) PAFF PAFF: Connects to 2700 pF
JP12 (1 – 2) HART/PAFF Connects MODINF to MOD_IN terminal block
J7
JP16 (5 – 6) HART HART: Connects to 680 pF
(7 – 8) PAFF PAFF: Connects to 120 pF
4.7.2 External Mode With Internal REF
Table 12 lists the external filter mode with internal REF shunt selection.
Table 12. External Filter Mode With Internal REF Shunt Selection
Jumper Position Description
JP8 CLOSED/HART HART: Connects to 0.022-µF load
capacitor
OPEN/PAFF
JP9 (1 – 2) HART Connects MODINF to MOD_IN terminal
block J7
(2 – 3) PAFF
JP12 (1 – 2) HART Connects MODINF to MOD_IN terminal
block J7
(2 – 3) PAFF
JP16 (3 – 4) HART HART: Connects to 150-k filter network
(1 – 2) PAFF PAFF: Connects to 27-k filter network

www.ti.com DAC8742HEVM Software Overview
11
SLAU700A–June 2017–Revised November 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
DAC8742H Evaluation Module
5 DAC8742HEVM Software Overview
This section discusses how to use the DAC8742HEVM software.
5.1 Starting the DAC8742HEVM Software
Once the DAC8742H EVM software is installed, the PC may have to be restarted. To launch the software,
locate the Texas Instruments folder in the All Programs menu and select the DAC8742H EVM icon.
Figure 4. DAC8742HEVM GUI Location
This section describes the features of the DAC8742H EVM software. The software, as shown in Figure 4,
provides basic control of all the registers and functions to the DAC8742H device. If the USB2ANY is
correctly connected, the STATUS displays “HARDWARE CONNECTED”. If the USB2ANY is not properly
connected or not connected at all, the STATUS displays “DEMO”. If the GUI is not displaying the
“CONNECTED” status while the USB2ANY is connected, unplug and reconnect the USB2ANY and re-
launch the GUI software.
Figure 5. DAC8742HEVM GUI – Power On

DAC8742HEVM Software Overview www.ti.com
12 SLAU700A–June 2017–Revised November 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
DAC8742H Evaluation Module
5.2 DAC8742HEVM Software Features
The DAC8742H EVM incorporates interactive functions that help configure the DAC8742H device. These
functions are built into several GUI pages, as shown in Figure 6. The Page Selection menu allows the
user to switch between the pages; each page representing a feature of the software.
Figure 6. DAC8742H EVM Software Page Selection

www.ti.com DAC8742HEVM Software Overview
13
SLAU700A–June 2017–Revised November 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
DAC8742H Evaluation Module
5.2.1 DAC8742HEVM Low Level Configuration Page
The DAC8742H EVM Register Map page (Figure 7) allows the user to access low-level communication
directly with the DAC8742H registers. Selecting a register on the Register Map list will present a
description of the values in that register as well as show information on the address, default value, size,
and current value of the register. Values are read and written to the registers by writing to the “Value” or
bit field of the GUI.
Figure 7. Low Level Configuration Page
The values of the register map can also be saved by pressing the Save Configuration button under the
File menu option. Additionally, the configuration files are accessed through the Load Configuration button.
Other options selectable by the user are the Update Mode,Write Selected (red box), Read Selected
(orange box), Write Modified (gray box) and Read All (yellow box) buttons. All buttons are displayed in
Figure 8.
Figure 8. Low Level Configuration Page Available Options
If Update Mode is selected to “Immediate”, all changes to register values update immediately, while
“Deferred” allows the user to modify the value of a register without taking effect until the Write Selected, or
Write Modified button is pressed.
The Read Selected button allows individual register reads, while the Read All button reads the status of all
registers located in the register map.

DAC8742HEVM Software Overview www.ti.com
14 SLAU700A–June 2017–Revised November 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
DAC8742H Evaluation Module
5.2.2 DAC8742HEVM High Level Configuration Page
The High Level Configuration page provides an interface to observe and control the different data
registers, modes, and configurations available for the DAC8742H device. Figure 9 displays this page.
Figure 9. High Level Configuration Page
This page is broken into three sections responsible for different modes of communication (UART/SPI), as
well as HART or PAFF mode of operation.
The first section is responsible for choosing the form of digital communication. The COMMUNICATION
MODE panel is responsible for selecting between HART and PAFF. The remaining three input controls
are only operable in SPI, but are used to modify the FIFO level set register (0x25) and TX_AMP
parameter of the MODEM CONTROL register (0x22). The FIFO levels set register is responsible for
programming the alarm thresholds for both transmit and receive FIFOs. The Hart Amplitude (TX_AMP)
input control allows the user to input an unsigned binary value that controls the amplitude (HART mode
only) of the transmitted waveform in 25-mVpp steps.

www.ti.com DAC8742HEVM Software Overview
15
SLAU700A–June 2017–Revised November 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
DAC8742H Evaluation Module
The panel to the aforementioned text is shown in Figure 10.
Figure 10. MODE Section
The second section displays the state to several digital inputs of the DAC8742HEVM device. Such digital
inputs include the /RESET, IF_SEL, REF_EN, and BPFEN pin. These buttons are shown in Figure 11,
highlighted with yellow boxes.
Figure 11. DAC8742HEVM Digital Input Selection

DAC8742HEVM Documentation www.ti.com
16 SLAU700A–June 2017–Revised November 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
DAC8742H Evaluation Module
The third and final section displays the HART or PAFF Write and Read control and indicator fields. Once
the mode is selected (shown in section 1) with the desired communication method (SPI, or UART), the
user can then input a valid HART/PAFF 8-bit hexadecimal array to write over the HART/PAFF BUS (Red
Box). The maximum amount of elements that can transfer to the internal FIFO are 15; therefore, the
number of elements input into the field should never exceed 15. Once the elements are input, press the
Generate Write button (Green box), and this shifts the contents into the FIFO and transmit for the
specified industrial protocol (HART/PAFF). Press the Generate Read button (Orange box) if you are
expecting an incoming transmission to the DAC8742H device. Once pressed, the HART/PAFF Read field
(Yellow box) will update with the captured data.
NOTE: For Read operations in UART, the user must specify the # Bytes to Read for proper
readback operation. (Purple box).
The Reinit Arrays button (gray box) clears the array fields. The FULL DUPLEX button connects TX FIFO
to RX FIFO.
Figure 12. HART/PAFF Write/Read Control and Indicator Section
6 DAC8742HEVM Documentation
This section contains the complete bill of materials and schematic diagram for the DAC8742HEVM.
Documentation information for the USB2ANY platform is found in the USB2ANY Platform User’s Guide.

XEN 2
CLKO
3
CLK_CFG0
4
CLK_CFG1
5
RST
6
CD/IRQ
7
IF_SEL
9UART_IN/CS
10
UART_RTS/SCLK
11
DUPLEX/SDI
12
UART_OUT/SDO
13
IOVDD
14
DGND 15
REG_CAP 18
MOD_OUT 19
REF 20
MOD_IN 21
MOD_INF 22
AVDD
23
AGND 26
X2 27
X1 28
DGND 29
REF_EN 30
BPF_EN 31
NC
1
NC
8
NC
16
NC
17
NC
24
NC
25
NC
32
U2
DAC8742HPBS DGND
AVDD
IOVDD
AGND
0.1µF
C14
0.1µF
C12
AGND
1µF
C22
0.1µF
C20
AGND
REF
IOVDD
1
2
3
JP13
IOVDD
/RST
1.00M
R19
1.00M
R5
1.00M
R6
1.00M
R7
1.00M
R14
TP2
TP4
UARTRTS/SCLK
DUPLEX/SDI
UARTOUT/SDO
UARTIN/CS
IF_SEL
XTAL1
XTAL2
DAC8742H
1
2
3
JP14
IOVDD
1.00M
R12
TP3
AGND
AGND AGND
AGND
1µF
C8
J3
AGND
AVDD
1µF
C6 J4
IOVDD
0.1µF
C9
0.1µF
C7
1µF
C10
J5
REF
0.1µF
C11
IOVDD
AVDD
AGND
REF
1
2
3
JP6
USB_3p3 TP1
AGND
JP5
JP7
5
4
1
2
3
6
7
8
J6
IOVDD
AGND
300pF
C16
100pF
C18
27.0k
R10
300pF
C21
150pF
C23
150k
R15
120pF
C25
680pF
C24
2700pF
C17
2200pF
C19
AGND
AGND
REF
REF
1
2
3
JP12
1
2
3
JP10
1
2
3
JP11
1 2
3 4
5 6
7 8
JP16
AGND
AGND
1
2
3
JP9
J7
AGND
TP5 TP6 TP7 TP8
1
2
3
JP18
IOVDD
1.00M
R16
BPF_EN
AGND
1
2
3
JP19
IOVDD
1.00M
R17
REF_EN
AGND
1
2
3
JP20
IOVDD
1.00M
R18
AGND
0.022µF
C15
2.2µF
C13
AGND
JP8
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15
17
19
21
23
25
27
29
16
18
20
22
24
26
28
30
J2
RXD_MISO
USB_3p3
REF_EN
BPF_EN
COM_SELECT
CS_GPIO6
TXD_MOSI
SCLK_GPIO2
IF_SEL
/RST
USB2ANY Connection
AGND AGND
1
2
3
JP3
IOVDD
Selectable COM
UARTRTS/SCLK SCLK_GPIO2
TXD_MOSI
RXD_MISO
CS_GPIO6
DUPLEX/SDI
UARTOUT/SDO
UARTIN/CS
COM_SELECT
0.1µF
C1
IOVDD
1
2
3
JP4
IOVDD 1.00k
R2
1.00k
R3
AGND
AGND
AGND
AGND
12
4 MHz
Y2
18pF
C4
1
2 3 4 5
J1
18pF
C2
18pF
C5
18pF
C3
2
1
3
JP1
2
1
3
JP2
XTAL Configuration
XTAL1
XTAL2
AGND
AGND
AGND
AGND
AGND
12
3.6864MHz
Y1
0
R1
JP15
JP17
1.00k
R11
620k
R13
536k
R9
S
1
1B1 2
1B2 3
1A
4
2B1 5
2B2 6
2A
7
3B2 10
GND 8
3A
93B1 11
4A
12
4B2 13
4B1 14
OE
15
VCC
16
U1
TS5N412PW
AGND
Mod_Out
Mod_In
CLKO
1.00M
R4
1.00M
R8
Copyright © 2017, Texas Instruments Incorporated
www.ti.com DAC8742HEVM Documentation
17
SLAU700A–June 2017–Revised November 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
DAC8742H Evaluation Module
6.1 DAC8742HEVM Board Schematic
Figure 13 illustrates the DAC8742HEVM board schematic.
Figure 13. DAC8742HEVM Board Schematic

Copyright © 2017, Texas Instruments Incorporated
DAC8742HEVM Documentation www.ti.com
18 SLAU700A–June 2017–Revised November 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
DAC8742H Evaluation Module
6.2 DAC8742HEVM PCB Components Layout
Figure 14 shows the layout of the components for the DAC8742HEVM board.
Figure 14. DAC8742HEVM PCB Components Layout

www.ti.com DAC8742HEVM Documentation
19
SLAU700A–June 2017–Revised November 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
DAC8742H Evaluation Module
6.3 DAC8742H Test Board Bill of Materials
Table 13 lists the DAC8742H BOM.
Table 13. DAC8742H Test Board Bill of Materials
Designator Quantity Value Description Package
Reference Part Number Manufacturer Alternate Part Number Alternate Manufacturer
!PCB1 1 Printed circuit board PA032 Any – –
C1, C7, C9,
C11, C12,
C14, C20
7 0.1 µF Capacitor, ceramic, 0.1 µF, 25 V,
± 10%, X7R, 0603 0603 GRM188R71E104KA01D MuRata
C2, C3, C4,
C5 4 18 pF Capacitor, ceramic, 18 pF, 50 V, ± 5%, C0G/NP0, 0603 0603 GRM1885C1H180JA01D MuRata
C6, C8, C10,
C22 4 1 µF Capacitor, ceramic, 1 µF, 25 V, ± 10%, X7R, AEC-Q200 Grade 1,
0603
0603 GCM188R71E105KA64D MuRata
C13 1 2.2 µF Capacitor, ceramic, 2.2 µF, 10 V,
± 10%, X7R, 0603 0603 GRM188R71A225KE15D MuRata
C15 1 0.022 µF Capacitor, ceramic, 0.022 µF, 50
V, ± 10%, X7R, 0603 0603 GRM188R71H223KA01D MuRata
C16, C21 2 300 pF Capacitor, ceramic, 300 pF, 50 V,
± 5%, C0G/NP0, 0603 0603 GRM1885C1H301JA01D MuRata
C17 1 2700 pF Capacitor, ceramic, 2700 pF, 50
V, ± 5%, C0G/NP0, 0603 0603 GRM1885C1H272JA01D MuRata
C18 1 100 pF Capacitor, ceramic, 100 pF, 50 V,
± 5%, C0G/NP0, 0603 0603 GRM1885C1H101JA01D MuRata
C19 1 2200 pF Capacitor, ceramic, 2200 pF, 50
V, ± 5%, C0G/NP0, 0603 0603 GRM1885C1H222JA01D MuRata
C23 1 150 pF Capacitor, ceramic, 150 pF, 50 V,
± 5%, C0G/NP0, 0603 0603 GRM1885C1H151JA01D MuRata
C24 1 680 pF Capacitor, ceramic, 680 pF, 50 V,
± 5%, C0G/NP0, 0603 0603 C0603C681J5GACTU Kemet
C25 1 120 pF Capacitor, ceramic, 120 pF, 50 V,
± 5%, C0G/NP0, 0603 0603 GRM1885C1H121JA01D MuRata
H1, H2, H3,
H4 4 Bumpon, Hemisphere, 0.44 × 0.20, clear Transparent Bumpon SJ-5303 (clear) 3M
J1 1 Connector, TH, SMA SMA 142-0701-201 Emerson
Network Power
J2 1 Header (shrouded), 2.54 mm, 15 ×
2, gold, TH Header (shrouded), 2.54
mm, 15 × 2, TH
302-S301 On-Shore
Technology
J3, J4, J5, J7 4 Terminal Block, 6 A, 3.5 mm Pitch,
2-position, TH 7.0 × 8.2 × 6.5 mm ED555/2DS On-Shore Technology

DAC8742HEVM Documentation www.ti.com
20 SLAU700A–June 2017–Revised November 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
DAC8742H Evaluation Module
Table 13. DAC8742H Test Board Bill of Materials (continued)
Designator Quantity Value Description Package
Reference Part Number Manufacturer Alternate Part Number Alternate Manufacturer
J6 1 Header, 100 mil, 8 × 1, gold, TH 8 × 1 header TSW-108-07-G-S Samtec
JP1, JP2,
JP3, JP4,
JP6, JP9,
JP10, JP11,
JP12, JP13,
JP14, JP18,
JP19, JP20
14 Header, 100 mil, 3 × 1, gold, TH 3 × 1 header TSW-103-07-G-S Samtec
JP5, JP7,
JP8, JP15,
JP17
5 Header, 100 mil, 2 × 1, gold, TH 2 × 1 header TSW-102-07-G-S Samtec
JP16 1 Header, 100 mil, 4 × 2, gold, TH 4 × 2 header TSW-104-07-G-D Samtec
R1 1 0 RES, 0, 5%, 0.1 W, 0603 0603 CRCW06030000Z0EA Vishay-Dale
R2, R3, R11 3 1.00 k RES, 1.00 k, 1%, 0.1 W, 0603 0603 CRCW06031K00FKEA Vishay-Dale
R4, R5, R6,
R7, R8, R12,
R14, R16,
R17, R18,
R19
11 1.00 Meg RES, 1.00 M, 1%, 0.1 W, 0603 0603 RC0603FR-071ML Yageo America
R9 1 536 k RES, 536 k, 1%, 0.1 W, 0603 0603 RC0603FR-07536KL Yageo America
R10 1 27.0 k RES, 27.0 k, 1%, 0.1 W, 0603 0603 RC0603FR-0727KL Yageo America
R13 1 620 k RES, 620 k, 1%, 0.1 W, 0603 0603 RC0603FR-07620KL Yageo America
R15 1 150 k RES, 150 k, 1%, 0.1 W, 0603 0603 CRCW0603150KFKEA Vishay-Dale
SH-J1, SH-
J2, SH-J3,
SH-J4, SH-
J5, SH-J6,
SH-J7, SH-
J8, SH-J9,
SH-J10, SH-
J11, SH-J12,
SH-J13, SH-
J14, SH-J15,
SH-J16, SH-
J17, SH-J18,
SH-J19, SH-
J20
20 1 × 2 Shunt, 100 mil, gold-plated, black Shunt 969102-0000-DA 3M SNT-100-BK-G Samtec
TP1 1 Test point, multipurpose, yellow,
TH Yellow multipurpose test
point
5014 Keystone
TP2, TP3,
TP4 3 Test point, multipurpose, red, TH Red multipurpose test point 5010 Keystone