Texas Instruments LMX9838 User manual

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LMX9838
SNOSAZ9F –JULY 2007–REVISED DECEMBER 2014
LMX9838 Bluetooth Serial Port Module
1 Features 3 Description
The Texas Instruments LMX9838 Bluetooth Serial
1• Complete Bluetooth®2.0 Stack Including Port module is a fully integrated Bluetooth 2.0
– Baseband and Link Manager baseband controller, 2.4 GHz radio, crystal, antenna,
– Protocols: L2CAP, RFCOMM, SDP LDO and discreets; combined to form a complete
small form factor (10 mm x 17 mm x 2.0 mm)
– Profiles: GAP, SDAP, SPP Bluetooth node.
• High Integration: Includes Processor, Antenna, All hardware and firmware is included to provide a
Crystal, EEPROM, LDO complete solution from antenna through the complete
• Supporting up to 7 Active Bluetooth Data Links lower and upper layers of the Bluetooth stack, up to
and 1 Active SCO Link the application including the Generic Access Profile
• Class 2 Operation (GAP), the Service Discovery Application Profile
(SDAP), and the Serial Port Profile (SPP). The
• UART Command/Data Port Speed 921.6kbits/s module includes a configurable service database to
• AAI for External PCM Codec fulfil service requests for additional profiles on the
• Better than -80dBm Input Sensitivity host. Moreover, the LMX9838 is qualified as a
• FCC, IC, CE, and Japan MIC Certified Bluetooth endproduct, ready to be used in the end
application without additional testing and license cost.
• Bluetooth SIG QD ID: B012394
• Compact Size: 10 mm x 17 mm x 2.0 mm Based on TI’s CompactRISC 16-bit processor
architecture and Digital Smart Radio technology, the
LMX9838 is optimized to handle the data and link
2 Applications management processing requirements of a Bluetooth
• Factory Automation and Control node.
• Test and Measurement Device Information(1)
• Telematics PART NUMBER PACKAGE BODY SIZE (NOM)
• POS Terminals LMX9838 PLGA (70) 17.00 mm × 10.00 mm
• Medical/Telemedicine (1) For all available packages, see the orderable addendum at
• Data Logging Systems the end of the data sheet.
• Audio Gateways
4 Block Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMX9838
SNOSAZ9F –JULY 2007–REVISED DECEMBER 2014 www.ti.com
Table of Contents
8.3 Feature Description................................................... 9
1 Features.................................................................. 18.4 Device Functional Modes........................................ 17
2 Applications ........................................................... 18.5 Programming - Command Interface........................ 21
3 Description............................................................. 19 Application and Implementation ........................ 26
4 Block Diagram........................................................ 19.1 Typical Applications ............................................... 26
5 Revision History..................................................... 210 Power Supply Recommendations ..................... 31
6 Pin Configuration and Functions......................... 310.1 Power Supply Schematics ................................... 31
7 Specifications......................................................... 510.2 Filtered Power Supply........................................... 33
7.1 Absolute Maximum Ratings ...................................... 510.3 Power Up .............................................................. 33
7.2 Handling Ratings ...................................................... 511 Regulatory Compliance...................................... 35
7.3 Recommended Operating Conditions....................... 511.1 FCC Instructions ................................................... 35
7.4 Thermal Information.................................................. 512 Device and Documentation Support ................. 38
7.5 Power Supply Requirements .................................... 612.1 Device Support .................................................... 38
7.6 Digital DC Characteristics ........................................ 612.2 Documentation Support ....................................... 38
7.7 RF Receiver Performance Characteristics................ 712.3 Trademarks........................................................... 38
7.8 RF Transmitter Performance Characteristics............ 712.4 Electrostatic Discharge Caution............................ 38
7.9 RF Synthesizer Performance Characteristics........... 812.5 Glossary................................................................ 38
8 Detailed Description.............................................. 913 Mechanical, Packaging, and Orderable
8.1 Overview................................................................... 9Information........................................................... 38
8.2 Functional Block Diagram......................................... 9
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (January 2014) to Revision F Page
• Added Handling Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1
• Changed EN 301 489-17 v1.2.1 to EN 301 489-17 v2.2.1................................................................................................... 35
Changes from Revision D (April 2013) to Revision E Page
• Added two parameters for operating conditions..................................................................................................................... 5
• Changed schematic.............................................................................................................................................................. 28
Changes from Revision C (April 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 36
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6 Pin Configuration and Functions
PLGA NAW0070A Package
70 Pins
Top View
Pin Functions
PAD NAME PAD LOCATION I/O DEFAULT LAYOUT DESCRIPTION
SYSTEM INTERFACE SIGNALS
OP3 16 I OP3: Pin checked during Startup Sequence for configuration option
OP4: I OP4: Pin checked during Startup Sequence for configuration option
OP4/PG4 26 PG4: I/O PG4: GPIO
OP5 25 I/O OP5: Pin checked during Startup Sequence for configuration option
32K- 28 O NC (if not used) 32.768 kHz Crystal Oscillator
32K+ 27 I GND (if not used) 32.768 kHz Crystal Oscillator
UART Interface Signals
CTS#(1) 15 I GND (if not used) Host Serial Port Clear To Send (active low)
RTS#(2) 14 O NC (if not used) Host Serial Port Request To Send (active low)
RXD 12 I Host Serial Port Receive Data
TXD 13 O Host Serial Port Transmit Data
AUXILIARY PORTS INTERFACE SIGNALS
PG6 7 I/O GPIO - Default setup LINK STATUS indication
PG7 19 I/O GPIO - Default setup RF traffic LED indication
Low active, either
RESET# 2 I NC or connect to Module Reset (active low)
host
XOSCEN 8 O Host main Clock Request. Toggles with Main crystal (X1) enable/disable
AUDIO INTERFACE SIGNALS
SCLK 20 I/O Audio PCM Interface Clock
SFS 21 I/O Audio PCM Interface Frame Synchronization
SRD 23 I Audio PCM Interface Receive Data Input
STD 22 O Audio PCM Interface Transmit Data Output
(1) Connect to GND if CTS is not use.
(2) Treat As No Connect If RTS is not used. Pad required for mechanical stability.
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Pin Functions (continued)
PAD NAME PAD LOCATION I/O DEFAULT LAYOUT DESCRIPTION
POWER, GROUND AND NO CONNECT SIGNALS
3, 4, 17, 18, 24,
GND I GND Must be connected to ground plane
29, 30, 31, 32
MVCC 6 I Module internal Voltage Regulator Input
1, 5, 33, 34, 35,
NC NC Place Pads for stability.
36, 37, 38, 39, 40
41, 42, 43, 44,
45, 46, 47, 48,
49, 50, 51, 52,
53, 54, 55, 56,
NC NC DO NOT PLACE ANY PADS.
57, 58, 59, 60,
61, 62, 63, 64,
65, 66, 67, 68,
69, 70
VCC_CORE 9 I/O Voltage Regulator Input/Output
VCC 10 I Voltage Regulator Input Baseband
VCC_IO 11 I Power Supply I/O
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7 Specifications
7.1 Absolute Maximum Ratings(1)
The following conditions are true unless otherwise stated in the tables: TA= –40°C to +85°C. VCC = 3.3 V. RF system
performance specifications are ensured on Texas Instruments Flagstaff board rev 2.1 evaluation platform.
MIN MAX UNIT
VCC Digital Voltage Regulator input -0.2 4 V
VIVoltage on any pad with GND = 0 V -0.2 VCC + 0.2 V
Lead Temperature NOPB(2)(3)
TLNOPB 250 °C
(solder 40 sec.)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional. This device is a high performance RF integrated circuit and is ESD sensitive. Handling and
assembly of this device should be performed at ESD free workstations.
(2) Reference IPC/JDEC J-STD-20C spec.
(3) NOPB = No Pb (No Lead).
7.2 Handling Ratings MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all 2000
pins(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification 1000
JESD22-C101, all pins(2)
ESDMM ESD - Machine Model 200(3) V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) All pins meet 200V Macine Model ESD rating except pins RXD, TXD, CTS, RTS, PG4, OP5, PG6, PG7, SCL, SDA, MDOD1, MWCS,
SFS, STD, SRD RATED AT 150v.
7.3 Recommended Operating Conditions MIN NOM MAX UNIT
MVCC Module internal Voltage Regulator input 3.0 3.3 3.6 V
VCC Digital Voltage Regulator input 2.5 3.3 3.6 V
TRDigital Voltage Regulator Rise Time 10 μs
Ambient Operating Temperature Range
TA-40 +25 +85 °C
Fully Functional Bluetooth Node
VCC_IO(1) Supply Voltage Digital I/O 1.8 3.3 3.6 V
VCC_CORE Supply Voltage Output(2) 1.8 V
VCC_COREMAX Supply Voltage Output Max Load 5 mA
VCC_CORESHORT When used as Supply Input (VCC grounded) 1.6 1.8 2 V
(1) VCC must be > (VCC_IO - 0.5V) to avoid backdrive supply.
(2) Should not be used for external supplies
7.4 Thermal Information LMX9838
THERMAL METRIC(1) NAW UNIT
70 PINS
RθJA Junction-to-ambient thermal resistance 45 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Power Supply Requirements(1)(2)
PARAMETER MIN TYP(3) MAX UNIT
ICC-TX Power supply current for continuous transmit 65 mA
ICC-RX Power supply current for continuous receive 65 mA
IRXSL Receive Data in SPP Link, Slave 26 mA
IRXM Receive Data in SPP Link, Master 23 mA
ISnM Sniff Mode, Sniff interval 1 second 6.5 mA
ISC-TLDIS Scanning, No Active Link, TL Disabled 1.1 mA
(1) Power supply requirements based on Class II output power.
(2) Based on UART Baudrate 115.2kbit/s.
(3) VCC = 3.3 V, Ambient Temperature = +25 °C.
7.6 Digital DC Characteristics
PARAMETER TEST CONDITIONS MIN MAX UNIT
Logical 1 Input Voltage high 1.8 V ≤VCC_IO ≤3.0 V 0.7 x VCC_IO VCC_IO + 0.2
VIH V
(except oscillator I/O) 3.0 V ≤VCC_IO ≤3.6 V 2.0 VCC_IO + 0.2
Logical 0 Input Voltage low 1.8 V ≤VCC_IO ≤3.0 V -0.2 0.25 x VCC_IO
VIL V
(except oscillator I/O) 3.0 V ≤VCC_IO ≤3.6 V -0.2 0.8
Logical 1 Output Voltage high VCC_IO = 1.8 V 0.7 x VCC_IO
VOH V
(except oscillator I/O) VCC_IO = 3.0 V 2.4
Logical 0 Output Voltage low
VOL 0.4 V
(except oscillator I/O)
VHYS Hysteresis Loop Width(1) 0.1 x VCC V
IIH Logical 1 Input leakage High 10 µA
IIL Logical 0 Input leakage Low -10 µA
IOH Logical 1 Output Current VOH = 2.4 V, VCC_IO = 3.0 V -10 mA
IOL Logical 0 Output Current VOH = 0.4 V, VCC_IO = 3.0 V 10 mA
(1) Specified by design.
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7.7 RF Receiver Performance Characteristics
All tests performed are based on Bluetooth Test Specification revision 2.0. All tests are measured at antenna port unless
otherwise specified. TA= –40°C to +85°C--VDD_RF = 2.8 V unless otherwise specified. RF system performance specifications
are ensured on Texas Instruments Flagstaff board rev 2.1 evaluation platform. All RF parameters are tested prior to the
antenna. PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
2.402 GHz -80 -76 dBm
RXsense Receive Sensitivity BER < 0.001 2.441 GHz -80 -76 dBm
2.480 GHz -80 -76 dBm
PinRF Maximum Input Level -10 0 dBm
F1= + 3 MHz,
IMP(2) Intermodulation Performance F2= + 6 MHz, -38 -36 dBm
PinRF = -64 dBm
RSSI Dynamic Range at LNA
RSSI -72 -52 dBm
Input PinRF = -10 dBm,
30 MHz < FCWI < 2 GHz, -10 dBm
BER < 0.001
PinRF = -27 dBm,
2000 MHz < FCWI < 2399 MHz, -27 dBm
BER < 0.001
Out Of Band Blocking
OOB(2) Performance PinRF = -27 dBm,
2498 MHz < FCWI < 3000 MHz, -27 dBm
BER < 0.001
PinRF = -10 dBm,
3000 MHz < FCWI < 12.75 GHz, -10 dBm
BER < 0.001
(1) Typical operating conditions are at 2.75V operating voltage and 25°C ambient temperature.
(2) The f0= -64 dBm Bluetooth modulated signal, f1= -39dbm sine wave, f2= -39 dBm Bluetooth modulated signal, f0= 2f1- f2, and |f2- f1|
= n * 1MHz, where n is 3, 4, or 5. For the typical case, n = 3.
7.8 RF Transmitter Performance Characteristics
All tests performed are based on Bluetooth Test Specification revision 2.0. All tests are measured at antenna port unless
otherwise specified. TA= -40°C to +85°C--VDD_RF = 2.8V unless otherwise specified. RF system performance specifications
are ensured on Texas Instruments Flagstaff board rev 2.1 evaluation platform. All RF parameters are tested prior to the
antenna. PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
2.402 GHz −4 0 +3 dBm
POUTRF Transmit Output Power 2.441 GHz −4 0 +3 dBm
2.480 GHz −4 0 +3 dBm
MOD ΔF1AVG Modulation Characteristics Data = 00001111 140 165 175 kHz
MOD ΔF2MAX(2) Modulation Characteristics Data = 10101010 115 125 kHz
ΔF2AVG/DF1AVG(3) Modulation Characteristics 0.8
20 dB Bandwidth 1000 kHz
Maximum gain setting:
POUT2*fo(4) PA 2nd Harmonic Suppression f0= 2402 MHz, -30 dBm
Pout = 4804 MHz
RF Output Impedance/Input
ZRFOUT(5) Pout @ 2.5 GHz 47 Ω
Impedance of RF Port (RF_inout)
(1) Typical operating conditions are at 2.75V operating voltage and 25°C ambient temperature.
(2) ΔF2max ≥115 kHz for at least 99.9% of all Δf2max.
(3) Modulation index set between 0.28 and 0.35.
(4) Out-of-Band spurs only exist at 2nd and 3rd harmonics of the CW frequency for each channel.
(5) Not tested in production.
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7.9 RF Synthesizer Performance Characteristics
All tests performed are based on Bluetooth Test Specification revision 2.0. All tests are measured at antenna port unless
otherwise specified. TA= -40°C to +85°C. VDD_RF = 2.8V unless otherwise specified. RF system performance specifications
are ensured on Texas Instruments Flagstaff board rev 2.1 evaluation platform. All RF parameters are tested prior to the
antenna. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fVCO VCO Frequency Range 2402 2480 MHz
tLOCK Lock Time f0± 20 kHz 120 µs
Initial Carrier Frequency
Δf0offset(1) During preamble -75 0 75 kHz
Tolerance DH1 data packet -25 0 25 kHz
DH3 data packet -40 0 40 kHz
Δf0drift(1) Initial Carrier Frequency Drift DH5 data packet -40 0 40 kHz
Drift Rate -20 0 20 kHz/50µs
tD- Tx Transmitter Delay Time From Tx data to antenna 4 µs
(1) Frequency accuracy is dependent on crystal oscillator chosen. The crystal must have a cumulative accuracy of < ±20ppm to meet
Bluetooth specifications.
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GPIO
UART
POR
LFO
32 kHz
Config
Options
Audio
Port
CVSD
Codecs
Combined
System and
Patch RAM
ROM
EPROM
Voltage
Regulator
XTAL
Compact RISC
Processor
BLUEtoothTM
Core
2.4 GHz
Radio
Antenna Link
Manager UART
Transport
PG6
PG7
TXD
RXD
RTS#
CTS#
RESET#
OP3
OP4/PG4
OP5
SCLK
SF
STD
SRD
32k+
32k-
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8 Detailed Description
8.1 Overview
LMX9838 is a fully certified Bluetooth 2.0 module, with integrated processor, radio, antenna, LDO, crystal, and
passive components to form a small form factor plug-n-play solution. The built-in Bluetooth stacks up to the
application layer allows users to communicate directly with SPP commands, and develop additional SPP-based
Bluetooth profiles on Host through UART interface.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Features Overview
The firmware supplied in the on-chip ROM memory offers a complete Bluetooth (v2.0) stack including profiles
and command interface. This firmware features point-to-point and point-to-multipoint link management supporting
data rates up to the theoretical maximum over RFComm of 704 kbps. The internal memory supports up to 7
active Bluetooth data links and one active SCO link.
The on-chip Patch RAM provided for lowest cost and risk, allows the flexibility of firmware upgrade.
The module is lead free and RoHS (Restriction of Hazardous Substances) compliant.
For more information on those quality standards, please visit our green compliance website at
http://focus.ti.com/quality/docs/qualityhome.tsp.
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Feature Description (continued)
8.3.2 Hardware
• Baseband and Link Management Processors based on TI's CompactRISC Core
• Embedded ROM and Patch RAM Memory
• Auxiliary Host Interface Ports:
– Link Status
– Transceiver Status (Tx or Rx)
• Advanced Power Management (APM) Features
• Supports Low-Power Mode with Optional 32.768 kHz Oscillator
• Full Radio Path Integrated Including Antenna
• On-Chip Reference Crystal for Bluetooth Operation
• Single Supply Voltage
8.3.3 Firmware
• Additional Profile Support on Host. e.g:
– Dial Up Networking (DUN)
– Facsimile Profile (FAX)
– File Transfer Protocol (FTP)
– Object Push Profile (OPP)
– Synchronization Profile (SYNC)
– Headset (HSP)
– Handsfree Profile (HFP)
– Basic Imaging Profile (BIP)
– Basic Printing Profile (BPP)
• On-Chip Application Including:
– Default Connections
– Command Interface:
– Link Setup and Configuration (also Multipoint)
– Configuration of the Module
– Service Database Modifications
– UART Transparent Mode
– Optimized Cable Replacement:
– Automatic Transparent Mode
– Event Filter
8.3.4 Compliance
• FCC compliance: The device complies with Part 15 of FCC Rules. Operation is subject to the following two
conditions:
– This device may not cause harmful interference
– This device must accept any interference received, including interference that may cause undesired
operation
• Compliant with IC for Canada, CE for Europe, and MIC for Japan. See Regulatory Compliance.
8.3.5 Package
• Complete system interface provided in Lead Grid Array on underside for surface mount assembly
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Feature Description (continued)
8.3.6 Baseband and Link Management Processors
Baseband and Lower Link control functions are implemented using a combination of Texas Instruments'
CompactRISC 16-bit processor and the Bluetooth Lower Link Controller. These processors operate from
integrated ROM memory and RAM and execute on-board firmware implementing all Bluetooth functions.
8.3.7 Bluetooth Lower Link Controller
The integrated Bluetooth Lower Link Controller (LLC) complies with the Bluetooth Specification version 2.0 and
implements the following functions:
• Adaptive Frequency Hopping
• Interlaced Scanning
• Fast Connect
• Support for 1, 3, and 5 slot packet types
• 79 Channel hop frequency generation circuitry
• Fast frequency hopping at 1600 hops per second
• Power management control
• Access code correlation and slot timing recovery
8.3.8 Bluetooth Upper Layer Stack
The integrated upper layer stack is prequalified and includes the following protocol layers:
• L2CAP
• RFComm
• SDP
8.3.9 Profile Support
The on-chip application of the LMX9838 allows full stand-alone operation, without any Bluetooth protocol layer
necessary outside the module. It supports the Generic Access Profile (GAP), the Service Discovery Application
Profile (SDAP), and the Serial Port Profile (SPP).
The on-chip profiles can be used as interfaces to additional profiles executed on the host. The LMX9838 includes
a configurable service database to answer requests with the profiles supported.
8.3.10 Application With Command Interface
The module supports automatic slave operation eliminating the need for an external control unit. The
implemented transparent option enables the chip to handle incoming data raw, without the need for packaging in
a special format. The device uses a pin to block unallowed connections. This pincode can be fixed or
dynamically set.
Acting as master, the application offers a simple but versatile command interface for standard Bluetooth
operation like inquiry, service discovery, or serial port connection. The firmware supports up to seven slaves.
Default Link Policy settings and a specific master mode allow optimized configuration for the application specific
requirements. See the Integrated Firmware section.
8.3.11 Memory
The LMX9838 introduces 16 kB of combined system and Patch RAM memory that can be used for data and/or
code upgrades of the ROM based firmware. Due to the flexible startup used for the LMX9838 operating
parameters like the Bluetooth Device Address (BD_ADDR) are defined during boot time. This allows reading out
the parameters of an internal EEPROM or programming them directly over UART.
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Feature Description (continued)
8.3.12 Transport Port - UART
The LMX9838 provides one Universal Asynchronous Receiver Transmitter (UART). The UART interface consists
out of Receive (RX), Transmit (TX), Ready-to-Send (RTS) and Clear-to-Send signals. RTS and CTS are used for
hardware handshaking between the host and the LMX9838. Since the LMX9838 acts as gateway between the
bluetooth and the UART interface, Texas Instruments recommends to use the handshaking signals especially for
transparent operation. In case two signals are used CTS needs to be pulled to GND. Refer to LMX9838 Software
User’s Guide, literature number SNOA498 for detailed information on 2-wire operation.
The UART interface supports formats of 8-bit data with or without parity, with one or two stop bits. It can operate
at standard baud rates from 2400bits/s up to a maximum baud rate of 921.6kbits/s. DMA transfers are supported
to allow for fast processor independent receive and transmit operation.
The UART baudrate is configured during startup by checking option pins OP3, OP4 and OP5. Table 2 gives the
correspondence between the OP pins settings and the UART speed.
The UART offers wakeup from the power save modes via the multi-input wakeup module. When the LMX9838 is
in low power mode, RTS# and CTS# can function as Host_WakeUp and Bluetooth_WakeUp respectively.
Table 1 represents the operational modes supported by the firmware for implementing the transport via the
UART.
Table 1. UART Operation Modes
ITEM RANGE DEFAULT at POWER-UP
Baud Rate 2.4 to 921.6 kbits/s Either configured by option pins, NVS
Flow Control RTS#/CTS# or None RTS#/CTS#
Parity Odd, Even, None None
Stop Bits 1,2 1
Data Bits 8 8
OP3, OP4, OP5 can be strapped to the host logic 0 and 1 levels to set the host interface boot-up configuration.
Alternatively all OP3, OP4, OP5 can be hardwired over 1k Ohm pullup/pulldown resistors. See Table 2.
Table 2. UART Frequency Settings
OP3(1) OP4(2) OP5(3) FUNCTION
1 0 0 UART speed read from NVS
1 0 1 UART speed 9.6 kbps
1 1 0 UART speed 115.2 kbps
1 1 1 UART speed 921.6 kbps
(1) If OP3 is 1, must use 1K pull up
(2) If OP4 is 1, must use 1K pull up
(3) If OP5 is 1, must use 1K pull up
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8.3.13 Audio Port
8.3.13.1 Advanced Audio Interface
The Advanced Audio Interface (AAI) is an advanced version of the Synchronous Serial Interface (SSI) that
provides a full-duplex communications port to a variety of industry-standard 13/14/15/16-bit linear or 8-bit log
PCM codecs, DSPs, and other serial audio devices.
The interface allows the support one codec or interface. The firmware selects the desired audio path and
interface configuration by a parameter that is located in RAM (imported from non-volatile storage or programmed
during boot-up). The audio path options include the OKI MSM7717 codec, the Winbond W681360/W681310
codecs and the PCM slave through the AAI.
In case an external codec or DSP is used the LMX9838 audio interface generates the necessary bit and frame
clock driving the interface.
Table 3 summarizes the audio path selection and the configuration of the audio interface at the specific modes.
The LMX9838 supports one SCO link.
Table 3. Audio Path Configuration
AAI FRAME AAI FRAME SYNC
AUDIO SETTING INTERFACE FORMAT AAI BIT CLOCK CLOCK PULSE LENGTH
OKI MSM7717 8-bit log PCM
Advanced audio interface 520 kHz 8 kHz 14 Bits
(a-law only)
Winbond W681310 8-bit log PCM
Advanced audio interface 520 kHz 8 kHz 14 Bits
A-law and u-law
Winbond W681360 Advanced audio interface 13-bit linear 520 kHz 8 kHz 13 Bits
PCM slave(1) Advanced audio interface 8/16 bits 128 - 1024 kHz 8 kHz 8/16 Bits
(1) In PCM slave mode, parameters are stored in NVS. Bit clock and frame clock must be generated by the host interface.
8.3.13.1.1 PCM Slave Configuration Example
PCM slave uses the slot 0, 1 slot per frame, 16 bit linear mode, long frame sync, normal frame sync. In this case,
0x03E0 should be stored in NVS. See LMX9838 Software User’s Guide, literature number SNOA498 for more
details.
8.3.14 Auxiliary Ports
8.3.14.1 RESET#
The RESET# is active low and will put radio and baseband into reset.
8.3.15 Digital Smart Radio
8.3.15.1 General Purpose I/Os
The LMX9838 device offers 3 pins which either can be used as indication and configuration pins or can be used
for General Purpose functionality. The selection is made out of settings derived out of the power up sequence.
In General Purpose configuration the pins are controlled hardware specific commands giving the ability to set the
direction, set them to high or low or enable a weak pull-up.
In alternate function the pins have pre-defined indication functionality. Please see Table 4 for a description on the
alternate indication functionality.
Table 4. Alternate GPIO Pin Configuration
PIN DESCRIPTION
Operation Mode pin to configure
OP4/PG4 Transport Layer settings during boot-up
PG6 GPIO - Link Status indication
PG7 RF Traffic indication
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8.3.16 Functional Architecture
The integrated Digital Smart Radio utilizes a heterodyne receiver architecture with a low intermediate frequency
(2 MHz) such that the intermediate frequency filters can be integrated on chip. The receiver consists of a low-
noise amplifier (LNA) followed by two mixers. The intermediate frequency signal processing blocks consist of a
poly-phase bandpass filter (BPF), two hard-limiters (LIM), a frequency discriminator (DET), and a post-detection
filter (PDF). The received signal level is detected by a received signal strength indicator (RSSI).
The received frequency equals the local oscillator frequency (fLO) plus the intermediate frequency (fIF):
fRF = fLO + fIF (supradyne).
The radio includes a synthesizer consisting of a phase detector, a charge pump, an (off-chip) loop-filter, an RF-
frequency divider, and a voltage controlled oscillator (VCO).
The transmitter utilizes IQ-modulation with bit-stream data that is gaussian filtered. Other blocks included in the
transmitter are a VCO buffer and a power amplifier (PA).
8.3.17 Receiver Front-End
The receiver front-end consists of a low-noise amplifier (LNA) followed by two mixers and two low-pass filters for
the I- and Q-channels.
The intermediate frequency (IF) part of the receiver front-end consists of two IF amplifiers that receive input
signals from the mixers, delivering balanced I- and Q-signals to the poly-phase bandpass filter. The poly-phase
bandpass filter is directly followed by two hard-limiters that together generate an AD-converted RSSI signal.
8.3.18 Poly-Phase Bandpass Filter
The purpose of the IF bandpass filter is to reject noise and spurious (mainly adjacent channel) interference that
would otherwise enter the hard limiting stage. In addition, it takes care of the image rejection.
The bandpass filter uses both the I- and Q-signals from the mixers. The out-of-band suppression should be
higher than 40 dB (f<1 MHz, f>3 MHz). The bandpass filter is tuned over process spread and temperature
variations by the autotuner circuitry. A 5th order Butterworth filter is used.
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8.3.19 Hard-Limiter and RSSI
The I- and Q-outputs of the bandpass filter are each followed by a hard-limiter. The hard-limiter has its own
reference current. The RSSI (Received Signal Strength Indicator) measures the level of the RF input signal.
The RSSI is generated by piece-wise linear approximation of the level of the RF signal. The RSSI has a mV/dB
scale, and an analog-to-digital converter for processing by the baseband circuit. The input RF power is converted
to a 5-bit value. The RSSI value is then proportional to the input power (in dBm).
The digital output from the ADC is sampled on the BPKTCTL signal low-to-high transition.
8.3.20 Receiver Back-End
The hard-limiters are followed by a two frequency discriminators. The I-frequency discriminator uses the 90×
phase-shifted signal from the Q-path, while the Q-discriminator uses the 90× phase-shifted signal from the I-path.
A poly-phase bandpass filter performs the required phase shifting. The output signals of the I- and Q-
discriminator are substracted and filtered by a low-pass filter. An equalizer is added to improve the eye-pattern
for 101010 patterns.
After equalization, a dynamic AFC (automatic frequency offset compensation) circuit and slicer extract the
RX_DATA from the analog data pattern. It is expected that the Eb/No of the demodulator is approximately 17 dB.
8.3.21 Frequency Discriminator
The frequency discriminator gets its input signals from the limiter. A defined signal level (independent of the
power supply voltage) is needed to obtain the input signal. Both inputs of the frequency discriminator have
limiting circuits to optimize performance. The bandpass filter in the frequency discriminator is tuned by the
autotuning circuitry.
8.3.22 Post-Detection Filter and Equalizer
The output signals of the FM discriminator first go through a post-detection filter and then through an equalizer.
Both the post-detection filter and equalizer are tuned to the proper frequency by the autotuning circuitry. The
post-detection filter is a low-pass filter intended to suppress all remaining spurious signals, such as the second
harmonic (4 MHz) from the FM detector and noise generated after the limiter.
The post-detection filter also helps for attenuating the first adjacent channel signal. The equalizer improves the
eye-opening for 101010 patterns. The post-detection filter is a third order Butterworth filter.
8.3.23 Autotuning Circuitry
The autotuning circuitry is used for tuning the bandpass filter, the detector, the post-detection filter, the equalizer,
and the transmit filters for process and temperature variations. The circuit also includes an offset compensation
for the FM detector.
8.3.24 Synthesizer
The synthesizer consists of a phase-frequency detector, a charge pump, a low-pass loop filter, a programmable
frequency divider, a voltage-controlled oscillator (VCO), a delta-sigma modulator, and a lookup table.
The frequency divider consists of a divide-by-2 circuit (divides the 5 GHz signal from the VCO down to 2.5 GHz),
a divide-by-8-or-9 divider, and a digital modulus control. The delta-sigma modulator controls the division ratio and
also generates an input channel value to the lookup table.
8.3.25 Phase-Frequency Detector
The phase-frequency detector is a 5-state phase-detector. It responds only to transitions, hence phase-error is
independent of input waveform duty cycle or amplitude variations. Loop lockup occurs when all the negative
transitions on the inputs, F_REF and F_MOD, coincide. Both outputs (i.e., Up and Down) then remain high. This
is equal to the zero error mode. The phase-frequency detector input frequency range operates at 12 MHz.
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8.3.26 Transmitter Circuitry
The transmitter consists of ROM tables, two Digital to Analog (DA) converters, two low-pass filters, IQ mixers,
and a power amplifier (PA).
The ROM tables generate a digital IQ signal based on the transmit data. The output of the ROM tables is
inserted into IQ-DA converters and filtered through two low-pass filters. The two signal components are mixed up
to 2.5 GHz by the TX mixers and added together before being inserted into the transmit PA.
8.3.27 IQ-DA Converters and TX Mixers
The ROM output signals drive an I- and a Q-DA converter. Two Butterworth low-pass filters filter the DA output
signals. The 6 MHz clock for the DA converters and the logic circuitry around the ROM tables are derived from
the autotuner.
The TX mixers mix the balanced I- and Q-signals up to 2.4-2.5 GHz. The output signals of the I- and Q-mixers
are summed.
8.3.28 32 kHz Oscillator
An oscillator is provided (see Figure 1) that is tuned to provide optimum performance and low-power
consumption while operating with a 32.768 kHz crystal. An external crystal clock network is required between the
32k+ clock input (pad 27) and the 32k- clock output (pad 28) signals.The oscillator is built in a Pierce
configuration and uses two external capacitors. Table 5 provides the oscillator’s specifications.
In case the 32kHz is not used, it is recommended to leave 32k- open and connect 32k+ to GND.
Figure 1. 32.768 kHz Oscillator
Table 5. 32.768 kHz Oscillator Specifications
PARAMETER CONDITION MIN TYP MAX UNIT
VDD Supply Voltage 1.62 1.8 1.98 V
IDDACT Supply Current (Active) 2 µA
f Nominal Output Frequency 32.768 kHz
VPPOSC Oscillating Amplitude 1.8 V
Duty Cycle 40% — 60%
8.3.29 Integrated Firmware
The LMX9838 device includes the full Bluetooth stack up to RFComm to support the following profiles:
• GAP (Generic Access Profile)
• SDAP (Service Discovery Application Profile)
• SPP (Serial Port Profile)
Figure 2 shows the Bluetooth protocol stack with command interpreter interface. The command interpreter offers
a number of different commands to support the functionality given by the different profiles. Execution and
interface timing is handled by the control application.
The chip has an internal data area in RAM that includes the parameters shown in Table 6.
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Figure 2. LMX9838 Software Implementation
8.4 Device Functional Modes
8.4.1 Operation Modes
On boot-up, the application configures the module following the parameters in the data area.
8.4.1.1 Automatic Operation
8.4.1.1.1 No Default Connections Stored:
In Automatic Operation the module is connectable and discoverable and automatically answers to service
requests. The command interpreter listens to commands and links can be set up. The full command list is
supported.
If connected by another device, the module sends an event back to the host, where the RFComm port has been
connected, and switches to transparent mode.
8.4.1.1.2 Default Connections Stored
If default connections were stored on a previous session, once the LMX9838 is reset, it will attempt to connect
each device stored within the data RAM three times. The host will be notified about the success of the link setup
via a link status event.
8.4.1.1.3 Non-Automatic Operation
In Non-Automatic Operation, the LMX9838 does not check the default connections section within the Data RAM.
If connected by another device, it will NOT switch to transparent mode and continue to interpret data sent on the
UART.
8.4.1.1.4 Transparent Mode
The LMX9838 supports transparent data communication from the UART interface to a bluetooth link.
If activated, the module does not interpret the commands on the UART which normally are used to configure and
control the module. The packages don’t need to be formatted as described in Table 8. Instead all data are
directly passed through the firmware to the active bluetooth link and the remote device.
Transparent mode can only be supported on a point-to-point connection. To leave Transparent mode, the host
must send a UART_BREAK signal to the module.
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Device Functional Modes (continued)
8.4.1.1.5 Force Master Mode
In Force Master mode tries to act like an access point for multiple connections. For this it will only accept the link
if a Master/slave role switch is accepted by the connecting device. After successful link establishment the
LMX9838 will be Master and available for additional incoming links. On the first incoming link the LMX9838 will
switch to transparent depending on the setting for automatic or command mode. Additional links will only be
possible if the device is not in transparent mode.
8.4.2 Default Connections
The LMX9838 device supports the storage of up to 3 devices within its NVS. Those connections can either be
connected after reset or on demand using a specific command.
8.4.3 Event Filter
The LMX9838 uses events or indicators to notify the host about successful commands or changes at the
bluetooth interface. Depending on the application the LMX9838 can be configured. The following levels are
defined:
• No Events:
– The LMX9838 is not reporting any events. Optimized for passive cable replacement solutions.
• Standard LMX9838 events:
– Only necessary events will be reported.
• All events:
– Additional to the standard all changes at the physical layer will be reported.
8.4.4 Default Link Policy
Each Bluetooth Link can be configured to support M/S role switch, Hold Mode, Sniff Mode and Park Mode. The
default link policy defines the standard setting for incoming and outgoing connections.
8.4.5 Audio Support
The LMX9838 offers commands to establish and release synchronous connections (SCO) to support Headset or
Handsfree applications. The firmware supports one active link with all available package types (HV1, HV2, HV3),
routing the audio data between the bluetooth link and the advanced audio interface. In order to provide the
analog data interface, an external audio codec is required. The LMX9838 includes a list of codecs which can be
used.
Table 6. Operation Parameters Stored in LMX9838
PARAMETER DEFAULT VALUE DESCRIPTION
BDADDR Preprogrammed by TI Bluetooth device address
Local Name Serial port device
PinCode 0000 Bluetooth PinCode
Operation Mode Automatic ON Automatic mode ON or OFF
Default Connections 0 Up to seven default devices to connect to
1 SPP entry:
Name: COM1
SDP Database Service discovery database, control for supported profiles
Authentication and encryption
enabled
UART Speed 9600 Sets the speed of the physical UART interface to the host
UART Settings 1 Stop bit, parity disabled Parity and stop bits on the hardware UART interface
Ports to Open 0000 0001 Defines the RFComm ports to open
Link Keys No link keys Link keys for paired devices
Security Mode 2 Security mode
Page Scan Mode Connectable Connectable/Not connectable for other devices
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Device Functional Modes (continued)
Table 6. Operation Parameters Stored in LMX9838 (continued)
PARAMETER DEFAULT VALUE DESCRIPTION
Discoverable/Not Discoverable/Limited Discoverable for other
Inquiry Scan Mode Discoverable devices
Configures modes allowed for incoming or outgoing connections
Default Link Policy All modes allowed (Role switch, Hold mode, Sniff mode...)
The Default Link Timeout configures the timeout, after which the link
Default Link Timeout 20 seconds is assumed lost, if no packages have been received from the remote
device
Defines the level of reporting on the UART
- no events
Event Filter Standard LMX9838 events reported - standard events
- standard including ACL link events
Configures the settings for the external codec and the air format.
• Codecs:
- Winbond W681360
- OKI MSM7717 / Winbond W681310
Default Audio Settings none - PCM Slave
• Air Format:
- CVSD
- µ-Law
- A-Law
8.4.6 Low Power Modes
The LMX9838 supports different Low Power Modes to reduce power in different operating situations. The
modular structure of the LMX9838 allows the firmware to power down unused modules.
The Low power modes have influence on:
• UART transport layer
– enabling or disabling the interface
• Bluetooth Baseband activity
– firmware disables LLC and Radio if possible
8.4.6.1 Power Modes
The following LMX9838 power modes, which depend on the activity level of the UART transport layer and the
radio activity are defined:
The radio activity level mainly depends on application requirements and is defined by standard bluetooth
operations like inquiry/page scanning or an active link.
A remote device establishing or disconnecting a link may also indirectly change the radio activity level.
The UART transport layer by default is enabled on device power up. In order to disable the transport layer the
command “Disable Transport Layer” is used. Thus only the Host side command interface can disable the
transport layer. Enabling the transport layer is controlled by the HW Wakeup signalling. This can be done from
either the Host or the LMX9838. See the LMX9838 Software User’s Guide, literature number SNOA498 for
detailed information on timing and implementation requirements.
Table 7. Power Mode Activity
POWER MODE UART ACTIVITY RADIO ACTIVITY REFERENCE CLOCK
PM0 OFF OFF none
PM1 ON OFF Main Clock
PM2 OFF Scanning Main Clock / 32.768 kHz
PM3 ON Scanning Main Clock
PM4 OFF SPP Link Main Clock
PM5 ON SPP Link Main Clock
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Figure 3. Transition Between Different Hardware Power Modes
8.4.7 Enabling and Disabling UART Transport
8.4.7.1 Hardware Wake-up Functionality
In certain usage scenarios the host is able to switch off the transport layer of the LMX9838 in order to reduce
power consumption. Afterwards both devices, host and LMX9838 are able to shut down their UART interfaces.
In order to save system connections the UART interface is reconfigured to hardware wake-up functionality. For a
detailed timing and command functionality, see the LMX9838 Software User’s Guide, AN-1699 literature number
SNOA498. The interface between host and LMX9838 is defined as described in Figure 4.
Figure 4. UART NULL Modem Connection
8.4.7.2 Disabling the UART Transport Layer
The Host can disable the UART transport layer by sending the “Disable Transport Layer” Command. The
LMX9838 will empty its buffers, send the confirmation event and disable its UART interface. Afterwards the
UART interface will be reconfigured to wake up on a falling edge of the CTS pin.
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