Texas Instruments AM5728 User manual

AM571x Industrial Development Kit (IDK)
Evaluation Module (EVM) Hardware
User's Guide
Literature Number: SPRUI97D
May 2017–Revised September 2019

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Table of Contents
Contents
Preface ........................................................................................................................................ 5
1 Introduction......................................................................................................................... 6
1.1 Description ................................................................................................................ 6
1.2 System View.............................................................................................................. 7
2 Functional Description........................................................................................................ 11
2.1 Processor................................................................................................................ 12
2.2 Clocks.................................................................................................................... 12
2.3 Reset Signals ........................................................................................................... 12
3 Power Supplies.................................................................................................................. 13
3.1 Power Source ........................................................................................................... 13
3.2 TPS6590377 PMIC..................................................................................................... 13
3.3 AVS Control ............................................................................................................. 13
3.4 Other Power Supplies.................................................................................................. 14
4 Configuration/Setup............................................................................................................ 15
4.1 Boot Configuration...................................................................................................... 15
4.2 I2C Address Assignments............................................................................................. 15
4.3 SEEPROM Header..................................................................................................... 16
4.4 JTAG Emulation ........................................................................................................ 16
5 Memories Supported........................................................................................................... 17
5.1 DDR3L SDRAM......................................................................................................... 17
5.2 SPI NOR Flash.......................................................................................................... 17
5.3 Board Identity Memory................................................................................................. 17
5.4 SD/MMC ................................................................................................................. 17
5.5 eMMC NAND Flash .................................................................................................... 17
6 Ethernet Ports.................................................................................................................... 18
6.1 100Mb Ethernet Ports on PRU-ICSS ................................................................................ 18
6.2 Gigabit (1000Mb) Ethernet Ports ..................................................................................... 18
7 USB Ports.......................................................................................................................... 19
7.1 Processor USB Port 1.................................................................................................. 19
7.2 Processor USB Port 2.................................................................................................. 19
7.3 FTDI USB Port.......................................................................................................... 19
8 PCIe.................................................................................................................................. 20
9 Video Input and Output....................................................................................................... 20
9.1 Camera................................................................................................................... 20
9.2 HDMI ..................................................................................................................... 20
9.3 LCD....................................................................................................................... 20
10 Industrial Interfaces............................................................................................................ 21
10.1 Profibus .................................................................................................................. 21
10.2 DCAN..................................................................................................................... 21
10.3 RS-485................................................................................................................... 21
11 User Interfaces................................................................................................................... 21

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Contents
11.1 Tri-color LEDs........................................................................................................... 21
11.2 Industrial Inputs......................................................................................................... 21
11.3 Industrial Outputs / LEDs.............................................................................................. 21
12 Pin Use Description............................................................................................................ 22
12.1 Functional Interface Mapping ......................................................................................... 22
12.2 GPIO Pin Mapping...................................................................................................... 22
13 Board Connectors .............................................................................................................. 24
14 EVM Important Notice ......................................................................................................... 37
Appendix A Known Deficiencies in AM571x IDK EVM ..................................................................... 38
A.1 Power solution not sufficient for full PCIe plug-in card compliance............................................. 38
A.2 Early versions of the AM571x IDK EVM not installed with SOC devices rated for the full industrial
temperature range...................................................................................................... 38
A.3 AM571x IDK EVM does not support eMMC HS200 mode....................................................... 38
A.4 PCIe PERSTn line not in proper state at start-up................................................................. 38
A.5 EDIO connectors J4 and J7 should support real-time debugging for both PRU1 and PRU2............... 38
A.6 HDQ implementation not correct .................................................................................... 38
A.7 Removing the power plug and inserting it again while the power supply is energized may cause
damage .................................................................................................................. 38
A.8 Software shutdown of PMIC not operational ...................................................................... 39
A.9 CCS System Reset fails ............................................................................................. 39
A.10 AM571x IDK EVM design contains 2 clamp circuits that may not be necessary ............................. 39
A.11 Crystal connected to osc0 needs to have 50ppm or better long term accuracy.............................. 39
A.12 Software must program the CDCE913 for 0pf load capacitance................................................ 39
A.13 Protection diode D2 should be rated for 5V ....................................................................... 39
A.14 PHY address LSB for U9 and U15 can be latched incorrectly .................................................. 40
A.15 3.3-V clamp circuit needs more margin ............................................................................ 40
A.16 Current PMIC does not provide the mandated power down sequence ........................................ 40
A.17 Power supply droop may cause board reset ...................................................................... 40
A.18 AM5718 pin N21 must be connected to 1.8 V, as it is VDDS18V_DDR1 and not N/C...................... 40
A.19 VOUT1 is used at 3.3 V, which violates erratum i920............................................................ 40
A.20 PMIC OSC16MCAP pin mistakenly grounded .................................................................... 40
Revision History.......................................................................................................................... 41

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List of Figures
List of Figures
1 AM571x IDK EVM - Top View.............................................................................................. 7
2 AM571x IDK EVM - Bottom View.......................................................................................... 8
3 AM571x IDK EVM with Camera Board Installed......................................................................... 9
4 AM571x IDK EVM with LCD Display Assembly Attached ............................................................ 10
5 AM571x IDK EVM Block Diagram ....................................................................................... 11
6 Connections from the TPS6590377 PMIC to the AM571x Processor............................................... 14
List of Tables
1 I2C1/IND_I2C............................................................................................................... 15
2 I2C2/AM571X_HDMI_DDC ............................................................................................... 15
3 SEEPROM Header......................................................................................................... 16
4 PRU-ICSS Ethernet Ports................................................................................................. 18
5 GPIO Pin Mapping ......................................................................................................... 23
6 Expansion Connector - J21............................................................................................... 24
7 I/O Expansion Header Connector - J37................................................................................. 26
8 MicroSD Connector - J15 ................................................................................................. 27
9 Power Jack Connector - J1 ............................................................................................... 27
10 Power Terminal Block Connector - J2................................................................................... 27
11 PRU1ETH0 RJ45 Connector - J3........................................................................................ 28
12 PRU1ETH1 RJ45 Connector - J5........................................................................................ 28
13 PRU2ETH0 RJ45 Connector - J6........................................................................................ 29
14 PRU2ETH1 RJ45 Connector - J8........................................................................................ 29
15 PRU2ETH0 Test Header Connector - J7 ............................................................................... 30
16 PRU2ETH1 Test Header Connector - J4 ............................................................................... 30
17 Camera Connector - J9.................................................................................................... 30
18 GigE RJ45 Connector - J10............................................................................................... 31
19 GigE RJ45 Connector - J12............................................................................................... 31
20 LCD Module FFC Connector - J16....................................................................................... 32
21 Touchscreen Controller FFC Connector - J17 ......................................................................... 32
22 HDMI Standard A-type Connector - J24 ................................................................................ 33
23 CTI-20 JTAG Connector - J18............................................................................................ 33
24 JTAG USB Micro-AB Connector - J19 .................................................................................. 34
25 USB Port 1 USB2.1 Standard A-type Connector - J23................................................................ 34
26 USB Port 2 USB2.1 Micro-AB Connector - J45........................................................................ 34
27 CAN Header Connector - J38 ............................................................................................ 35
28 Profibus DB9F Connector - J14.......................................................................................... 35
29 RS-485 Header Connector - J39......................................................................................... 35
30 PCIe Connector – J52..................................................................................................... 36

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Preface
Preface
SPRUI97D–May 2017–Revised September 2019
Read This First
About This Manual
This document describes the hardware architecture of the AM571x Industrial Development Kit (IDK)
Evaluation Module (EVM) (Part# TMDXIDK571x) that supports the Texas Instruments Sitara™ ARM®
Cortex®-A15 AM571x processor family.
Glossary
TI Glossary —This glossary lists and explains terms, acronyms, and definitions.
Related Documentation From Texas Instruments
For product information, visit the Texas Instruments website at http://www.ti.com.
SPRS957—AM571x Sitara Processors Silicon Revision 2.0 Data Manual
SPRZ436—AM571x Sitara Processors Silicon Errata. Describes the known exceptions to the functional
specifications for the device.
SPRUHZ7—AM571x Sitara Processors Silicon Revision 2.0, 1.0 Technical Reference Manual. Details
the integration, the environment, the functional description, and the programming models for each
peripheral and subsystem in the device.
Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help —
straight from the experts. Search existing answers or ask your own question to get the quick design help
you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications
and do not necessarily reflect TI's views; see TI's Terms of Use.
Trademarks
Sitara, E2E, Code Composer Studio, SmartReflex are trademarks of Texas Instruments.
ARM, Cortex are registered trademarks of ARM Limited.
Windows is a registered trademark of Microsoft Corporation.

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AM571x Industrial Development Kit (IDK) Evaluation Module (EVM)
Hardware
User's Guide
SPRUI97D–May 2017–Revised September 2019
AM571x Industrial Development Kit (IDK)
Evaluation Module (EVM) Hardware
1 Introduction
This document describes the hardware architecture of the AM571x Industrial Development Kit (IDK)
Evaluation Module (EVM) (Part# TMDXIDK571x) that supports the Texas Instruments Sitara™ ARM®
Cortex®-A15 AM571x processor family.
1.1 Description
The AM571x IDK is a standalone test, development, and evaluation module that enables developers to
write software and develop hardware for industrial control and industrial communications applications. It
has been equipped with a TI AM5718 processor and a defined set of features to allow you to experience
industrial communication solutions using various serial or Ethernet based interfaces. Using standard
interfaces, the AM571x IDK may interface to other processors or systems and act as a communication
gateway or controller. In addition, it can directly operate as a standard remote I/O system or a sensor
connected to an industrial communication network.
The AM571x IDK contains embedded emulation circuitry to quickly enable developers to begin using this
IDK. The embedded emulation logic allows emulation and debug using standard development tools such
as the Texas Instruments Code Composer Studio™ integrated development environment (IDE) by simply
connecting a USB cable to a Windows®-based computer.
The standard (4-port Ethernet) configuration for the AM571x IDK EVM provides the following functionality:
• Two Gigabit (1000Mb) metallic ports connected via PHY/RGMII to the on-chip Ethernet switch
• Two 100Mb metallic ports connected via PHY/MII to the PRU-ICSS subsystems
• LCD panel output from Display Parallel Interface (DPI) Video Output 1
Reconfiguration through header shunt removal provides an alternate 6-port Ethernet configuration:
• Two Gigabit (1000Mb) metallic ports connected via PHY/RGMII to the on-chip Ethernet switch
• Four 100Mb metallic ports connected via PHY/MII to the PRU-ICSS subsystems
Software support for the AM571x IDK EVM is provided within the Processor Software Development Kit
(SDK) package. This includes both Linux and RTOS support.

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AM571x Industrial Development Kit (IDK) Evaluation Module (EVM)
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1.2 System View
The system view of the AM571x IDK EVM consists of the main board and the camera board. There is also
an optional LCD panel and touch screen assembly that can be attached to the AM571x IDK EVM.
The top and the bottom views of the AM571x IDK EVM are provided in Figure 1 and Figure 2,
respectively.
The top view of the AM571x IDK EVM with the camera board installed is provided in Figure 3. The side
view of the AM571x IDK EVM with the optional LCD display assembly attached is provided in Figure 4.
Figure 1. AM571x IDK EVM - Top View

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Figure 2. AM571x IDK EVM - Bottom View

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AM571x Industrial Development Kit (IDK) Evaluation Module (EVM)
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Figure 3. AM571x IDK EVM with Camera Board Installed

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Figure 4. AM571x IDK EVM with LCD Display Assembly Attached

AM571x
DDR1 QSPI
RGMII0
MMC1
HDMI / I2C2
PCIe / I2C1
HDMI
PCIe x2
GbE
MMC2 I2C
QSPI
32MB
eMMC
16GB uSD EEPROM
USB2.0
MicroAB
I2C
USB2
UART
Camera
Header VIN4B / I2C1
JTAG
JTAG
(60-pin)
ICs
TI ICs
Connectors
ISO1176T Profibus
DB9
PRU UART
TPS6590377
PMIC
KSZ9031
DDR3
1GB
w/ECC
Warm
RESET
INT
RGY LED ENET Status
GPIO
GPIO
RGMII1
GbE
KSZ9031
DCAN1
USB1 USB2.0
Std A
FTDI USB
SN65HVD78D RS485
Header
UART2
Industrial Inputs &
Outputs/LEDs
SPI3 / I2C1
LCD &
Touch Panel
MIPI
Serializer
VOUT1/PR1_MII0_1
ISO1050
TPD6E001
TPD4S012
TPD2EUSB30
DCAN
Header
TPD12S016
TLK105L
ICSS0
RJ45
TLK105L
ICSS0
RJ45
TLK105L
ICSS1
RJ45
PR2_MII0
TLK105L
ICSS1
RJ45
PR2_MII1
ICSS Header
prx_mii0/1_txen/rxdv,
prx_edio_data_out + sync
FET Switches
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AM571x Industrial Development Kit (IDK) Evaluation Module (EVM)
Hardware
2 Functional Description
The AM571x IDK EVM is implemented on a single board with interface circuitry, memory ICs, and
connectors around the AM5718 processor. The board also contains power conversion circuitry to
efficiently create the needed power supply voltages from a single +5V input. As stated previously, this
EVM ships with a separate camera module that plugs in to the main board. An optional LCD panel and
touch screen assembly can be purchased separately and mounted on to the main board.
Figure 5 shows the functional block diagram of the AM571x IDK EVM.
Figure 5. AM571x IDK EVM Block Diagram

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2.1 Processor
The AM5718 processor is the central processing unit for this IDK EVM. The interface circuitry, memory
ICs, and connectors implemented on the board around the AM5718 processor provide development
support for the many industrial communication interfaces available on this platform. See the AM571x
Sitara Processors Silicon Revision 2.0 Data Manual (SPRS957) and the AM571x Sitara Processors
Technical Reference Manual (SPRUHZ7) for details about the processor.
The AM571x IDK EVM contains system configuration for the boot mode control inputs SYSBOOT[15..0].
These can be strapped using resistors. The default configuration will meet the needs of most developers.
Resistor reconfiguration is supported so that you can explore other boot configurations of the AM571x
processor. See Section 4 for more details.
2.2 Clocks
The main clock for the processor is derived from a 20-MHz crystal. An on-board oscillator in the AM571x
processor generates the base clock and the subsequent module clocks as needed within the AM571x
processor. The board design supports a crystal attached to the RTC block, but this is not needed since
RTC-only mode is not supported in this device.
2.3 Reset Signals
The AM571x processor contains 3 reset inputs and an output indicating a reset is in progress. The reset
pins are:
• PORz: PORz is a hard reset that resets everything including emulation logic. It also tri-states most
outputs.
• RESETn: RESETn is a device reset commonly driven by control logic or emulation.
• RTC_PORz: Separate PORz for the RTC module that must be driven at the same time as PORz.
(Note that PORz and RTC_PORz can only be directly connected as long as VDDSHV3 and VDDSHV5
are driven at the same voltage.)
• RSTOUTn: Output signal from SOC indicating that the device has entered reset. This is used to reset
other circuits that must be reset at the same time as the processor.
More details about the behavior of these reset pins within the AM571x processor can be found in the
AM571x Sitara Processors Silicon Revision 2.0 Data Manual (SPRS957). There are push buttons on the
IDK that can initiate either a RESETn or PORz input. SW1 can drive PORz active (low) and SW2 can
drive RESETn active (low).
There is a device erratum in all of the AM571x devices that prevents use of RESETn independent from
PORz (see i862, Reset Should Use PORz, in the AM571x Sitara Processors Silicon Errata (SPRZ436).
The workaround is to generate PORz whenever a device reset occurs even if it is from an internal initiator.
This is accomplished through cooperation with the PMIC paired with the AM571x device on the IDK EVM.
The RSTOUTn output from the AM571x device is connected to the NRESWARM input of the PMIC. This
initiates a re-start that drives RESET_OUT low and resets all voltages to their initial values. Since
RESET_OUT from the PMIC is connected to PORz in the AM571x device, a hard reset is forced on the
SOC that meets the needs of the erratum workaround.
The AM571x IDK EVM is started by pressing the start-up push button, SW3. The POWERHOLD input can
be connected to VRTC_OUT in customer designs to cause the board to power-on as soon as the main
supply is stable.
The configuration of the PMIC to provide RESET_OUT from the NRESWARM input creates an always-on
implementation. This always-on mode of operation prevents software shut-down of the IDK. Customer
designs should have power-good monitoring circuitry such as a TPS3808 connected to the main supply to
the PMIC that is connected to the PMIC RESET_IN, as shown in the AM571x IDK EVM schematic (v1.3).
The TPS3808 can detect the main supply voltage dropping and then trigger the PMIC to execute a
controlled shut-down that meets the requirements in the AM571x Sitara Processors Silicon Revision 2.0
Data Manual (SPRS957).

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3 Power Supplies
This section describes how the power supplies required for the design are generated.
3.1 Power Source
The AM571x IDK EVM uses an external 5V power supply. The 5V power input is converted into different
voltage levels to provide power inputs to the AM571x processor and other circuitry.
Early versions of the AM571x IDK EVM shipped with the GlobTek, Inc. external power supply with the part
number TR9CA6500LCP-N, model number GT-43008-3306-1.0-T3. This external power supply is rated for
an output voltage of +5VDC with an output current up to 6.5A. This external power supply contains
applicable regional product regulatory/safety certification requirements for most worldwide locations. If you
cannot use this supply, one with equivalent ratings that is approved for your location must be obtained.
Note that recently sold IDK EVMs do not ship with a power supply in the box due to international
concerns. Also note that the power supply listed above is being discontinued. The manufacturer has
provided a drop-in replacement. This is the TR9CA8000LCPIM(R6B), which is readily available from
distributors such as Digikey.
The AM571x IDK EVM contains a right angle mounted power connector that accepts the +5VDC supply
input on the center pin with the outer shell as the common return. The power connector accepts a mating
plug with a 2.5-mm ID and a 5.5-mm OD.
Removing the power plug and inserting it again while the power supply is energized may damage the
AM571x IDK EVM and/or other devices attached to the board such as emulators that provide an alternate
path to ground. Removal of AC power from the external power supply is a safer method, if required.
It is recommended that the external power supply have the common return bonded to earth ground. If this
is not possible, a separate connection from the board ground to earth ground may need to be provided.
Terminal block J53 is added for this purpose.
3.2 TPS6590377 PMIC
The power requirements of the processor are met by the TPS6590377 Power Management IC (PMIC).
The power sequencing requirements of the AM571x processor are also handled by the TPS6590377
PMIC. Figure 6 shows the supply connections from the TPS6590377 PMIC to the AM571x processor.
Refer to the AM571x Sitara Processors Silicon Revision 2.0 Data Manual (SPRS957) for more information
about the required supply voltages and supply sequencing. Also refer to the TPS659037 Power
Management Unit (PMU) for Processor Data Manual (SLIS165) and the TPS659037 User's Guide to
Power AM572x and AM571x User’s Guide (SLIU011) for details about its operation.
Note that the production version of the AM571x IDK EVM uses the TPS6590377 PMIC that supplies the
voltages needed for the latest silicon version of the AM5718 processor. Beta prototype IDK EVM units
used the TPS6590375 PMIC and Alpha prototype IDK EVM units used the TPS6590372 PMIC.
3.3 AVS Control
The AM571x processor consumes most of its power in its core logic. Therefore, minimizing the voltage
supplied to this core logic can minimize power consumption. SmartReflex™ technology is used to provide
this optimized solution.
This core logic is separated into multiple segments that can each be controlled separately. In this way,
applications that need more performance in some processing blocks can operate at higher performance
levels by increasing the supply voltage, while other processing blocks that do not require the same level of
performance can operate at lower voltage thus further optimizing system power consumption.
The TPS6590377 PMIC is connected to the I2C1 on the AM5718 processor. This allows the application
software to individually control the AVS supply outputs. It also allows the application to control the voltage
generated by LDO1 that is used for the SDIO interface that operates at either 1.8V or 3.3V depending on
the operating mode.

5-V Input
Power
SMPS1, SMPS2
AVS (6 A max)
SMPS4, SMPS5
AVS (4 A max)
SMPS6
AVS (3 A max)
SMPS8
AVS (1 A max)
SMPS7
AVS (2 A max)
LDO9
(50 mA max)
LDOLN
(100 mA max)
LDO3
(200 mA max)
LDOVRTC
(25 mA max)
LDO1
(300 mA max)
LDOUSB
(100 mA max)
SMPS3
(3 A max)
PMIC
TPS659037
TPS51200
5 V
VDD_MPU
VDD_DSPEVE
VDD_GPU
VDD_IVAHD
VDD_CORE
VDD_RTC
VDDSHV8 (SDIO)
VDDA_USB3V3
VDD_DDR
Dual-Voltage Rails
(set to 3.3 V)
1V8
3V3
5V0
EMIF1
EMIF2
VTT
DDR Other Domains
Processor
Core Domains
1.06 V
1.15 V
1.15 V
1.05 V
1.06 V
1.06 V
1.35 V or 1.5 V
1.35 V or 1.5 V
1.8 V
1.8 V
1.35 V or 1.5 V
1.8 V
3.3 V
3.3 V
1.8 V
0.675 V or 0.75 V
1.8 V
Peripherals
DDR_REF
SMPS9
(1 A max)
LDO2
(300 mA max)
VDDSHV5 (RTC I/O)
3.3 V
3.3 V
VREF
0.675 V or 0.75 V
VDD_1V8
VDDA_1V8 (PLLs)
1V8_PHY (USB/SATA)
VDDA_RTC
1.8-V Domains
1V8_PHY (HDMI/PCIe)
LDO4
(200 mA max)
OSC16MIN
OSC16MOUT
1.8 V
3.3V Input
Power
TPS22965
(Power Switch)
REGEN1
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Figure 6. Connections from the TPS6590377 PMIC to the AM571x Processor
3.4 Other Power Supplies
The AM571x IDK EVM contains 8 other power conversion devices that support the interface and memory
circuitry:
• TPS63010 Buck-Boost Converter: This converter generates 5.0V from the main supply input. It
supplies this voltage to the industrial interface circuits, the HDMI interface and to the USB master
ports.
• TPS61085 Boost Converter: This converter generates 12.0V from the main supply input. It supplies
voltage to the industrial interface circuits and the PCIe card connector.
• TPS51200 DDR Termination Voltage LDO (2 each): This LDO provides the push/pull termination
current required for the DDR3 memory interfaces. There is one implemented for each DDR3 EMIF.
• LP38693ADJ Low-Dropout Regulator: This LDO generates the 3.7V LCD bias voltage.
• TPS61081DRC LCD Backlight Generator: This Boost converter generates the LCD backlight supply.
• TPS71712 Low-Dropout Regulator: This LDO generates the 1.2V supply needed for the LCD driver
logic.
• TPS76650 Low-Dropout Regulator: This LDO generates the 5.0V supply needed for the Profibus
interface.
• R1Z-3.305HP Isolated DC-DC Supply: This converter generates 5.0V isolated from the primary
3.3V DC supply on board for the DCAN interface.

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4 Configuration/Setup
This section discusses the board configuration.
4.1 Boot Configuration
Various boot configurations can be set using the pull-up/pull-down resistor combinations provided on the
SYSBOOT[15..0] pins. Boot configuration pins are latched upon de-assertion of the PORz pin. Refer to
the AM571x Sitara Processors Silicon Revision 2.0 Data Manual (SPRS957) for more details. The
AM571x IDK EVM is configured by default to 0x8106 to enable UBOOT/Linux boot from the SDCARD.
The secondary boot device selected by this boot mode is QSPI1.
4.2 I2C Address Assignments
The AM571x IDK EVM contains multiple I2C buses connected to a master port on the processor. Each
bus contains one or more I2C slave devices that must have unique addresses to prevent contention.
Table 1 and Table 2 list the addresses of the I2C slave devices attached to buses I2C1 and I2C2,
respectively.
Table 1. I2C1/IND_I2C
I2C Slave Device Address(es)
TPS590377 PMIC, U3 0x58, 0x59, 0x5A, 0x5B, 0x12
Camera Header, J9 Undefined
CDCE913 Ethernet Clock Generator A, U23 0x65
TPIC2810 Industrial Output Driver, U89 0x60
LCD Panel Driver TC358778, U73 0x0E
Touchscreen FPC Connector, J17 —
ID Memory SEEPROM, U33 0x50
PCIe Card Connector, J52 Undefined
Expansion Connector, J21 Undefined
Table 2. I2C2/AM571X_HDMI_DDC
I2C Slave Device Address(es)
HDMI Bridge, U46 —
CDCE913 Ethernet Clock Generator B, U25 0x65
NOTE: SCL/SDA names are swapped between the HDMI DDC port and I2C2 port on AM57xx
devices – I2C2 schematic connections to U25 must be reversed.

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Hardware
4.3 SEEPROM Header
Each of the AM571x IDK EVMs has a unique serial number. This serial number is printed on a sticker
attached to the IDK and it is programmed into a SEEPROM memory device connected to the AM5718
processor over the I2C bus. The SEEPROM also contains board details such as board type, version,
configuration, and so on. This information is stored in a structure at the beginning of the SEEPROM in a
known format that can be read by the application software. These values are all stored with the first
character or MSB stored at the lowest addressable location in each field. Table 3 lists all of the fields in
this header definition.
Table 3. SEEPROM Header
Name Size (bytes) Contents
Header 4 MSB 0xEE3355AA LSB
Board Name 8 Name for board in ASCII “AM571IDK” = AM571x Industrial Development Kit EVM.
Version 4 Hardware version code for board in ASCII “1.3A” = revision 01.3A
Serial Number 12 Serial number of the board. This is a 12-character string that is: WWYY4P52nnnn, where
WW = 2 digit week of the year of production, YY = 2 digit year of production,
nnnn = incrementing board number.
Configuration Option 32 Codes to show the configuration setup on this board. Reserved.
Ethernet MAC
Address #0 6 Ethernet MAC Address #0 assigned to the AM571x IDK EVM. This is the first of a block of addresses available for the Industrial Interface ports.
Ethernet MAC
Address #5 6 Ethernet MAC Address #5 assigned to the AM571x IDK EVM. This is the last of a block of 6 contiguous addresses available for the industrial interface ports.
Available 32696 Available user space for other non-volatile codes/data.
4.4 JTAG Emulation
The AM571x IDK EVM supports embedded XDS100V2 USB Emulation through the USB Micro-AB
connector, J19, and the FTDI controller. This controller is powered from the USB VBUS, thus the emulator
connection to the PC is retained whenever the IDK is power cycled.
The AM571x IDK EVM also has a 20-pin CTI JTAG connector, J18, to support standard external
emulators that may operate more efficiently than the embedded XDS100V2 emulation. The AM571x IDK
EVM does not support emulation trace capability.

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5 Memories Supported
The AM571x IDK EVM supports on-board memories including DDR3L SDRAM, SPI NOR Flash, eMMC
NAND Flash, and I2C SEEPROM. It also supports a MicroSD card socket that can add memory storage.
5.1 DDR3L SDRAM
The AM571x IDK EVM design supports a single bank of DDR3L SDRAM that is attached to the EMIF on
the AM5718 processor. The EMIF can support up to 2GB of DDR3L SDRAM memory at speeds up to
1333MT/s. The SDRAM implemented on the EMIF on the IDK EVM contains two 4Gbit (256M × 16)
SDRAMs for a total of 1GB of DDR3L SDRAM memory. The part number for the DDR3L SDRAM memory
used is MT41K256M16HA-125 that contains timing for 1600MT/s operation. The package used is the 96-
ball TFBGA package. See the AM571x Sitara Processors Technical Reference Manual (SPRUHZ7) for
memory locations for this memory.
The EMIF also contains an SDRAM attached to the ECC byte lane. Use of ECC on the DDR3L interface is
currently highly constrained by limitations in the AM571x devices. Refer to the AM571x Sitara Processors
Silicon Errata (SPRZ436) for more details.
5.2 SPI NOR Flash
The AM571x IDK EVM supports a 256Mbit (32MB) SPI Flash Memory from Spansion (S25FL256S) in a
16-pin SOIC package. It is connected to the QSPI port of the AM5718 device.
5.3 Board Identity Memory
Each of the AM571x IDK EVM boards contains a 256Kb (32KB) Serial EEPROM that contains board-
specific data. This data allows the application software to automatically detect the type of board that it is
running on and also to determine its version and, potentially, optional features. Other hardware specific
data can be stored on this memory device as well. The part number of the memory device is
CAT24C256WI-G in a SOIC-8 package. Refer to Section 4 for details on the data stored in this memory.
5.4 SD/MMC
The SD/MMC connector on the AM571x IDK EVM is a MicroSD connector (part number SCHA5B0200).
This is a standard SD/MMC card type of connector. It is connected to the MMC1 port of the AM571x
processor that is optimized for this use. Refer to the AM571x Sitara Processors Silicon Revision 2.0 Data
Manual (SPRS957) and the AM571x Sitara Processors Technical Reference Manual (SPRUHZ7) for
supported card types and densities.
The SDWP input pin to the MMC1 port is connected to a 2-pin header, J44. The default state has the pin
pulled high. Shorting the header pulls the pin low. The polarity of this input is programmable; thus, the
hardware does not define whether a high or low level indicates Write Protest is active or not.
The transient protection implemented at the SDCARD connector is the TPD6E001.
5.5 eMMC NAND Flash
The MMC2 port on the AM571x processor supports eMMC memory devices, since it has 8 data lines. The
eMMC footprint is compliant with the JEDEC/MMC standard. Boards have been assembled and
successfully tested with the Kingston EMMC16G-S100 and the Micron MTFC16GAKAECN-2M WT. These
are 16GB eMMC NAND Flash memories that are standard version 5.0 compliant.

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6 Ethernet Ports
The AM571x IDK EVM supports up to four 100Mb Industrial Ethernet ports attached to the PRU-ICSS
subsystems and up to two Gigabit (1000Mb) Ethernet ports connected to the integrated Ethernet switch.
The final number of available ports depends on the configuration selection:
• 4-port Ethernet mode: provides two 100Mb Industrial Ethernet ports and two Gigabit (1000Mb)
Ethernet ports.
• 6-port Ethernet mode: provides four 100Mb Industrial Ethernet ports and two Gigabit (1000Mb)
Ethernet ports.
Selection between these Ethernet modes is controlled by header J51. Installing a shunt on header J51
that shorts these pins together enables 4-port Ethernet mode. Removing the shunt from these pins
enables 6-port Ethernet mode. The LCD output is only available when 4-port Ethernet mode is selected.
6.1 100Mb Ethernet Ports on PRU-ICSS
The AM571x IDK EVM contains four 100Mb Ethernet ports that each connect to an industrial
PHY/Transceiver (TLK105L), which then connect to RJ45 metallic connectors, with integrated magnetics,
J3, J5, J6, and J8. These Ethernet transceivers are connected to the PRU1 and PRU2 subsystems within
the AM5718 processor. Table 4 shows the mapping from the PRU-ICSS ports to the RJ45 connectors.
The COL functionality on the MII interface is not used. The TLK105L contains a feature that must be
enabled via software that provides rapid link status on the COL pin. Therefore, this pin is connected to the
RXLINK input to the PRU-ICSS ports for this purpose.
Test headers J4 and J7 are available to support real-time code development. The signals contained are
available for simplified probing.
The reset for the transceivers is driven low coincident with the PORz reset to the AM5718 processor. The
reset for each transceiver can also be driven low individually by separate GPIO signals from the
processor. A 25-MHz clock is provided into each of the TLK105L industrial transceivers.
Table 4. PRU-ICSS Ethernet Ports
Connector PRU-ICSS Port MDIO Address Notes
J3 PRU1ETH0 0x0 on PRU1 Not available in all configuration selections. MII pins multiplexed with VOUT1
to the LCD bridge.
J5 PRU1ETH1 0x1 on PRU1 Not available in all configuration selections. MII pins multiplexed with VOUT1
to the LCD bridge.
J6 PRU2ETH0 0x0 on PRU2
J8 PRU2ETH1 0x1 on PRU2
6.2 Gigabit (1000Mb) Ethernet Ports
The AM571x IDK EVM contains two Gigabit (1000Mb) Ethernet PHY/Transceivers (KSZ9031RN)
interfaced to connectors J10 (RGMII0) and J12 (RGMII1). These Gigabit Ethernet transceivers are
connected over RGMII0 and RGMII1 to the Ethernet switch block within the AM5718 processor.
The resets for the transceivers are driven low coincident with the PORz reset to the AM5718 processor. A
25-MHz clock is provided into each of the KSZ9031RN Gigabit transceivers.

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7 USB Ports
The AM571x IDK EVM contains three USB ports. Two ports are attached to the USB peripherals USB1
and USB2 on the AM5718 processor. The third port provides both XDS100V2 JTAG emulation and UART
Console over the USB. This port simplifies the development environment for programmers using
computers that support this capability such as Windows®-based computers.
7.1 Processor USB Port 1
Processor port USB1 is implemented only as a USB host (master). It supports only the USB2.1 (high
speed and lower) data rates. The connector on the board, J23, is a USB2.1 Standard A-type connector.
The ESD devices implemented on this USB port are the TPD2EUSB30 for the DP and DM lines.
Since processor USB port 1 supports host mode, it has the capability to drive 5.0V power on the VBUS
pin. The TPS2065D load switch is controlled by the USB1_DRVVBUS pin for this purpose.
7.2 Processor USB Port 2
Processor port USB2 is implemented as either USB host (master) or USB device (slave). It supports only
the USB2.1 (high speed and lower) data rates. The connector on the board, J45, is a USB2.1 Micro-AB
connector. The ESD device implemented on this USB port is the TPD4S012.
Since processor USB port 2 supports host mode, it has the capability to drive 5.0V power on the VBUS
pin. The TPS2051 load switch is controlled by the USB2_DRVVBUS pin for this purpose.
The USB2.1 standard defines different ranges of capacitance for the VBUS pin depending on whether it is
host or device. Since this port can do either, the AM571x IDK EVM provides the capability to meet either
requirement. The VBUS pin from the connector contains a 4.7µF capacitor that is appropriate for device
mode operation. When operating in host mode, 2-pin header J50 can be shorted to add 150µF of
additional capacitance to the VBUS pin. The shunt for this header is shown on the schematic as M2. It is
not installed on units when shipped as we expect this port to primarily be used in device mode.
7.3 FTDI USB Port
The FTDI bridge device provides both XDS100V2 JTAG emulation and UART Console over the USB. The
connector on the board, J19, is a USB Micro-AB connector but it only operates in device (slave) mode
with the FTDI bridge device. The ESD device implemented on this USB port to the FTDI bridge is the
TPD2E001. Refer to Section 4.4 for more details on this functionality.
The FTDI USB device is implemented so that it operates from the VBUS power provided over the USB
cable. This allows the FTDI device to remain fully operational during an AM571x IDK EVM power cycle.
This in turn allows the console port to the PC to remain active to allow logging from the serial port
immediately as the AM5718 device boots. It also provides faster re-connect for the XDS100V2 JTAG
emulator.

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8 PCIe
The AM571x processors contain two lanes of peripheral component interconnect express (PCIe). These
can be implemented either as a single, dual-lane port or as two single-lane ports. The PCIe peripheral can
be configured to either be a Root Complex (master) or an Endpoint (slave). The AM571x IDK EVM
implements a single dual-lane port as a Root Complex. The AM571x IDK EVM terminates this dual-lane
port in a ×4 PCIe female connector that accepts standard PCIe Endpoint cards.
A 2-pin header, J49, is available to provide the 3V3_AUX power separate from the primary 3V3 supply.
This is needed for some cards and PCIe driver configurations. The shunt, shown on the schematic as M1,
should be installed when the board is received since 3V3_AUX will be needed in most cases. Please refer
to the documentation for the card being installed to determine whether this shunt should remain installed.
The PERSTn reset for the connector is driven low coincident with the PORz reset to the AM5718
processor. The PERSTn reset to the connector can also be driven low by a GPIO signal from the
processor. This reset can also be blocked by a GPIO signal from the processor.
A 100-MHz clock is provided separately to both the PCIe peripheral and to the PCIe connector. These
clocks are buffered outputs from the same low-jitter source.
The AM571x IDK EVM is compatible with standard PCIe plug-in cards but not fully compliant with the
PCIe CEM standard. It does not support hot-plug and also does not provide sufficient current on the 3.3V
and 12V pins for all plug-in cards. It is currently limited to about 0.5A on each supply.
9 Video Input and Output
The AM571x processor family supports industrial video capture and display in addition to its industrial
communications capabilities. The AM571x IDK EVM contains a camera header for attaching a module
containing a camera sensor as well as support for an LCD panel display and HDMI video output.
9.1 Camera
The AM571x IDK EVM supports a camera daughterboard that attaches to a 24-pin (2 × 24) header, J9.
The custom-designed camera module from TI, previously designed for the AM437x IDK EVM, mounts on
this header. This header is connected to VIN4B on the AM5718 processor.
The 2Mp camera board contains the Darling Industrial camera module (part number DC-OVBD420AH).
The camera module contains the OmniVision OV2659 camera sensor. Please contact OmniVision for the
latest documentation on this sensor.
9.2 HDMI
The AM571x IDK EVM supports an HDMI connector driven from the HDMI port on the AM5718 processor.
The connector on the board, J24, is an HDMI Standard A-type connector. It is implemented with the
TPD12S016 HDMI companion chip. This companion chip provides I2C level shifting buffers, 5V load
switch, and multi-channel ESD protection.
9.3 LCD
The AM571x IDK EVM is available with an optional LCD panel that also has a capacitive touch overlay.
The video output driven for the LCD panel from the AM5718 processor is on VOUT1. A MIPI bridge device
from Toshiba, TC358778, is implemented to convert from the 24-bit RGB presented on the VOUT1 pins to
serial MIPI RGB streams. The LCD panel is shipped with FPC cables that plug into J16 for the MIPI video
and into J17 for the touchscreen controller. Both the MIPI bridge device and the touchscreen controller are
connected to the IND_I2C chain from processor port I2C1.
The LCD output functionality is available only when the AM571x IDK EVM is configured for the 4-port
Ethernet mode. When the AM571x IDK EVM is configured for the 6-port Ethernet mode, the LCD output is
no longer available since the same pins on the AM5718 device are used for both functions.
NOTE: Installing a shunt on header J51 that shorts these pins together enables 4-port Ethernet
mode. Removing the shunt from these pins enables 6-port Ethernet mode.