Texas Instruments MSP430F663x User manual

PRODUCT PREVIEW
MSP430F663x
www.ti.com SLAS566 –OCTOBER 2009
MIXED SIGNAL MICROCONTROLLER
1FEATURES
• Low Supply-Voltage Range, 1.8 V to 3.6 V • Two Universal Serial Communication
Interfaces
• Ultralow Power Consumption – USCI_A0 and USCI_A1 Each Supporting
– Active Mode (AM): TBD μA/MHz – Enhanced UART supporting
– Standby Mode (LPM3 WDT Mode): TBD μAAuto-Baudrate Detection
– Off Mode (LPM4 RAM Retention): TBD μA– IrDA Encoder and Decoder
– Shutdown Mode (LPM5 RTC Mode): TBD μA– Synchronous SPI
– Shutdown Mode (LPM5): TBD μA– USCI_B0 and USCI_B1 Each Supporting
• Wake-Up From Standby Mode in Less Than – I2CTM
5μs– Synchronous SPI
• 16-Bit RISC Architecture, Extended Memory,
up to 20-MHz System Clock • Full-Speed Universal Serial Bus (USB)
• Flexible Power Management System – Integrated USB-PHY
– Fully Integrated LDO With Programmable – Integrated 3.3-V/1.8-V USB Power System
Regulated Core Supply Voltage – Integrated USB-PLL
– Supply Voltage Supervision, Monitoring, – Eight Input, Eight Output Endpoints
and Brownout • 12-Bit Analog-to-Digital (A/D) Converter With
• Unified Clock System Internal Shared Reference, Sample-and-Hold,
– FLL Control Loop for Frequency and Autoscan Feature
Stabilization • Dual 12-Bit Digital-to-Analog (D/A) Converters
– Low Power/Low Frequency Internal Clock With Synchronization
Source (VLO) • Comparator
– Low Frequency Trimmed Internal Reference • Integrated LCD Driver With Contrast Control
Source (REFO) for up to 160 Segments
– 32-kHz Crystals (XT1) • Hardware Multiplier Supporting 32-Bit
– High-Frequency Crystals Up to 32 MHz Operations
(XT2) • Flash Memory
• 16-Bit Timer TA0, Timer_A With Five – Serial Onboard Programming, No External
Capture/Compare Registers Programming Voltage Needed
• 16-Bit Timer TA1, Timer_A With Three – Enhanced Data Integrity
Capture/Compare Registers • Six-Channel Internal DMA
• 16-Bit Timer TA2, Timer_A With Three • Real-Time Clock Module With Supply Voltage
Capture/Compare Registers Backup Switch
• 16-Bit Timer TB0, Timer_B With Seven • Family Members are Summarized in Table 1
Capture/Compare Shadow Registers • For Complete Module Descriptions, See the
MSP430x5xx/MSP430x6xx Family User's Guide
(SLAU208)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the Copyright © 2009, Texas Instruments Incorporated
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
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PRODUCT PREVIEW
MSP430F663x
SLAS566 –OCTOBER 2009 www.ti.com
DESCRIPTION
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 5 μs.
The MSP430F663x series are microcontroller configurations with four 16-bit timers, a high performance 12-bit
analog-to-digital (A/D) converter, two universal serial communication interfaces (USCI), hardware multiplier,
DMA, real-time clock module with alarm capabilities, comparator, USB 2.0, and up to 74 I/O pins.
Typical applications for this device include analog and digital sensor systems, digital motor control, remote
controls, thermostats, digital timers, hand-held meters, etc.
Family members available are summarized in Table 1.
Table 1. Family Members
USCI
Flash SRAM Timer_A Timer_B ADC12_A DAC12_A Comp_B Package
Channel A: Channel B:
Device I/O
(KB) (KB) (1) (2) (3) (Ch) (Ch) (Ch) Type
UART/IrDA/ SPI/I2C
SPI
12 ext / 100 PZ,
MSP430F6638 256 16 + 2 5, 3, 3 7 2 2 2 12 74
4 int 113 ZQW
12 ext / 100 PZ,
MSP430F6637(4) 192 16 + 2 5, 3, 3 7 2 2 2 12 74
4 int 113 ZQW
12 ext / 100 PZ,
MSP430F6636(4) 128 16 + 2 5, 3, 3 7 2 2 2 12 74
4 int 113 ZQW
12 ext / 100 PZ,
MSP430F6635(4) 256 16 + 2 5, 3, 3 7 2 2 - 12 74
4 int 113 ZQW
12 ext / 100 PZ,
MSP430F6634(4) 192 16 + 2 5, 3, 3 7 2 2 - 12 74
4 int 113 ZQW
12 ext / 100 PZ,
MSP430F6633(4) 128 16 + 2 5, 3, 3 7 2 2 - 12 74
4 int 113 ZQW
100 PZ,
MSP430F6632(4) 256 16 + 2 5, 3, 3 7 2 2 - - 12 74 113 ZQW
100 PZ,
MSP430F6631(4) 192 16 + 2 5, 3, 3 7 2 2 - - 12 74 113 ZQW
100 PZ,
MSP430F6630(4) 128 16 + 2 5, 3, 3 7 2 2 - - 12 74 113 ZQW
(1) The additional 2 KB USB SRAM that is listed can be used as general purpose SRAM when USB is not in use.
(2) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(3) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(4) Product Preview
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PRODUCT PREVIEW
MSP430F663x
www.ti.com SLAS566 –OCTOBER 2009
Ordering Information(1)
PACKAGED DEVICES (2)
TAPLASTIC 100-PIN TQFP (PZ) PLASTIC 113-BALL BGA (ZQW)
MSP430F6638IPZ MSP430F6638IZQW(3)
MSP430F6637IPZ(3) MSP430F6637IZQW(3)
MSP430F6636IPZ(3) MSP430F6636IZQW(3)
MSP430F6635IPZ(3) MSP430F6635IZQW(3)
–40°C to 85°C MSP430F6634IPZ(3) MSP430F6634IZQW(3)
MSP430F6633IPZ(3) MSP430F6633IZQW(3)
MSP430F6632IPZ(3) MSP430F6632IZQW(3)
MSP430F6631IPZ(3) MSP430F6631IZQW(3)
MSP430F6630IPZ(3) MSP430F6630IZQW(3)
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/package.
(3) Product preview.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 3
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PRODUCT PREVIEW
Unified
Clock
System
256KB
192KB
128KB
Flash
MCLK
ACLK
SMCLK
I/O Ports
P1/P2
2×8 I/Os
Interrupt
Capability
PA
1×16 I/Os
CPUXV2
and
Working
Registers
EEM
(L: 8+2)
XIN XOUT
JTAG/
Interface/
Port PJ
SBW
PA PB PC PD
DMA
6 Channel
XT2IN
XT OUT2
Power
Management
LDO
SVM/
Brownout
SVS
SYS
Watchdog
P2 Port
Mapping
Controller
I/O Ports
P3/P4
2×8 I/Os
Interrupt
Capability
PB
1×16 I/Os
I/O Ports
P5/P6
2×8 I/Os
PC
1×16 I/Os
I/O Ports
P7/P8
1×6 I/Os
PD
1×14 I/Os
1×8 I/Os
I/O Ports
P9
1×8 I/Os
PE
1×8 I/Os
MPY32
TA0
Timer_A
5 CC
Registers
TA1 and
TA2
2 Timer_A
each with
3 CC
Registers
TB0
Timer_B
7 CC
Registers
RTC_B
Battery
Backup
System
CRC16
USCI0,1
Ax: UART,
IrDA, SPI
Bx: SPI, I2C
ADC12_A
200 KSPS
16 Channels
(12 ext/4 int)
Autoscan
12 Bit
DVCC DVSS AVCC AVSS
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x
RST/NMI
REF
Reference
1.5V, 2.0V,
2.5V
DAC12_A
12 bit
2 channels
voltage out
LCD_B
160
Segments
USB
Full-speed
Comp_B
EDI
Enhanced
Data
Integrity
PJ.x
16KB
RAM
+2KB RAM
USB Buffer
+8B Backup
RAM
Unified
Clock
System
256KB
192KB
128KB
Flash
16KB
RAM
+2KB RAM
USB Buffer
+8B Backup
RAM
MCLK
ACLK
SMCLK
I/O Ports
P1/P2
2×8 I/Os
Interrupt
Capability
PA
1×16 I/Os
CPUXV2
and
Working
Registers
EEM
(L: 8+2)
XIN XOUT
JTAG/
Interface/
Port PJ
SBW
PA PB PC PD
DMA
6 Channel
XT2IN
XT OUT2
Power
Management
LDO
SVM/
Brownout
SVS
SYS
Watchdog
P2 Port
Mapping
Controller
I/O Ports
P3/P4
2×8 I/Os
Interrupt
Capability
PB
1×16 I/Os
I/O Ports
P5/P6
2×8 I/Os
PC
1×16 I/Os
I/O Ports
P7/P8
1×6 I/Os
PD
1×14 I/Os
1×8 I/Os
I/O Ports
P9
1×8 I/Os
PE
1×8 I/Os
MPY32
TA0
Timer_A
5 CC
Registers
TA1 and
TA2
2 Timer_A
each with
3 CC
Registers
TB0
Timer_B
7 CC
Registers
CRC16
USCI0,1
Ax: UART,
IrDA, SPI
Bx: SPI, I2C
ADC12_A
200 KSPS
16 Channels
(12 ext/4 int)
Autoscan
12 Bit
DVCC DVSS AVCC AVSS
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x
RST/NMI
REF
Reference
1.5V, 2.0V,
2.5V
LCD_B
160
Segments
USB
Full-speed
Comp_B
EDI
Enhanced
Data
Integrity
PJ.x
RTC_B
Battery
Backup
System
MSP430F663x
SLAS566 –OCTOBER 2009 www.ti.com
Functional Block Diagram, MSP430F6638, MSP430F6637, MSP430F6636
Functional Block Diagram, MSP430F6635, MSP430F6634, MSP430F6633
4Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
DRAFT ONLY

PRODUCT PREVIEW
Unified
Clock
System
256KB
192KB
128KB
Flash
MCLK
ACLK
SMCLK
I/O Ports
P1/P2
2×8 I/Os
Interrupt
Capability
PA
1×16 I/Os
CPUXV2
and
Working
Registers
EEM
(L: 8+2)
XIN XOUT
JTAG/
Interface/
Port PJ
SBW
PA PB PC PD
DMA
6 Channel
XT2IN
XT OUT2
Power
Management
LDO
SVM/
Brownout
SVS
SYS
Watchdog
P2 Port
Mapping
Controller
I/O Ports
P3/P4
2×8 I/Os
Interrupt
Capability
PB
1×16 I/Os
I/O Ports
P5/P6
2×8 I/Os
PC
1×16 I/Os
I/O Ports
P7/P8
1×6 I/Os
PD
1×14 I/Os
1×8 I/Os
I/O Ports
P9
1×8 I/Os
PE
1×8 I/Os
MPY32
TA0
Timer_A
5 CC
Registers
TA1 and
TA2
2 Timer_A
each with
3 CC
Registers
TB0
Timer_B
7 CC
Registers
CRC16
USCI0,1
Ax: UART,
IrDA, SPI
Bx: SPI, I2C
DVCC DVSS AVCC AVSS
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x
RST/NMI
REF
Reference
1.5V, 2.0V,
2.5V
LCD_B
160
Segments
USB
Full-speed
Comp_B
EDI
Enhanced
Data
Integrity
PJ.x
RTC_B
Battery
Backup
System
16KB
RAM
+2KB RAM
USB Buffer
+8B Backup
RAM
MSP430F663x
www.ti.com SLAS566 –OCTOBER 2009
Functional Block Diagram, MSP430F6632, MSP430F6631, MSP430F6630
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 5
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PRODUCT PREVIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76 77 78 79 80
81
82
83 84 85 86 87 88 89 90 91 92 93 94 95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6/DAC0
P6.7/CB7/A7/DAC1
P7.4/CB8/A12
P7.5/CB9/A13
P7.6/CB10/A14/DAC0
P7.7/CB11/A15/DAC1
P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−
AVCC1
AVSS1
XIN
XOUT
DVCC1
DVSS1
VCORE
P5.2/R23
LCDCAP/R33
COM0
P5.3/COM1/S42
P9.7/S0
P9.6/S1
P9.5/S2
P9.4/S3
P9.3/S4
P9.2/S5
P9.1/S6
P9.0/S7
P8.7/S8
P8.6/UCB1SOMI/UCB1SCL/S9
P8.5/UCB1SIMO/UCB1SDA/S10
DVCC2
DVSS2
P2.0/P2MAP0
MSP430F6638
MSP430F6637
MSP430F6636
PZ PACKAGE
(TOP VIEW)
P6.3/CB3/A3
P6.2/CB2/A2
P6.1/CB1/A1
P6.0/CB0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK P7.3/XT2OUT
P7.2/XT2IN VBUS
VUSB PU.1/DM
PUR
PU.0/DP
VSSU V18
AVSS3
P1.3/TA0.2/S36
P1.4/TA0.3/S35
AVSS2
P5.6/ADC12CLK/DMAE0
P5.4/COM2/S41
P5.5/COM3/S40
P1.0/TA0CLK/ACLK/S39
P3.0/TA1CLK/CBOUT/S31
P3.1/TA1.0/S30
P3.2/TA1.1/S29
P1.6/TA0.1/S33
P1.7/TA0.2/S32
P1.1/TA0.0/S38
P1.2/TA0.1/S37
P1.5/TA0.4/S34
P3.3/TA1.2/S28
P3.4/TA2CLK/SMCLK/S27
P3.5/TA2.0/S26
P3.6/TA2.1/S25
P3.7/TA2.2/S24
P4.0/TB0.0/S23
P4.2/TB0.2/S21
P4.1/TB0.1/S22
P4.4/TB0.4/S19
P4.3/TB0.3/S20
P4.6/TB0.6/S17
P4.5/TB0.5/S18
P8.0/TB0CLK/S15
P4.7/TB0OUTH/SVMOUT/S16
P8.4 /S11/UCB1CLK/UCA1STE
VBAK
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6/R03
P2.7/P2MAP7/LCDREF/R13
DVCC3
DVSS3 VBAT
P5.7/RTCCLK
P8.1/UCB1STE/UCA1CLK/S14
P8.2/UCA1TXD/UCA1SIMO/S13
P8.3/UCA1RXD/UCA1SOMI/S12
MSP430F663x
SLAS566 –OCTOBER 2009 www.ti.com
Pin Designation, MSP430F6638IPZ, MSP430F6637IPZ, MSP430F6636IPZ
6Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
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PRODUCT PREVIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76 77 78 79 80
81
82
83 84 85 86 87 88 89 90 91 92 93 94 95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6
P6.7/CB7/A7
P7.4/CB8/A12
P7.5/CB9/A13
P7.6/CB10/A14
P7.7/CB11/A15
P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−
AVCC1
AVSS1
XIN
XOUT
DVCC1
DVSS1
VCORE
P5.2/R23
LCDCAP/R33
COM0
P5.3/COM1/S42
P9.7/S0
P9.6/S1
P9.5/S2
P9.4/S3
P9.3/S4
P9.2/S5
P9.1/S6
P9.0/S7
P8.7/S8
P8.6/UCB1SOMI/UCB1SCL/S9
P8.5/UCB1SIMO/UCB1SDA/S10
DVCC2
DVSS2
P2.0/P2MAP0
MSP430F6635
MSP430F6634
MSP430F6633
PZ PACKAGE
(TOP VIEW)
P6.3/CB3/A3
P6.2/CB2/A2
P6.1/CB1/A1
P6.0/CB0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK P7.3/XT2OUT
P7.2/XT2IN VBUS
VUSB PU.1/DM
PUR
PU.0/DP
VSSU V18
AVSS3
P1.3/TA0.2/S36
P1.4/TA0.3/S35
AVSS2
P5.6/ADC12CLK/DMAE0
P5.4/COM2/S41
P5.5/COM3/S40
P1.0/TA0CLK/ACLK/S39
P3.0/TA1CLK/CBOUT/S31
P3.1/TA1.0/S30
P3.2/TA1.1/S29
P1.6/TA0.1/S33
P1.7/TA0.2/S32
P1.1/TA0.0/S38
P1.2/TA0.1/S37
P1.5/TA0.4/S34
P3.3/TA1.2/S28
P3.4/TA2CLK/SMCLK/S27
P3.5/TA2.0/S26
P3.6/TA2.1/S25
P3.7/TA2.2/S24
P4.0/TB0.0/S23
P4.2/TB0.2/S21
P4.1/TB0.1/S22
P4.4/TB0.4/S19
P4.3/TB0.3/S20
P4.6/TB0.6/S17
P4.5/TB0.5/S18
P8.0/TB0CLK/S15
P4.7/TB0OUTH/SVMOUT/S16
P8.4 /S11/UCB1CLK/UCA1STE
VBAK
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6/R03
P2.7/P2MAP7/LCDREF/R13
DVCC3
DVSS3 VBAT
P5.7/RTCCLK
P8.1/UCB1STE/UCA1CLK/S14
P8.2/UCA1TXD/UCA1SIMO/S13
P8.3/UCA1RXD/UCA1SOMI/S12
MSP430F663x
www.ti.com SLAS566 –OCTOBER 2009
Pin Designation, MSP430F6635IPZ, MSP430F6634IPZ, MSP430F6633IPZ
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 7
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PRODUCT PREVIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76 77 78 79 80
81
82
83 84 85 86 87 88 89 90 91 92 93 94 95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P6.4/CB4
P6.5/CB5
P6.6/CB6
P6.7/CB7
P7.4/CB8
P7.5/CB9
P7.6/CB10
P7.7/CB11
P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−
AVCC1
AVSS1
XIN
XOUT
DVCC1
DVSS1
VCORE
P5.2/R23
LCDCAP/R33
COM0
P5.3/COM1/S42
P9.7/S0
P9.6/S1
P9.5/S2
P9.4/S3
P9.3/S4
P9.2/S5
P9.1/S6
P9.0/S7
P8.7/S8
P8.6/UCB1SOMI/UCB1SCL/S9
P8.5/UCB1SIMO/UCB1SDA/S10
DVCC2
DVSS2
P2.0/P2MAP0
MSP430F6632
MSP430F6631
MSP430F6630
PZ PACKAGE
(TOP VIEW)
P6.3/CB3
P6.2/CB2
P6.1/CB1
P6.0/CB0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK P7.3/XT2OUT
P7.2/XT2IN VBUS
VUSB PU.1/DM
PUR
PU.0/DP
VSSU V18
AVSS3
P1.3/TA0.2/S36
P1.4/TA0.3/S35
AVSS2
P5.6/DMAE0
P5.4/COM2/S41
P5.5/COM3/S40
P1.0/TA0CLK/ACLK/S39
P3.0/TA1CLK/CBOUT/S31
P3.1/TA1.0/S30
P3.2/TA1.1/S29
P1.6/TA0.1/S33
P1.7/TA0.2/S32
P1.1/TA0.0/S38
P1.2/TA0.1/S37
P1.5/TA0.4/S34
P3.3/TA1.2/S28
P3.4/TA2CLK/SMCLK/S27
P3.5/TA2.0/S26
P3.6/TA2.1/S25
P3.7/TA2.2/S24
P4.0/TB0.0/S23
P4.2/TB0.2/S21
P4.1/TB0.1/S22
P4.4/TB0.4/S19
P4.3/TB0.3/S20
P4.6/TB0.6/S17
P4.5/TB0.5/S18
P8.0/TB0CLK/S15
P4.7/TB0OUTH/SVMOUT/S16
P8.4 /S11/UCB1CLK/UCA1STE
VBAK
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6/R03
P2.7/P2MAP7/LCDREF/R13
DVCC3
DVSS3 VBAT
P5.7/RTCCLK
P8.1/UCB1STE/UCA1CLK/S14
P8.2/UCA1TXD/UCA1SIMO/S13
P8.3/UCA1RXD/UCA1SOMI/S12
MSP430F663x
SLAS566 –OCTOBER 2009 www.ti.com
Pin Designation, MSP430F6632IPZ, MSP430F6631IPZ, MSP430F6630IPZ
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A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12
C1 C2 C3 C11 C12
D1 D2 D4 D5 D6 D7 D8 D9 D11 D12
E1 E2 E4 E5 E6 E7 E8 E9 E11 E12
F1 F2 F4 F5 F8 F9 F11 F12
G1 G2 G4 G5 G8 G9 G11 G12
J1 J2 J4 J5 J6 J7 J8 J9 J11 J12
H1 H2 H4 H5 H6 H7 H8 H9 H11 H12
K1 K2 K11 K12
L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12
M1 M2 M3 M5 M6 M7 M8 M9 M10 M11 M12
M4
ZQW PACKAGE
(TOP VIEW)
MSP430F663x
www.ti.com SLAS566 –OCTOBER 2009
Pin Designation, MSP430F6638IZQW, MSP430F6637IZQW, MSP430F6636IZQW,
MSP430F6635IZQW, MSP430F6634IZQW, MSP430F6633IZQW, MSP430F6632IZQW,
MSP430F6631IZQW, MSP430F6630IZQW
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MSP430F663x
SLAS566 –OCTOBER 2009 www.ti.com
Terminal Functions
TERMINAL I/O
NO. DESCRIPTION
(1)
NAME PZ ZQW
General-purpose digital I/O
P6.4/CB4/A4 1 A1 I/O Comparator_B input CB4
Analog input A4 – ADC (not available on '6632, '6631, '6630 devices)
General-purpose digital I/O
P6.5/CB5/A5 2 B2 I/O Comparator_B input CB5
Analog input A5 – ADC (not available on '6632, '6631, '6630 devices)
General-purpose digital I/O
Comparator_B input CB6
P6.6/CB6/A6/DAC0 3 B1 I/O Analog input A6 – ADC (not available on '6632, '6631, '6630 devices)
DAC12.0 output (not available on '6635, '6634, '6633, '6632, '6631, '6630 devices)
General-purpose digital I/O
Comparator_B input CB7
P6.7/CB7/A7/DAC1 4 C2 I/O Analog input A7 – ADC (not available on '6632, '6631, '6630 devices)
DAC12.1 output (not available on '6635, '6634, '6633, '6632, '6631, '6630 devices)
General-purpose digital I/O
P7.4/CB8/A12 5 C1 I/O Comparator_B input CB8
Analog input A12 –ADC (not available on '6632, '6631, '6630 devices)
General-purpose digital I/O
P7.5/CB9/A13 6 C3 I/O Comparator_B input CB9
Analog input A13 – ADC (not available on '6632, '6631, '6630 devices)
General-purpose digital I/O
Comparator_B input CB10
P7.6/CB10/A14/DAC0 7 D2 I/O Analog input A14 – ADC (not available on '6632, '6631, '6630 devices)
DAC12.0 output (not available on '6635, '6634, '6633, '6632, '6631, '6630 devices)
General-purpose digital I/O
Comparator_B input CB11
P7.7/CB11/A15/DAC1 8 D1 I/O Analog input A15 – ADC (not available on '6632, '6631, '6630 devices)
DAC12.1 output (not available on '6635, '6634, '6633, '6632, '6631, '6630 devices)
General-purpose digital I/O
P5.0/VREF+/VeREF+ 9 D4 I/O Output of reference voltage to the ADC
Input for an external reference voltage to the ADC
General-purpose digital I/O
P5.1/VREF-/VeREF- 10 E4 I/O Negative terminal for the ADC's reference voltage for both sources, the internal
reference voltage, or an external applied reference voltage
E1,
AVCC1 11 Analog power supply
E2
AVSS1 12 F2 Analog ground supply
XIN 13 F1 I Input terminal for crystal oscillator XT1
XOUT 14 G1 O Output terminal of crystal oscillator XT1
AVSS2 15 G2 Analog ground supply
General-purpose digital I/O
P5.6/ADC12CLK/DMAE0 16 H1 I/O Conversion clock output ADC (not available on '6632, '6631, '6630 devices)
DMA external trigger input
General-purpose digital I/O with port interrupt and map-able secondary function
P2.0/P2MAP0 17 G4 I/O Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock input/output
General-purpose digital I/O with port interrupt and map-able secondary function
P2.1/P2MAP1 18 H2 I/O Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I2C data
General-purpose digital I/O with port interrupt and map-able secondary function
P2.2/P2MAP2 19 J1 I/O Default mapping: USCI_B0 SPI slave out/master in; USCI_B0 I2C clock
General-purpose digital I/O with port interrupt and map-able secondary function
P2.3/P2MAP3 20 H4 I/O Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable
General-purpose digital I/O with port interrupt and map-able secondary function
P2.4/P2MAP4 21 J2 I/O Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in/master out
General-purpose digital I/O with port interrupt and map-able secondary function
P2.5/P2MAP5 22 K1 I/O Default mapping: USCI_A0 UART receive data; USCI_A0 slave out/master in
(1) I = input, O = output, N/A = not available on this package offering
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MSP430F663x
www.ti.com SLAS566 –OCTOBER 2009
Terminal Functions (continued)
TERMINAL I/O
NO. DESCRIPTION
(1)
NAME PZ ZQW
General-purpose digital I/O with port interrupt and map-able secondary function
P2.6/P2MAP6/R03 23 K2 I/O Default mapping: no secondary function
Input/output port of lowest analog LCD voltage (V5)
General-purpose digital I/O with port interrupt and map-able secondary function
Default mapping: no secondary function
P2.7/P2MAP7/LCDREF/R13 24 L2 I/O External reference voltage input for regulated LCD voltage
Input/output port of third most positive analog LCD voltage (V3 or V4)
DVCC1 25 L1 Digital power supply
DVSS1 26 M1 Digital ground supply
VCORE(2) 27 M2 Regulated core power supply (internal usage only, no external current loading)
General-purpose digital I/O
P5.2/R23 28 L3 I/O Input/output port of second most positive analog LCD voltage (V2)
LCDCAP/R33 29 M3 I/O Input/output port of most positive analog LCD voltage (V1)
COM0 30 J4 O LCD common output COM0 for LCD backplane
General-purpose digital I/O
P5.3/COM1/S42 31 L4 I/O LCD common output COM1 for LCD backplane
LCD segment output S42
General-purpose digital I/O
P5.4/COM2/S41 32 M4 I/O LCD common output COM2 for LCD backplane
LCD segment output S41
General-purpose digital I/O
P5.5/COM3/S40 33 J5 I/O LCD common output COM3 for LCD backplane
LCD segment output S40
General-purpose digital I/O with port interrupt
Timer TA0 clock signal TACLK input
P1.0/TA0CLK/ACLK/S39 34 L5 I/O ACLK output (divided by 1, 2, 4, or 8)
LCD segment output S39
General-purpose digital I/O with port interrupt
Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output
P1.1/TA0.0/S38 35 M5 I/O BSL transmit output
LCD segment output S38
General-purpose digital I/O with port interrupt
Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output
P1.2/TA0.1/S37 36 J6 I/O BSL receive input
LCD segment output S37
General-purpose digital I/O with port interrupt
P1.3/TA0.2/S36 37 H6 I/O Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output
LCD segment output S36
General-purpose digital I/O with port interrupt
P1.4/TA0.3/S35 38 M6 I/O Timer TA0 CCR3 capture: CCI3A input compare: Out3 output
LCD segment output S35
General-purpose digital I/O with port interrupt
P1.5/TA0.4/S34 39 L6 I/O Timer TA0 CCR4 capture: CCI4A input, compare: Out4 output
LCD segment output S34
General-purpose digital I/O with port interrupt
P1.6/TA0.1/S33 40 J7 I/O Timer TA0 CCR1 capture: CCI1B input, compare: Out1 output
LCD segment output S33
General-purpose digital I/O with port interrupt
P1.7/TA0.2/S32 41 M7 I/O Timer TA0 CCR2 capture: CCI2B input, compare: Out2 output
LCD segment output S32
General-purpose digital I/O with port interrupt
Timer TA1 clock input
P3.0/TA1CLK/CBOUT/S31 42 L7 I/O Comparator_B output
LCD segment output S31
(2) VCORE is for internal usage only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.
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MSP430F663x
SLAS566 –OCTOBER 2009 www.ti.com
Terminal Functions (continued)
TERMINAL I/O
NO. DESCRIPTION
(1)
NAME PZ ZQW
General-purpose digital I/O with port interrupt
P3.1/TA1.0/S30 43 H7 I/O Timer TA1 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
LCD segment output S30
General-purpose digital I/O with port interrupt
P3.2/TA1.1/S29 44 M8 I/O Timer TA1 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
LCD segment output S29
General-purpose digital I/O with port interrupt
P3.3/TA1.2/S28 45 L8 I/O Timer TA1 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
LCD segment output S28
General-purpose digital I/O with port interrupt
Timer TA2 clock input
P3.4/TA2CLK/SMCLK/S27 46 J8 I/O SMCLK output
LCD segment output S27
General-purpose digital I/O with port interrupt
P3.5/TA2.0/S26 47 M9 I/O Timer TA2 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
LCD segment output S26
General-purpose digital I/O with port interrupt
P3.6/TA2.1/S25 48 L9 I/O Timer TA2 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
LCD segment output S25
General-purpose digital I/O with port interrupt
P3.7/TA2.2/S24 49 M10 I/O Timer TA2 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
LCD segment output S24
General-purpose digital I/O with port interrupt
P4.0/TB0.0/S23 50 J9 I/O Timer TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
LCD segment output S23
General-purpose digital I/O with port interrupt
P4.1/TB0.1/S22 51 M11 I/O Timer TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
LCD segment output S22
General-purpose digital I/O with port interrupt
P4.2/TB0.2/S21 52 L10 I/O Timer TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
LCD segment output S21
General-purpose digital I/O with port interrupt
P4.3/TB0.3/S20 53 M12 I/O Timer TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output
LCD segment output S20
General-purpose digital I/O with port interrupt
P4.4/TB0.4/S19 54 L12 I/O Timer TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output
LCD segment output S19
General-purpose digital I/O with port interrupt
P4.5/TB0.5/S18 55 L11 I/O Timer TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output
LCD segment output S18
General-purpose digital I/O with port interrupt
P4.6/TB0.6/S17 56 K11 I/O Timer TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output
LCD segment output S17
General-purpose digital I/O with port interrupt
Timer TB0: Switch all PWM outputs high impedance
P4.7/TB0OUTH/SVMOUT/S16 57 K12 I/O SVM output
LCD segment output S16
General-purpose digital I/O
P8.0/TB0CLK/S15 58 J11 I/O Timer TB0 clock input
LCD segment output S15
General-purpose digital I/O
P8.1/UCB1STE/UCA1CLK/S14 59 J12 I/O USCI_B1 SPI slave transmit enable; USCI_A1 clock input/output
LCD segment output S14
General-purpose digital I/O
P8.2/UCA1TXD/UCA1SIMO/S13 60 H11 I/O USCI_A1 UART transmit data; USCI_A1 SPI slave in/master out
LCD segment output S13
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MSP430F663x
www.ti.com SLAS566 –OCTOBER 2009
Terminal Functions (continued)
TERMINAL I/O
NO. DESCRIPTION
(1)
NAME PZ ZQW
General-purpose digital I/O
P8.3/UCA1RXD/UCA1SOMI/S12 61 H12 I/O USCI_A1 UART receive data; USCI_A1 SPI slave out/master in
LCD segment output S12
General-purpose digital I/O
P8.4/UCB1CLK/UCA1STE/S11 62 G11 I/O USCI_B1 clock input/output; USCI_A1 SPI slave transmit enable
LCD segment output S11
DVSS2 63 G12 Digital ground supply
DVCC2 64 F12 Digital power supply
General-purpose digital I/O
P8.5/UCB1SIMO/UCB1SDA/S10 65 F11 I/O USCI_B1 SPI slave in/master out; USCI_B1 I2C data
LCD segment output S10
General-purpose digital I/O
P8.6/UCB1SOMI/UCB1SCL/S9 66 G9 I/O USCI_B1 SPI slave out/master in; USCI_B1 I2C clock
LCD segment output S9
General-purpose digital I/O
P8.7/S8 67 E12 I/O LCD segment output S8
General-purpose digital I/O
P9.0/S7 68 E11 I/O LCD segment output S7
General-purpose digital I/O
P9.1/S6 69 F9 I/O LCD segment output S6
General-purpose digital I/O
P9.2/S5 70 D12 I/O LCD segment output S5
General-purpose digital I/O
P9.3/S4 71 D11 I/O LCD segment output S4
General-purpose digital I/O
P9.4/S3 72 E9 I/O LCD segment output S3
General-purpose digital I/O
P9.5/S2 73 C12 I/O LCD segment output S2
General-purpose digital I/O
P9.6/S1 74 C11 I/O LCD segment output S1
General-purpose digital I/O
P9.7/S0 75 D9 I/O LCD segment output S0
B11
VSSU 76 and USB PHY ground supply
B12 General-purpose digital I/O - controlled by USB control register
PU.0/DP 77 A12 I/O USB data terminal DP
PUR 78 B10 I/O USB pull-up resistor pin (open drain)
General-purpose digital I/O - controlled by USB control register
PU.1/DM 79 A11 I/O USB data terminal DM
VBUS 80 A10 USB LDO input (connect to USB power source)
VUSB 81 A9 USB LDO output
V18 82 B9 USB regulated power (internal usage only, no external current loading)
AVSS3 83 A8 Analog ground supply
General-purpose digital I/O
P7.2/XT2IN 84 B8 I/O Input terminal for crystal oscillator XT2
General-purpose digital I/O
P7.3/XT2OUT 85 B7 I/O Output terminal of crystal oscillator XT2
VBAK 86 A7 Chip internal backup subsystem
VBAT 87 D8 Backup supply voltage
General-purpose digital I/O
P5.7/RTCCLK 88 D7 I/O RTCCLK output
DVCC3 89 A6 Digital power supply
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MSP430F663x
SLAS566 –OCTOBER 2009 www.ti.com
Terminal Functions (continued)
TERMINAL I/O
NO. DESCRIPTION
(1)
NAME PZ ZQW
DVSS3 90 A5 Digital ground supply
Test mode pin – select digital I/O on JTAG pins
TEST/SBWTCK 91 B6 I Spy-bi-wire input clock
General-purpose digital I/O
PJ.0/TDO 92 B5 I/O Test data output port
General-purpose digital I/O
PJ.1/TDI/TCLK 93 A4 I/O Test data input or test clock input
General-purpose digital I/O
PJ.2/TMS 94 E7 I/O Test mode select
General-purpose digital I/O
PJ.3/TCK 95 D6 I/O Test clock
Reset input active low
RST/NMI/SBWTDIO 96 A3 I/O Non-maskable interrupt input
Spy-bi-wire data input/output
General-purpose digital I/O
P6.0/CB0/A0 97 B4 I/O Comparator_B input CB0
Analog input A0 – ADC (not available on '6632, '6631, '6630 devices)
General-purpose digital I/O
P6.1/CB1/A1 98 B3 I/O Comparator_B input CB1
Analog input A1 – ADC (not available on '6632, '6631, '6630 devices)
General-purpose digital I/O
P6.2/CB2/A2 99 A2 I/O Comparator_B input CB2
Analog input A2 – ADC (not available on '6632, '6631, '6630 devices)
General-purpose digital I/O
P6.3/CB3/A3 100 D5 I/O Comparator_B input CB3
Analog input A3 – ADC (not available on '6632, '6631, '6630 devices)
E5
E6
E8
F4
F5 Reserved BGA package balls. It is recommended to connect to ground
Reserved N/A F8 (DVSS/AVSS).
G5
G8
H5
H8
H9
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Program Counter PC/R0
Stack Pointer SP/R1
Status Register SR/CG1/R2
Constant Generator CG2/R3
General-Purpose Register R4
General-Purpose Register R5
General-Purpose Register R6
General-Purpose Register R7
General-Purpose Register R8
General-Purpose Register R9
General-Purpose Register R10
General-Purpose Register R11
General-Purpose Register R12
General-Purpose Register R13
General-Purpose Register R15
General-Purpose Register R14
MSP430F663x
www.ti.com SLAS566 –OCTOBER 2009
SHORT-FORM DESCRIPTION
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The
register-to-register operation execution time is one
cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
Instruction Set
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data. Table 2 shows examples of the three
types of instruction formats; the address modes are
listed in Table 3.
Table 2. Instruction Word Formats
Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 →R5
Single operands, destination only e.g., CALL R8 PC →(TOS), R8 →PC
Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0
Table 3. Address Mode Descriptions
ADDRESS MODE S (1) D(1) SYNTAX EXAMPLE OPERATION
Register + + MOV Rs,Rd MOV R10,R11 R10 →R11
Indexed + + MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) →M(6+R6)
Symbolic (PC relative) + + MOV EDE,TONI M(EDE) →M(TONI)
Absolute + + MOV &MEM, &TCDAT M(MEM) →M(TCDAT)
Indirect + MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) →M(Tab+R6)
M(R10) →R11
Indirect auto-increment + MOV @Rn+,Rm MOV @R10+,R11 R10 + 2 →R10
Immediate + MOV #X,TONI MOV #45,TONI #45 →M(TONI)
(1) S = source, D = destination
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MSP430F663x
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Operating Modes
The MSP430 has one active mode and six software selectable low-power modes of operation. An interrupt event
can wake up the device from any of the five low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following seven operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc generator remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc generator is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc generator is disabled
– Crystal oscillator is stopped
– Complete data retention
• Low-power mode 5 (LPM5)
– Internal regulator disabled
– No data retention
– optional RTC clocked by low-frequency oscillator
– Wakeup from RST/NMI, RTC_B, P1, P2, P3, and P4
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Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 4. Interrupt Sources, Flags, and Vectors of MSP430F663x Configurations
SYSTEM WORD
INTERRUPT SOURCE INTERRUPT FLAG PRIORITY
INTERRUPT ADDRESS
System Reset
Power-Up, External Reset
Watchdog Timeout, Key Violation WDTIFG, KEYV (SYSRSTIV)(1) (2) Reset 0FFFEh 63, highest
Flash Memory Key Violation
EDI Parity Error
System NMI SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
PMM VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, (Non)maskable 0FFFCh 62
Vacant Memory Access JMBOUTIFG (SYSSNIV)(1)
JTAG Mailbox
User NMI
NMI NMIIFG, OFIFG, ACCVIFG, BUSIFG (Non)maskable 0FFFAh 61
Oscillator Fault (SYSUNIV)(1) (2)
Flash Memory Access Violation
Comp_B Comparator B interrupt flags (CBIV)(1) (3) Maskable 0FFF8h 60
Timer TB0 TB0CCR0 CCIFG0 (3) Maskable 0FFF6h 59
TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,
Timer TB0 Maskable 0FFF4h 58
TB0IFG (TBIV)(1) (3)
Watchdog Interval Timer Mode WDTIFG Maskable 0FFF2h 57
USCI_A0 Receive/Transmit UCA0RXIFG, UCA0TXIFG (UCA0IV)(1) (3) Maskable 0FFF0h 56
USCI_B0 Receive/Transmit UCB0RXIFG, UCB0TXIFG (UCAB0IV)(1) (3) Maskable 0FFEEh 55
ADC12_A(4) ADC12IFG0 to ADC12IFG15 (ADC12IV)(1) (3) Maskable 0FFECh 54
Timer TA0 TA0CCR0 CCIFG0(3) Maskable 0FFEAh 53
TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
Timer TA0 Maskable 0FFE8h 52
TA0IFG (TA0IV)(1) (3)
USB_UBM USB interrupts (USBIV)(1) (3) Maskable 0FFE6h 51
DMA0IFG, DMA1IFG, DMA2IFG, DMA3IFG,
DMA Maskable 0FFE4h 50
DMA4IFG, DMA5IFG (DMAIV)(1) (3)
Timer TA1 TA1CCR0 CCIFG0(3) Maskable 0FFE2h 49
TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
Timer TA1 Maskable 0FFE0h 48
TA1IFG (TA1IV)(1) (3)
I/O Port P1 P1IFG.0 to P1IFG.7 (P1IV)(1) (3) Maskable 0FFDEh 47
USCI_A1 Receive/Transmit UCA1RXIFG, UCA1TXIFG (UCA1IV)(1) (3) Maskable 0FFDCh 46
USCI_B1 Receive/Transmit UCB1RXIFG, UCB1TXIFG (UCB1IV)(1) (3) Maskable 0FFDAh 45
I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV)(1) (3) Maskable 0FFD8h 44
LCD_B LCD_B Interrupt Flags (LCDBIV)(1) Maskable 0FFD6h 43
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RTC_B Maskable 0FFD4h 42
RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV)(1) (3)
DAC12_A(5) DAC12_0IFG, DAC12_1IFG(1) (3) Maskable 0FFD2h 41
Timer TA2 TA2CCR0 CCIFG2(3) Maskable 0FFD0h 40
TA2CCR1 CCIFG1 to TA2CCR2,
Timer TA2 Maskable 0FFCEh 39
TA2IFG (TA2IV)(1) (3)
I/O Port P3 P3IFG.0 to P3IFG.7 (P3IV)(1) (3) Maskable 0FFCCh 38
I/O Port P4 P4IFG.0 to P4IFG.7 (P4IV)(1) (3) Maskable 0FFCAh 37
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(3) Interrupt flags are located in the module.
(4) Only on devices with peripheral module ADC12_A, otherwise reserved.
(5) Only on devices with peripheral module DAC12_A, otherwise reserved.
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Table 4. Interrupt Sources, Flags, and Vectors of MSP430F663x Configurations (continued)
SYSTEM WORD
INTERRUPT SOURCE INTERRUPT FLAG PRIORITY
INTERRUPT ADDRESS
0FFC8h 36
Reserved Reserved(6) ⋮ ⋮
0FF80h 0, lowest
(6) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatability with other devices, it is recommended to reserve these locations.
Memory Organization
Table 5. Memory Organization(1)
MSP430F6636 MSP430F6637 MSP430F6638
MSP430F6633 MSP430F6634 MSP430F6635
MSP430F6630 MSP430F6631 MSP430F6632
Memory (flash) Total Size 128KB 192KB 256KB
Main: interrupt vector 00FFFFh–00FF80h 00FFFFh–00FF80h 00FFFFh–00FF80h
Bank 3 N/A N/A 64 KB
047FFF-038000h
Bank 2 N/A 64 KB 64 KB
037FFF-028000h 037FFF-028000h
Main: code memory Bank 1 64 KB 64 KB 64 KB
027FFF-018000h 027FFF-018000h 027FFF-018000h
Bank 0 64 KB 64 KB 64 KB
017FFF-008000h 017FFF-008000h 017FFF-008000h
EDI support software Total Size 4KB 4KB 4KB
(ROM) 007FFFh-007000h 007FFFh-007000h 007FFFh-007000h
Sector 3 4 KB 4 KB 4 KB
0063FFh–005400h 0063FFh–005400h 0063FFh–005400h
Sector 2 4 KB 4 KB 4 KB
0053FFh–004400h 0053FFh–004400h 0053FFh–004400h
RAM Sector 1 4 KB 4 KB 4 KB
0043FFh–003400h 0043FFh–003400h 0043FFh–003400h
Sector 0 4 KB 4 KB 4 KB
0033FFh–002400h 0033FFh–002400h 0033FFh–002400h
Size 2KB 2KB 2KB
USB RAM(2) RAM 0023FFh-001C00h 0023FFh-001C00h 0023FFh-001C00h
Info A 128 B 128 B 128 B
0019FFh–001980h 0019FFh–001980h 0019FFh–001980h
Info B 128 B 128 B 128 B
00197Fh–001900h 00197Fh–001900h 00197Fh–001900h
Information memory
(flash) Info C 128 B 128 B 128 B
0018FFh–001880h 0018FFh–001880h 0018FFh–001880h
Info D 128 B 128 B 128 B
00187Fh–001800h 00187Fh–001800h 00187Fh–001800h
BSL 3 512 B 512 B 512 B
0017FFh–001600h 0017FFh–001600h 0017FFh–001600h
BSL 2 512 B 512 B 512 B
0015FFh–001400h 0015FFh–001400h 0015FFh–001400h
Bootstrap loader (BSL)
memory (flash) BSL 1 512 B 512 B 512 B
0013FFh–001200h 0013FFh–001200h 0013FFh–001200h
BSL 0 512 B 512 B 512 B
0011FFh–001000h 0011FFh–001000h 0011FFh–001000h
Size 4KB 4KB 4KB
Peripherals 000FFFh–000000h 000FFFh–000000h 000FFFh–000000h
(1) N/A = Not available.
(2) USB RAM can be used as general purpose RAM when not used for USB operation.
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Bootstrap Loader (BSL)
The BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the
device memory via the BSL is protected by user-defined password. For complete description of the features of
the BSL and its implementation, see the MSP430 Memory Programming User's Guide, TI literature number
SLAU265.
Table 6. BSL Functions
BSL FUNCTION DEVICE OUTPUT SIGNAL
Data transmit P1.1
Data receive P1.2
Flash Memory
The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the
flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also
called information memory.
• Segment A can be locked separately.
Enhanced Data Integrity (EDI)
The EDI feature provides additional functionality over the regular MSP430 flash memory controller. The main
purpose of the EDI function is gaining higher reliability of flash content and overall system integrity in harsh
environments and application areas requiring this feature. The additional level of security is reached by
caluclating more dimensional checksums.
The on-chip EDI support software allows easily to use the different EDI features. The implementation cover the
following functionality:
• Level #0
– User-defined or auto configuration of memory
– Error patching of up to four addresses (4 Error Cache entries)
– Handling of detected errors in an error list stored in RAM or flash
– Restart on error
• Level #1:
– All functionality of level #0 implemenation
– Recover on error
– User-defined error handling
For Complete EDI Description, See the MSP430 On-Chip EDI Support Software User's Guide (SLAUxxx)
RAM Memory
The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,
however all data is lost. Features of the RAM memory include:
• RAM memory has n sectors. The size of a sector can be found in the Memory Organization section.
• Each sector 0 to n can be complete disabled, however data retention is lost.
• Each sector 0 to n automatically enters low power retention mode when possible.
• For Devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.
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Backup RAM Memory
The Backup RAM provides a limited number of bytes of RAM that are retained during LPM5 and during operation
from a backup supply in case the Battery Backup System module is implemented.
There are 8 bytes of Backup RAM available on MSP430F663x. It can be wordwise accessed via the control
registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.
Peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using all
instructions. For complete module descriptions, see the MSP430x5xx/MSP430x6xx Family User's Guide,
literature number SLAU 208.
Digital I/O
There are up to nine 8-bit I/O ports implemented: P1 through P9 are complete and port PJ contains four
individual I/O ports.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Programmable drive strength on all ports.
• Edge-selectable interrupt input capability for all the eight bits of ports P1, P2, P3, and P4.
• Read/write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1 through P9) or word-wise in pairs (PA through PD).
Port Mapping Controller
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P2.
Table 7. Port Mapping, Mnemonics and Functions
VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
0 PM_NONE None DVSS
PM_CBOUT - Comparator_B output
1PM_TB0CLK Timer TB0 clock input -
PM_ADC12CLK - ADC12CLK
2PM_DMAE0 DMAE0 Input -
PM_SVMOUT - SVM output
3Timer TB0 high impedance input
PM_TB0OUTH -
TB0OUTH
4 PM_TB0CCR0B Timer TB0 CCR0 capture input CCI0B Timer TB0: TB0.0 compare output Out0
5 PM_TB0CCR1B Timer TB0 CCR1 capture input CCI1B Timer TB0: TB0.1 compare output Out1
6 PM_TB0CCR2B Timer TB0 CCR2 capture input CCI2B Timer TB0: TB0.2 compare output Out2
7 PM_TB0CCR3B Timer TB0 CCR3 capture input CCI3B Timer TB0: TB0.3 compare output Out3
8 PM_TB0CCR4B Timer TB0 CCR4 capture input CCI4B Timer TB0: TB0.4 compare output Out4
9 PM_TB0CCR5B Timer TB0 CCR5 capture input CCI5B Timer TB0: TB0.5 compare output Out5
10 PM_TB0CCR6B Timer TB0 CCR6 capture input CCI6B Timer TB0: TB0.6 compare output Out6
PM_UCA0RXD USCI_A0 UART RXD (Direction controlled by USCI - input)
11 PM_UCA0SOMI USCI_A0 SPI slave out master in (direction controlled by USCI)
PM_UCA0TXD USCI_A0 UART TXD (Direction controlled by USCI - output)
12 PM_UCA0SIMO USCI_A0 SPI slave in master out (direction controlled by USCI)
PM_UCA0CLK USCI_A0 clock input/output (direction controlled by USCI)
13 PM_UCB0STE USCI_B0 SPI slave transmit enable (direction controlled by USCI - input)
PM_UCB0SOMI USCI_B0 SPI slave out master in (direction controlled by USCI)
14 PM_UCB0SCL USCI_B0 I2C clock (open drain and direction controlled by USCI)
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