Texas Instruments MSP430G2231 User manual

Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
MSP430G2231-Q1
SLAS787B –NOVEMBER 2011–REVISED MARCH 2014
MSP430G2231 Automotive Mixed-Signal Microcontroller
1 Features 2 Applications
1• Qualified for Automotive Applications • Low-Cost Sensor Systems
• Low Supply-Voltage Range: 1.8 V to 3.6 V 3 Description
• Ultra-Low-Power Consumption The Texas Instruments MSP430™ family of ultra-low-
– Active Mode: 220 µA at 1 MHz, 2.2 V power microcontrollers consists of several devices
– Standby Mode: 0.5 µA featuring different sets of peripherals targeted for
various applications. The architecture, combined with
– Off Mode (RAM Retention): 0.1 µA five low-power modes, is optimized to achieve
• Five Power-Saving Modes extended battery life in portable measurement
• Ultra-Fast Wakeup From Standby Mode in Less applications. The device features a powerful 16-bit
Than 1 µs RISC CPU, 16-bit registers, and constant generators
that contribute to maximum code efficiency. The
• 16-Bit RISC Architecture, 62.5-ns Instruction digitally controlled oscillator (DCO) allows wake-up
Cycle Time from low-power modes to active mode in less than
• Basic Clock Module Configurations 1 µs.
– Internal Frequencies up to 16 MHz With One The MSP430G2231 devices are ultra-low-power
Calibrated Frequency mixed signal microcontrollers with a built-in 16-bit
– Internal Very Low Power Low-Frequency (LF) timer and ten I/O pins. The MSP430G2231 devices
Oscillator have a 10-bit A/D converter and built-in
communication capability using synchronous
– 32-kHz Crystal protocols (SPI or I2C). For configuration details, see
– External Digital Clock Source Table 1.
• 16-Bit Timer_A With Two Capture/Compare Typical applications include low-cost sensor systems
Registers that capture analog signals, convert them to digital
• Universal Serial Interface (USI) Supports SPI and values, and then process the data for display or for
I2Ctransmission to a host system.
• Brownout Detector Device Information(1)
• 10-Bit 200-ksps Analog-to-Digital Converter (ADC) PACKAGE
With Internal Reference, Sample-and-Hold, and ORDER NUMBER BODY SIZE
(PIN)
Autoscan MSP430G2231IRSARQ1 RSA (16) 4 mm x 4 mm
• Serial Onboard Programming, MSP430G2231IPW4RQ1 PW (14) 5 mm x 4.4 mm
No External Programming Voltage Needed,
Programmable Code Protection by Security Fuse
• On-Chip Emulation Logic With Spy-Bi-Wire
Interface
• For Family Members Details, See Device
Characteristics
• Available Packages
– 14-Pin Plastic Small-Outline Thin Package
(TSSOP) (PW)
– 16-Pin QFN Package (RSA) (1) For the most current part, package, and ordering information,
• For Complete Module Descriptions, See the see the Package Option Addendum at the end of this
MSP430x2xx Family User’s Guide (SLAU144)document, or see the TI web site at www.ti.com.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

Clock
System
Brownout
Protection
RST/NMI
DVCC DVSS
MCLK
Watchdog
WDT+
15-Bit
Timer0_A2
2 CC
Registers
16-MHz
CPU
incl. 16
Registers
Emulation
2BP
JTAG
Interface
SMCLK
ACLK
MDB
MAB
Port P1
8 I/O
Interrupt
capability
pullup/down
resistors
P1.x
8
Spy-Bi-
Wire
XIN XOUT
RAM
128B
Flash
2KB
ADC
10-Bit
8 Ch.
Autoscan
1 ch DMA
P2.x
Port P2
2 I/O
Interrupt
capability
pullup/down
resistors
2
USI
Universal
Serial
Interface
SPI, I2C
MSP430G2231-Q1
SLAS787B –NOVEMBER 2011–REVISED MARCH 2014 www.ti.com
4 Functional Block Diagram
Figure 1. Functional Block Diagram
2Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2231-Q1

MSP430G2231-Q1
www.ti.com SLAS787B –NOVEMBER 2011–REVISED MARCH 2014
Table of Contents
9.18 Crystal Oscillator, Xt1, Low-Frequency Mode ..... 25
1 Features ................................................................. 19.19 Internal Very-Low-Power Low-Frequency Oscillator
2 Applications .......................................................... 1(VLO) ...................................................................... 25
3 Description ............................................................ 19.20 Timer_A ................................................................ 25
4 Functional Block Diagram ................................... 29.21 USI, Universal Serial Interface ............................. 26
5 Revision History ................................................... 49.22 Typical Characteristics – USI Low-Level Output
6 Device Characteristics ......................................... 4Voltage On SDA and SCL ...................................... 26
9.23 10-Bit ADC, Power Supply and Input Range
7 Terminal Configuration and Functions ............... 5Conditions ............................................................... 27
7.1 14-Pin PW Package (Top View) .............................. 59.24 10-Bit ADC, Built-In Voltage Reference ............... 28
7.2 16-Pin RSA Package (Top View) ............................. 59.25 10-Bit ADC, External Reference .......................... 29
7.3 Terminal Functions .................................................. 69.26 10-Bit ADC, Timing Parameters ........................... 29
8 Detailed Description ............................................. 79.27 10-Bit ADC, Linearity Parameters ........................ 29
8.1 CPU .......................................................................... 79.28 10-Bit ADC, Temperature Sensor and Built-In VMID
8.2 Instruction Set .......................................................... 7................................................................................. 30
8.3 Operating Modes ..................................................... 89.29 Flash Memory ...................................................... 30
8.4 Interrupt Vector Addresses ...................................... 99.30 RAM ..................................................................... 31
8.5 Special Function Registers (SFRs) ........................ 10 9.31 JTAG and Spy-Bi-Wire Interface .......................... 31
8.6 Memory Organization ............................................. 11 9.32 JTAG Fuse ........................................................... 31
8.7 Flash Memory ........................................................ 11 10 I/O Port Schematics ........................................... 32
8.8 Peripherals ............................................................. 12 10.1 Port P1 Pin Schematic: P1.0 To P1.2, Input/Output
9 Specifications ...................................................... 16 With Schmitt Trigger ............................................... 32
9.1 Absolute Maximum Ratings ................................... 16 10.2 Port P1 Pin Schematic: P1.3, Input/Output With
9.2 Recommended Operating Conditions .................... 16 Schmitt Trigger ........................................................ 34
9.3 Active Mode Supply Current Into VCC Excluding 10.3 Port P1 Pin Schematic: P1.4, Input/Output With
External Current ...................................................... 17 Schmitt Trigger ........................................................ 35
9.4 Typical Characteristics – Active Mode Supply Current 10.4 Port P1 Pin Schematic: P1.5, Input/Output With
(Into VCC) ................................................................ 17 Schmitt Trigger ........................................................ 36
9.5 Low-Power Mode Supply Currents (Into VCC)10.5 Port P1 Pin Schematic: P1.6, Input/Output With
Excluding External Current ..................................... 18 Schmitt Trigger ........................................................ 37
9.6 Typical Characteristics, Low-Power Mode Supply 10.6 Port P1 Pin Schematic: P1.7, Input/Output With
Currents .................................................................. 18 Schmitt Trigger ........................................................ 38
9.7 Schmitt-Trigger Inputs – Ports Px .......................... 19 10.7 Port P2 Pin Schematic: P2.6, Input/Output With
Schmitt Trigger ........................................................ 39
9.8 Leakage Current – Ports Px .................................. 19 10.8 Port P2 Pin Schematic: P2.7, Input/Output With
9.9 Outputs – Ports Px ................................................. 19 Schmitt Trigger ........................................................ 40
9.10 Output Frequency – Ports Px .............................. 19 11 Device and Documentation Support ................ 41
9.11 Typical Characteristics – Outputs ........................ 20 11.1 Device Support .................................................... 41
9.12 POR, BOR ........................................................... 21 11.2 Documentation Support ....................................... 43
9.13 Main DCO Characteristics ................................... 23 11.3 Community Resources ......................................... 43
9.14 DCO Frequency ................................................... 23 11.4 Trademarks .......................................................... 44
9.15 Calibrated DCO Frequencies – Tolerance ........... 24 11.5 Electrostatic Discharge Caution ........................... 44
9.16 Wakeup From Lower-Power Modes (LPM3,
LPM4) – Electrical Characteristics .......................... 24 11.6 Glossary ............................................................... 44
9.17 Typical Characteristics – DCO Clock Wakeup Time 12 Mechanical, Packaging, and Orderable
From LPM3, LPM4 .................................................. 24 Information .......................................................... 44
Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: MSP430G2231-Q1

MSP430G2231-Q1
SLAS787B –NOVEMBER 2011–REVISED MARCH 2014 www.ti.com
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
REVISION DESCRIPTION
SLAS787 Product Preview release
SLAS787A Production Data release
Formatting and document organization changes throughout.
Removed all information related to operation at 105°C.
SLAS787B Removed all device variants except for MSP430G2231.
Added Device and Documentation Support and Mechanical, Packaging, and Orderable Information.
6 Device Characteristics
Table 1 shows the features of the MSP430G2231 device.
Table 1. Family Members
Flash RAM ADC10 Package
Device BSL EEM Timer_A USI Clock I/O
(KB) (B) Channel Type
16-QFN
MSP430G2231 - 1 2 128 1x TA2 1 8 LF, DCO, VLO 10 14-TSSOP
4Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2231-Q1

1
2
3
4
5
P1.4/SMCLK/A4/VREF+/VEREF+/TCK
6
P1.5/TA0.0/SCLK/A5/TMS
7
P1.6/TA0.1/SDO/SCL/TDI/TCLK
8
P1.7/SDI/SDA/TDO/TDI
9 RST/NMI/SBWTDIO
10 TEST/SBWTCK
11 XOUT/P2.7
12 XIN/P2.6/TA0.1
13
DVSS
14
DVSS
15
DVCC
16
DVCC
P1.0/TA0CLK/ACLK/A0
P1.1/TA0.0/A1
P1.2/TA0.1/A2
P1.3/ADC10CLK/A3/VREF-/VEREF-
1 DVCC
2
3
4
5
6
78
P1.6/TA0.1/A6/SDO/SCL/TDI/TCLK
9 P1.7/A7/SDI/SDA/TDO/TDI
10 RST/NMI/SBWTDIO
11 TEST/SBWTCK
12 XOUT/P2.7
13 XIN/P2.6/TA0.1
14 DVSS
P1.0/TA0CLK/ACLK/A0
P1.1/TA0.0/A1
P1.2/TA0.1/A2
P1.3/ADC10CLK/A3/VREF-/VEREF-
P1.4/SMCLK/A4/VREF+/VEREF +/TCK
P1.5/TA0.0/A5/SCLK/TMS
MSP430G2231-Q1
www.ti.com SLAS787B –NOVEMBER 2011–REVISED MARCH 2014
7 Terminal Configuration and Functions
7.1 14-Pin PW Package (Top View)
NOTE: See port schematics in I/O Port Schematics for detailed I/O information.
7.2 16-Pin RSA Package (Top View)
NOTE: See port schematics in I/O Port Schematics for detailed I/O information.
Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: MSP430G2231-Q1

MSP430G2231-Q1
SLAS787B –NOVEMBER 2011–REVISED MARCH 2014 www.ti.com
7.3 Terminal Functions
Table 2. Terminal Functions
TERMINAL
NO. I/O DESCRIPTION
NAME PW RSA
P1.0/ General-purpose digital I/O pin
TA0CLK/ Timer0_A, clock signal TACLK input
2 1 I/O
ACLK/ ACLK signal output
A0 ADC10 analog input A0
P1.1/ General-purpose digital I/O pin
TA0.0/ 3 2 I/O Timer0_A, capture: CCI0A input, compare: Out0 output
A1 ADC10 analog input A1
P1.2/ General-purpose digital I/O pin
TA0.1/ 4 3 I/O Timer0_A, capture: CCI1A input, compare: Out1 output
A2 ADC10 analog input A2
P1.3/ General-purpose digital I/O pin
ADC10CLK/ ADC10, conversion clock output
5 4 I/O
A3/ ADC10 analog input A3
VREF-/VEREF ADC10 negative reference voltage
P1.4/ General-purpose digital I/O pin
SMCLK/ SMCLK signal output
A4/ 6 5 I/O ADC10 analog input A4
VREF+/VEREF+/ ADC10 positive reference voltage
TCK JTAG test clock, input terminal for device programming and test
P1.5/ General-purpose digital I/O pin
TA0.0/ Timer0_A, compare: Out0 output
A5/ 7 6 I/O ADC10 analog input A5
SCLK/ USI: clock input in I2C mode; clock input/output in SPI mode
TMS JTAG test mode select, input terminal for device programming and test
P1.6/ General-purpose digital I/O pin
TA0.1/ Timer0_A, capture: CCI1A input, compare: Out1 output
A6/ ADC10 analog input A6
8 7 I/O
SDO/ USI: Data output in SPI mode
SCL/ USI: I2C clock in I2C mode
TDI/TCLK JTAG test data input or test clock input during programming and test
P1.7/ General-purpose digital I/O pin
A7/ ADC10 analog input A7
SDI/ 9 8 I/O USI: Data input in SPI mode
SDA/ USI: I2C data in I2C mode
TDO/TDI(1) JTAG test data output terminal or test data input during programming and test
XIN/ Input terminal of crystal oscillator
P2.6/ 13 12 I/O General-purpose digital I/O pin
TA0.1 Timer0_A, compare: Out1 output
XOUT/ Output terminal of crystal oscillator(2)
12 11 I/O
P2.7 General-purpose digital I/O pin
RST/ Reset
NMI/ 10 9 I Nonmaskable interrupt input
SBWTDIO Spy-Bi-Wire test data input/output during programming and test
TEST/ Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST.
11 10 I
SBWTCK Spy-Bi-Wire test clock input during programming and test
DVCC 1 15, 16 NA Supply voltage
DVSS 14 13, 14 NA Ground reference
QFN Pad - Pad NA QFN package pad connection to VSS recommended.
(1) TDO or TDI is selected via JTAG instruction.
(2) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to
this pad after reset.
6Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2231-Q1

Program Counter PC/R0
Stack Pointer SP/R1
Status Register SR/CG1/R2
Constant Generator CG2/R3
General-Purpose Register R4
General-Purpose Register R5
General-Purpose Register R6
General-Purpose Register R7
General-Purpose Register R8
General-Purpose Register R9
General-Purpose Register R10
General-Purpose Register R11
General-Purpose Register R12
General-Purpose Register R13
General-Purpose Register R15
General-Purpose Register R14
MSP430G2231-Q1
www.ti.com SLAS787B –NOVEMBER 2011–REVISED MARCH 2014
8 Detailed Description Instruction Set (continued)
8.1 CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-to-
register operation execution time is one cycle of the
CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data.
8.2 Instruction Set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 3 shows examples of the three types of
instruction formats, and Table 4 shows the address
modes.
Table 3. Instruction Word Formats
INSTRUCTION FORMAT SYNTAX OPERATION
Dual operands, source-destination ADD R4,R5 R4 + R5 ---> R5
Single operands, destination only CALL R8 PC -->(TOS), R8--> PC
Relative jump, un/conditional JNE Jump-on-equal bit = 0
Table 4. Address Mode Descriptions(1)
ADDRESS MODE S D SYNTAX EXAMPLE OPERATION
Register ✓ ✓ MOV Rs,Rd MOV R10,R11 R10 -- --> R11
Indexed ✓ ✓ MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) -- --> M(6+R6)
Symbolic (PC relative) ✓ ✓ MOV EDE,TONI M(EDE) -- --> M(TONI)
Absolute ✓ ✓ MOV &MEM,&TCDAT M(MEM) -- --> M(TCDAT)
Indirect ✓MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) -- --> M(Tab+R6)
M(R10) -- --> R11
Indirect autoincrement ✓MOV @Rn+,Rm MOV @R10+,R11 R10 + 2-- --> R10
Immediate ✓MOV #X,TONI MOV #45,TONI #45 -- --> M(TONI)
(1) S = source, D = destination
Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: MSP430G2231-Q1

MSP430G2231-Q1
SLAS787B –NOVEMBER 2011–REVISED MARCH 2014 www.ti.com
8.3 Operating Modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 1 (LPM1)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– DCO's dc generator is disabled if DCO not used in active mode
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and SMCLK are disabled
– DCO's dc generator remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK and SMCLK are disabled
– DCO's dc generator is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK and SMCLK are disabled
– DCO's dc generator is disabled
– Crystal oscillator is stopped
8Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2231-Q1

MSP430G2231-Q1
www.ti.com SLAS787B –NOVEMBER 2011–REVISED MARCH 2014
8.4 Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed) the
CPU goes into LPM4 immediately after power-up.
Table 5. Interrupt Sources, Flags, and Vectors
SYSTEM WORD
INTERRUPT SOURCE INTERRUPT FLAG PRIORITY
INTERRUPT ADDRESS
Power-Up PORIFG
External Reset RSTIFG
Watchdog Timer+ WDTIFG Reset 0FFFEh 31, highest
Flash key violation KEYV(2)
PC out-of-range(1)
NMI NMIIFG (non)-maskable
Oscillator fault OFIFG (non)-maskable 0FFFCh 30
Flash memory access violation ACCVIFG(2)(3) (non)-maskable 0FFFAh 29
0FFF8h 28
0FFF6h 27
Watchdog Timer+ WDTIFG maskable 0FFF4h 26
Timer_A2 TACCR0 CCIFG(4) maskable 0FFF2h 25
Timer_A2 TACCR1 CCIFG, TAIFG(2)(4) maskable 0FFF0h 24
0FFEEh 23
0FFECh 22
ADC10 ADC10IFG(4)(5) maskable 0FFEAh 21
USI USIIFG, USISTTIFG(2)(4) maskable 0FFE8h 20
I/O Port P2 (two flags) P2IFG.6 to P2IFG.7(2)(4) maskable 0FFE6h 19
I/O Port P1 (eight flags) P1IFG.0 to P1IFG.7(2)(4) maskable 0FFE4h 18
0FFE2h 17
0FFE0h 16
See (6) 0FFDEh to 15 to 0, lowest
0FFC0h
(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address ranges.
(2) Multiple source flags
(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
(4) Interrupt flags are located in the module.
(5) MSP430G2x31 only
(6) The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: MSP430G2231-Q1

MSP430G2231-Q1
SLAS787B –NOVEMBER 2011–REVISED MARCH 2014 www.ti.com
8.5 Special Function Registers (SFRs)
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend rw: Bit can be read and written.
rw-0,1: Bit can be read and written. It is reset or set by PUC.
rw-(0,1): Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
Table 6. Interrupt Enable Register 1 and 2
Address 76543210
00h ACCVIE NMIIE OFIE WDTIE
rw-0 rw-0 rw-0 rw-0
WDTIE Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in
interval timer mode.
OFIE Oscillator fault interrupt enable
NMIIE (Non)maskable interrupt enable
ACCVIE Flash access violation interrupt enable
Address 76543210
01h
Table 7. Interrupt Flag Register 1 and 2
Address 76543210
02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG
rw-0 rw-(0) rw-(1) rw-1 rw-(0)
WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.
OFIFG Flag set on oscillator fault.
PORIFG Power-On Reset interrupt flag. Set on VCC power-up.
RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up.
NMIIFG Set via RST/NMI pin
Address 76543210
03h
10 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2231-Q1

MSP430G2231-Q1
www.ti.com SLAS787B –NOVEMBER 2011–REVISED MARCH 2014
8.6 Memory Organization
Table 8. Memory Organization
MSP430G2231
Memory Size 2KB
Main: interrupt vector Flash 0xFFFF to 0xFFC0
Main: code memory Flash 0xFFFF to 0xF800
Information memory Size 256 Byte
Flash 010FFh to 01000h
RAM Size 128B
027Fh to 0200h
Peripherals 16-bit 01FFh to 0100h
8-bit 0FFh to 010h
8-bit SFR 0Fh to 00h
8.7 Flash Memory
The flash memory can be programmed using the Spy-Bi-Wire or JTAG port or in-system by the CPU. The CPU
can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also
called information memory.
• Segment A contains calibration data. After reset segment A is protected against programming and erasing. It
can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is
required.
Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: MSP430G2231-Q1

MSP430G2231-Q1
SLAS787B –NOVEMBER 2011–REVISED MARCH 2014 www.ti.com
8.8 Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
8.8.1 Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO).
The basic clock module is designed to meet the requirements of both low system cost and low power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1µs. The basic
clock module provides the following clock signals:
• Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
• Main clock (MCLK), the system clock used by the CPU.
• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
Table 9. DCO Calibration Data (Provided From Factory In Flash Information
Memory Segment A)
CALIBRATION
DCO FREQUENCY SIZE ADDRESS
REGISTER
CALBC1_1MHZ byte 010FFh
1 MHz CALDCO_1MHZ byte 010FEh
8.8.2 Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off.
8.8.3 Digital I/O
There is one 8-bit I/O port implemented—port P1—and two bits of I/O port P2:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt condition is possible.
• Edge-selectable interrupt input capability for all the eight bits of port P1 and the two bits of port P2.
• Read/write access to port-control registers is supported by all instructions.
• Each I/O has an individually programmable pull-up/pull-down resistor.
8.8.4 WDT+ Watchdog Timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be disabled or configured as an interval timer and can
generate interrupts at selected time intervals.
12 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2231-Q1

MSP430G2231-Q1
www.ti.com SLAS787B –NOVEMBER 2011–REVISED MARCH 2014
8.8.5 Timer_A2
Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 10. Timer_A2 Signal Connections – Device With ADC10
INPUT PIN NUMBER MODULE OUTPUT PIN NUMBER
DEVICE INPUT MODULE MODULE OUTPUT
SIGNAL INPUT NAME BLOCK
PW RSA PW RSA
SIGNAL
2 - P1.0 1 - P1.0 TACLK TACLK
ACLK ACLK Timer NA
SMCLK SMCLK
2 - P1.0 1 - P1.0 TACLK INCLK
3 - P1.1 2 - P1.1 TA0 CCI0A 3 - P1.1 2 - P1.1
ACLK (internal) CCI0B 7 - P1.5 6 - P1.5
CCR0 TA0
VSS GND
VCC VCC
4 - P1.2 3 - P1.2 TA1 CCI1A 4 - P1.2 3 - P1.2
8 - P1.6 7 - P1.6 TA1 CCI1B 8 - P1.6 7 - P1.6
CCR1 TA1
VSS GND 13 - P2.6 12 - P2.6
VCC VCC
8.8.6 USI
The universal serial interface (USI) module is used for serial data communication and provides the basic
hardware for synchronous communication protocols like SPI and I2C.
8.8.7 ADC10
The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion
result handling, allowing ADC samples to be converted and stored without any CPU intervention.
Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: MSP430G2231-Q1

MSP430G2231-Q1
SLAS787B –NOVEMBER 2011–REVISED MARCH 2014 www.ti.com
8.8.8 Peripheral File Map
Table 11. Peripherals With Word Access
REGISTER
MODULE REGISTER DESCRIPTION OFFSET
NAME
ADC10 ADC data transfer start address ADC10SA 1BCh
ADC control 0 ADC10CTL0 01B0h
ADC control 1 ADC10CTL0 01B2h
ADC memory ADC10MEM 01B4h
Timer_A Capture/compare register TACCR1 0174h
Capture/compare register TACCR0 0172h
Timer_A register TAR 0170h
Capture/compare control TACCTL1 0164h
Capture/compare control TACCTL0 0162h
Timer_A control TACTL 0160h
Timer_A interrupt vector TAIV 012Eh
Flash Memory Flash control 3 FCTL3 012Ch
Flash control 2 FCTL2 012Ah
Flash control 1 FCTL1 0128h
Watchdog Timer+ Watchdog/timer control WDTCTL 0120h
Table 12. Peripherals With Byte Access
REGISTER
MODULE REGISTER DESCRIPTION OFFSET
NAME
ADC10 ADC analog enable ADC10AE0 04Ah
ADC data transfer control 1 ADC10DTC1 049h
ADC data transfer control 0 ADC10DTC0 048h
USI USI control 0 USICTL0 078h
USI control 1 USICTL1 079h
USI clock control USICKCTL 07Ah
USI bit counter USICNT 07Bh
USI shift register USISR 07Ch
Basic Clock System+ Basic clock system control 3 BCSCTL3 053h
Basic clock system control 2 BCSCTL2 058h
Basic clock system control 1 BCSCTL1 057h
DCO clock frequency control DCOCTL 056h
Port P2 Port P2 resistor enable P2REN 02Fh
Port P2 selection P2SEL 02Eh
Port P2 interrupt enable P2IE 02Dh
Port P2 interrupt edge select P2IES 02Ch
Port P2 interrupt flag P2IFG 02Bh
Port P2 direction P2DIR 02Ah
Port P2 output P2OUT 029h
Port P2 input P2IN 028h
14 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2231-Q1

MSP430G2231-Q1
www.ti.com SLAS787B –NOVEMBER 2011–REVISED MARCH 2014
Table 12. Peripherals With Byte Access (continued)
REGISTER
MODULE REGISTER DESCRIPTION OFFSET
NAME
Port P1 Port P1 resistor enable P1REN 027h
Port P1 selection P1SEL 026h
Port P1 interrupt enable P1IE 025h
Port P1 interrupt edge select P1IES 024h
Port P1 interrupt flag P1IFG 023h
Port P1 direction P1DIR 022h
Port P1 output P1OUT 021h
Port P1 input P1IN 020h
Special Function SFR interrupt flag 2 IFG2 003h
SFR interrupt flag 1 IFG1 002h
SFR interrupt enable 2 IE2 001h
SFR interrupt enable 1 IE1 000h
Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: MSP430G2231-Q1

Supply voltage range,
during flash memory
programming
Supply voltage range,
during program execution
Legend:
16 MHz
System Frequency - MHz
12 MHz
6 MHz
1.8 V
Supply Voltage - V
3.3 V
2.7 V
2.2 V 3.6 V
MSP430G2231-Q1
SLAS787B –NOVEMBER 2011–REVISED MARCH 2014 www.ti.com
9 Specifications
9.1 Absolute Maximum Ratings (1)
Voltage applied at VCC to VSS –0.3 V to 4.1 V
Voltage applied to any pin(2) –0.3 V to VCC + 0.3 V
Diode current at any device pin ±2 mA
Unprogrammed device –55°C to 150°C
Storage temperature range, Tstg (3) Programmed device –55°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
9.2 Recommended Operating Conditions
Typical values are specified at VCC = 3.3 V and TA= 25°C (unless otherwise noted) MIN NOM MAX UNIT
During program execution 1.8 3.6
VCC Supply voltage V
During flash programming 2.2 3.6
VSS Supply voltage 0 V
TAOperating free-air temperature I version –40 85 °C
VCC = 1.8 V, dc 6
Duty cycle = 50% ± 10%
VCC = 2.7 V,
fSYSTEM Processor frequency (maximum MCLK frequency)(1)(2) dc 12 MHz
Duty cycle = 50% ± 10%
VCC = 3.3 V, dc 16
Duty cycle = 50% ± 10%
(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Note: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 2. Safe Operating Area
16 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2231-Q1

0.0
1.0
2.0
3.0
4.0
5.0
1.5 2.0 2.5 3.0 3.5 4.0
VCC − Supply Voltage − V
Active Mode Current − mA
fDCO = 1 MHz
fDCO = 8 MHz
fDCO = 12 MHz
fDCO = 16 MHz
0.0
1.0
2.0
3.0
4.0
0.0 4.0 8.0 12.0 16.0
fDCO − DCO Frequency − MHz
Active Mode Current − mA
TA= 25 °C
TA= 85 °C
VCC = 2.2 V
VCC = 3 V
TA= 25 °C
TA= 85 °C
MSP430G2231-Q1
www.ti.com SLAS787B –NOVEMBER 2011–REVISED MARCH 2014
9.3 Active Mode Supply Current Into VCC Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
PARAMETER TEST CONDITIONS TAVCC MIN TYP MAX UNIT
fDCO = fMCLK = fSMCLK = 1 MHz, 2.2 V 220
fACLK = 32768 Hz,
Program executes in flash,
Active mode (AM)
IAM,1MHz BCSCTL1 = CALBC1_1MHZ, µA
current (1 MHz) 3 V 300 370
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
9.4 Typical Characteristics – Active Mode Supply Current (Into VCC)
Figure 3. Active Mode Current vs Supply Voltage, TA= 25°C Figure 4. Active Mode Current vs DCO Frequency
Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: MSP430G2231-Q1

0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
-40
I – Low-Power Mode Current – µA
LPM3
Vcc = 3.6 V
T – Temperature – °C
A
Vcc = 1.8 V
Vcc = 3 V
Vcc = 2.2 V
-20 020 40 60 80
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
-40
I – Low-Power Mode Current – µA
LPM4
Vcc = 3.6 V
T – Temperature – °C
A
Vcc = 1.8 V
Vcc = 3 V
Vcc = 2.2 V
-20 020 40 60 80
MSP430G2231-Q1
SLAS787B –NOVEMBER 2011–REVISED MARCH 2014 www.ti.com
9.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
PARAMETER TEST CONDITIONS TAVCC MIN TYP MAX UNIT
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32768 Hz,
Low-power mode 0
ILPM0,1MHz BCSCTL1 = CALBC1_1MHZ, 25°C 2.2 V 65 µA
(LPM0) current(3) DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
fMCLK = fSMCLK = 0 MHz,
fDCO = 1 MHz,
fACLK = 32768 Hz,
Low-power mode 2
ILPM2 BCSCTL1 = CALBC1_1MHZ, 25°C 2.2 V 22 µA
(LPM2) current(4) DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
fDCO = fMCLK = fSMCLK = 0 MHz,
Low-power mode 3 fACLK = 32768 Hz,
ILPM3,LFXT1 25°C 2.2 V 0.7 1.5 µA
(LPM3) current(4) CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
fDCO = fMCLK = fSMCLK = 0 MHz,
Low-power mode 3 fACLK from internal LF oscillator (VLO),
ILPM3,VLO 25°C 2.2 V 0.5 0.7 µA
current, (LPM3)(4) CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
fDCO = fMCLK = fSMCLK = 0 MHz, 25°C 2.2 V 0.1 0.5 µA
Low-power mode 4 fACLK = 0 Hz,
ILPM4 (LPM4) current(5) CPUOFF = 1, SCG0 = 1, SCG1 = 1, 85°C 2.2 V 0.8 1.5 µA
OSCOFF = 1
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.
(3) Current for brownout and WDT clocked by SMCLK included.
(4) Current for brownout and WDT clocked by ACLK included.
(5) Current for brownout included.
9.6 Typical Characteristics, Low-Power Mode Supply Currents
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
Figure 6. LPM4 Current vs Temperature
Figure 5. LPM3 Current vs Temperature
18 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2231-Q1

MSP430G2231-Q1
www.ti.com SLAS787B –NOVEMBER 2011–REVISED MARCH 2014
9.7 Schmitt-Trigger Inputs – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
0.45 VCC 0.75 VCC
VIT+ Positive-going input threshold voltage V
3 V 1.35 2.25
0.25 VCC 0.55 VCC
VIT– Negative-going input threshold voltage V
3 V 0.75 1.65
Vhys Input voltage hysteresis (VIT+ – VIT–) 3 V 0.3 1 V
For pullup: VIN = VSS
RPull Pullup/pulldown resistor 3 V 20 35 50 kΩ
For pulldown: VIN = VCC
CIInput capacitance VIN = VSS or VCC 5 pF
9.8 Leakage Current – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
Ilkg(Px.y) High-impedance leakage current (1) (2) 3 V ±50 nA
(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
9.9 Outputs – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VOH High-level output voltage I(OHmax) = –6 mA(1) 3 V VCC – 0.3 V
VOL Low-level output voltage I(OLmax) = 6 mA(1) 3 V VSS + 0.3 V
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
9.10 Output Frequency – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Port output frequency
fPx.y Px.y, CL= 20 pF, RL= 1 kΩ(1) (2) 3 V 12 MHz
(with load)
fPort_CLK Clock output frequency Px.y, CL= 20 pF(2) 3 V 16 MHz
(1) A resistive divider with 2 × 0.5 kΩbetween VCC and VSS is used as load. The output is connected to the center tap of the divider.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: MSP430G2231-Q1

VOH − High-Level Output Voltage − V
−25
−20
−15
−10
−5
0
0 0.5 1 1.5 2 2.5
VCC = 2.2 V
P1.7
TA= 25°C
TA= 85°C
OH
I − Typical High-Level Output Current − mA
VOH − High-Level Output Voltage − V
−50
−40
−30
−20
−10
0
0 0.5 1 1.5 2 2.5 3 3.5
VCC = 3 V
P1.7
TA= 25°C
TA= 85°C
OH
I − Typical High-Level Output Current − mA
VOL − Low-Level Output Voltage − V
0
5
10
15
20
25
30
0 0.5 1 1.5 2 2.5
VCC = 2.2 V
P1.7 TA= 25°C
TA= 85°C
OL
I − Typical Low-Level Output Current − mA
VOL − Low-Level Output Voltage − V
0
10
20
30
40
50
0 0.5 1 1.5 2 2.5 3 3.5
VCC = 3 V
P1.7 TA= 25°C
TA= 85°C
OL
I − Typical Low-Level Output Current − mA
MSP430G2231-Q1
SLAS787B –NOVEMBER 2011–REVISED MARCH 2014 www.ti.com
9.11 Typical Characteristics – Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
Figure 7. Typical Low-Level Output Current vs Low-Level Figure 8. Typical Low-Level Output Current vs Low-Level
Output Voltage Output Voltage
Figure 9. Typical High-Level Output Current vs High-Level Figure 10. Typical High-Level Output Current vs High-Level
Output Voltage Output Voltage
20 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2231-Q1