Texas Instruments MUX36D04EVM-PDK User manual

1
SBAU255A–January 2016–Revised March 2016
Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated
MUX36D04EVM-PDK
All trademarks are the property of their respective owners.
User's Guide
SBAU255A–January 2016–Revised March 2016
MUX36D04EVM-PDK
This user guide describes the characteristics, operation, and use of the MUX36D04 evaluation module
(EVM) performance demonstration kit (PDK). This kit is an evaluation platform for MUX36D04, an analog
multiplexer (mux) that offers 4:1 differential or 8:2 single-ended channels. This user guide includes setup
and operating instructions, complete circuit descriptions, schematic diagrams, printed circuit board (PCB)
layout, and a bill of materials (BOM).
NOTE: The MUX36D04EVM may also be used to evaluate the performance of the MUX509 as the
two parts are pin compatible. The MUX509 would have to be separately ordered and
manually soldered on the MUX36D04EVM.
Throughout this document, the terms MUX36D04EVM, demonstration kit, evaluation board, evaluation
module, and EVM are synonymous with the MUX36D04EVM-PDK.
The following related documents are available through the Texas Instruments web site at www.ti.com.
Related Documentation
Device Literature Number
MUX36D04 SBOS705

www.ti.com
2SBAU255A–January 2016–Revised March 2016
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
MUX36D04EVM-PDK
Contents
1 Overview...................................................................................................................... 3
1.1 MUX36D04EVM-PDK Features................................................................................... 3
2 EVM Setup.................................................................................................................... 4
2.1 Powering Up the EVM.............................................................................................. 4
2.2 Digital Signal Connections......................................................................................... 5
2.3 Analog Signal Connections........................................................................................ 5
3 Evaluation Using the MUX36D04EVM-PDK ............................................................................. 6
3.1 Channel Selection Logic........................................................................................... 6
3.2 Key Specifications .................................................................................................. 6
4 Bill of Materials, PCB Layout, and Schematics.......................................................................... 7
4.1 Bill of Materials...................................................................................................... 7
4.2 PCB Layout.......................................................................................................... 8
4.3 Schematic............................................................................................................ 9
List of Figures
1 Power Connections for Single Supply (Left) and Dual Supply (Right) Operation ................................... 4
2 PCB Layer 1: Top Layer.................................................................................................... 8
3 PCB Layer 2: GND Plane................................................................................................... 8
4 Schematic: Electrical ........................................................................................................ 9
5 Schematic: Mechanical ..................................................................................................... 9
List of Tables
1 J1 and J13 Header Description............................................................................................ 4
2 Digital Signal Locations ..................................................................................................... 5
3 Analog Signal Locations .................................................................................................... 5
4 Channel Selection Truth Table............................................................................................. 6
5 Bill of Materials .............................................................................................................. 7

www.ti.com Overview
3
SBAU255A–January 2016–Revised March 2016
Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated
MUX36D04EVM-PDK
1 Overview
The MUX36D04 is a CMOS analog multiplexer that offers 4:1 differential or 8:2 single-ended channels,
operates with either dual supplies (±5 V to ±18 V) or a single supply (10 V to 36 V), and supports true rail-
to-rail input and output. The MUX36D04 has very low on- and off-leakage currents and low quiescent
current that make it ideally suited for portable applications.
1.1 MUX36D04EVM-PDK Features
The MUX36D04EVM-PDK includes the following features:
• Hardware required for evaluation of the with industry-standard TSSOP package MUX36D04.
• Multiple connectors on input and output pins for ease of evaluation.
• Layout as per the reference layout in data sheet.
• In addition to basic switching operations, the EVM can be used to test the crosstalk and off-isolation,
as per the data sheet.

PSU PSU
VDD
J18
VSS
VDD
GND
J18
GND GNDVDD VSS
VSS
VDD
GND
1 2 3 1 2 3
EVM Setup www.ti.com
4SBAU255A–January 2016–Revised March 2016
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
MUX36D04EVM-PDK
2 EVM Setup
This section describes the power supply and jumper configuration options available on the
MUX36D04EVM-PDK.
2.1 Powering Up the EVM
The MUX36D04 can operate with either dual supplies (±5 V to ±18 V) or a single supply (10 V to 36 V). It
can operate with both symmetric supplies (such as VDD = 12 V, VSS = –12 V), and unsymmetric supplies
(such as VDD = 12 V, VSS = –5 V).
The MUX36D04EVM-PDK provides connections for the power supply pins with either a single or dual
power supply, from a minimum VDD – VSS range of 10 V to maximum of 36 V. The VDD supply must be
connected at pin 1 and VSS at pin 2 of J18 from a tabletop power-supply unit (PSU) as shown in Figure 1.
For single-supply operation, connect VSS to GND through a wire-bridge between pin 2 and pin 3 of J18.
VDD and VSS can be monitored using TP10 and TP22, respectively.
Figure 1. Power Connections for Single Supply (Left) and Dual Supply (Right) Operation
Jumpers J1 and J13 are provided to enable monitoring of the currents drawn from each of these supplies
by the MUX36D04 using ammeters. In case ammeters are not used, headers J1 and J13 must be shorted
using shunts for normal operation, as listed in Table 1. The EVM ships with these shunts inserted.
Table 1. J1 and J13 Header Description
Signal Location Description
VDD J1 pin 1 to pin 2 Positive power supply for the MUX36D04
VSS J13 pin 1 to pin 2 Negative power supply for the MUX36D04

www.ti.com EVM Setup
5
SBAU255A–January 2016–Revised March 2016
Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated
MUX36D04EVM-PDK
2.2 Digital Signal Connections
The digital signals of the MUX36D04 are brought out to headers. Each of these signals can be connected
to VDD or VSS by using shunts as listed on Table 2.
Table 2. Digital Signal Locations
Signal Location Description
EN J3 pin 2 Active high digital input. When this pin is low, all switches are turned off.
When this pin is high, the A[2:0] inputs determine which switch is turned on.
A0 J4 pin 2 Address line A0
A1 J5 pin 2 Address line A1
Alternatively, these signals may be driven directly from a processor by removing the shunts, and wiring the
processor general-purpose I/Os to pin 2 of J3, J4, and J5 jumpers.
2.3 Analog Signal Connections
The analog signals of MUX36D04 are accessible at multiple locations on the MUX36D04EVM-PDK.
Table 3 lists all the locations. These signals may be used as input or output signals because the device
acts as a switch between the input and output terminals.
Table 3. Analog Signal Locations
Signal Header SMA Testpoint Description
S1A J16 pin4 J2 TP12 Source terminal 1A
S2A J16 pin3 J6 TP14 Source terminal 2A
S3A J16 pin2 J8 TP18 Source terminal 3A
S4A J16 pin1 J10 TP20 Source terminal 4A
S1B J16 pin7 J11 TP21 Source terminal 1B
S2B J16 pin8 J12 TP24 Source terminal 2B
S3B J16 pin9 J14 TP25 Source terminal 3B
S4B J16 pin10 J15 TP26 Source terminal 4B
DA NA J7 TP17 Drain terminal A
DB NA J9 TP19 Drain terminal B

Evaluation Using the MUX36D04EVM-PDK www.ti.com
6SBAU255A–January 2016–Revised March 2016
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
MUX36D04EVM-PDK
3 Evaluation Using the MUX36D04EVM-PDK
All parameters listed in the specifications table of the MUX36D04 data sheet can be tested on the
MUX36D04EVM-PDK.
3.1 Channel Selection Logic
Table 4 provides the truth table for the selection logic for the MUX36D04. This behavior of the device can
be evaluated by driving the digital selection signal listed in Section 2.2 to the appropriate levels.
(1) X denotes don't care..
Table 4. Channel Selection Truth Table
EN A1 A0 On channel
0 X(1) X(1) All channels are off
1 0 0 Channel 1
1 0 1 Channel 2
1 1 0 Channel 3
1 1 1 Channel 4
3.2 Key Specifications
The MUX36D04 datasheet contains detailed information of the test setups for each of the mux
parameters. The MUX36D04EVM-PDK can be used to validate these parameters as per the test
procedures described in the data sheet.

www.ti.com Bill of Materials, PCB Layout, and Schematics
7
SBAU255A–January 2016–Revised March 2016
Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated
MUX36D04EVM-PDK
4 Bill of Materials, PCB Layout, and Schematics
This section contains the MUX36D04EVM-PDK bill of materials (BOM),PCB layout, and EVM schematics.
4.1 Bill of Materials
Table 5 lists the MUX36D04EVM-PDK BOM.
Table 5. Bill of Materials
Manufacturer Part Number Qty Reference Designators Manufacturer Description
PA020 1 PCB1 Any Printed Circuit Board
C3216X5R1E476M160AC 2 C1, C4 TDK CAP, CERM, 47 µF, 25 V, +/- 20%, X5R, 1206
GMK316AB7106KL 2 C2, C5 Taiyo Yuden CAP, CERM, 10 µF, 35 V, +/- 10%, X7R, 1206
C3216X7R1H105K 2 C3, C6 TDK CAP, CERM, 1 µF, 50 V, +/- 10%, X7R, 1206
GRM188R72A104KA35D 2 C7, C10 MuRata CAP, CERM, 0.1 µF, 100 V, +/- 10%, X7R, 0603
C1608C0G2A101J 2 C8, C9 TDK CAP, CERM, 100 pF, 100 V, +/- 5%, C0G/NP0, 0603
N/A 3 FID1, FID2, FID3 N/A Fiducial mark. There is nothing to buy or mount.
SJ-5303 (CLEAR) 4 H1, H2, H3, H4 3M Bumpon, Hemisphere, 0.44 X 0.20, Clear
TSM-102-01-L-SV 2 J1, J13 Samtec Header, 100mil, 2x1, Gold with Tin Tail, SMT
5-1814832-1 10 J2, J6, J7, J8, J9, J10, J11,
J12, J14, J15 TE Connectivity SMA Straight PCB Socket Die Cast, 50 Ohm, TH
TSM-103-01-L-SV 3 J3, J4, J5 Samtec Header, 100mil, 3x1, Gold, SMT
OSTTE100161 1 J16 On-Shore Technology Terminal Block, 3.5mm, 10x1, Tin, Blue, TH
39357-0003 1 J18 Molex Terminal Block, 3.5 mm, 3x1, Tin, TH
THT-14-423-10 1 LBL1 Brady Thermal Transfer Printable Labels, 0.650" W x 0.200" H - 10,000 per roll
ERJ-6GEY0R00V 8 R1, R2, R3, R4, R5, R6, R7,
R8 Panasonic RES, 0, 5%, 0.125 W, 0805
969102-0000-DA 5 SH-J1, SH-J3, SH-J4, SH-J5,
SH-J13 3M Shunt, 100mil, Gold plated, Black
5005 3 TP1, TP10, TP11 Keystone Test Point, Compact, Red, TH
5006 7 TP2, TP3, TP4, TP5, TP6,
TP7, TP8 Keystone Test Point, Compact, Black, TH
5008 3 TP9, TP21, TP22 Keystone Test Point, Compact, Orange, TH
5122 8 TP12, TP14, TP18, TP20,
TP23, TP24, TP25, TP26 Keystone Test Point, Compact, Blue, TH
5009 3 TP13, TP15, TP16 Keystone Test Point, Compact, Yellow, TH
5007 2 TP17, TP19 Keystone Test Point, Compact, White, TH
MUX36D04IPWR 1 U1 Texas Instruments Fault-Protected, 8-Channel, Single-Ended and 4-Channel, Differential Multiplexer, PW0016A

Bill of Materials, PCB Layout, and Schematics www.ti.com
8SBAU255A–January 2016–Revised March 2016
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
MUX36D04EVM-PDK
4.2 PCB Layout
Figure 2 and Figure 3 illustrate the EVM PCB layout.
Figure 2. PCB Layer 1: Top Layer
Figure 3. PCB Layer 2: GND Plane

FID2FID1 FID3
H1
SJ-5303 (CLEAR)
H2
SJ-5303 (CLEAR)
H3
SJ-5303 (CLEAR)
H4
SJ-5303 (CLEAR)
SH-J1
969102-0000-DA
SH-J3
969102-0000-DA
SH-J4
969102-0000-DA
SH-J5
969102-0000-DA
SH-J13
969102-0000-DA
A0 1
A1 16
DA 8
DB 9
EN
2
GND 15
S1A
4
S2A
5
S3A
6
S4A
7
S1B
13
S2B
12
S3B
11
S4B
10
VDD
14
VSS 3
U1
MUX36D04IPWR
GND
0.1µF
C10
100pF
C9
0.1µF
C7
100pF
C8
GND
GND
VDD
VSS
TP10
TP11
TP22TP21
TP13
1
2 3 4 5
S1A
J2
1
2 3 4 5
S2A
J6
1
2 3 4 5
S3A
J8
1
2 3 4 5
S4A
J10
1
2 3 4 5
S1B
J11
1
2 3 4 5
S2B
J12
1
2 3 4 5
S3B
J14
1
2 3 4 5
S4B
J15
1
2 3 4 5
DA
J7
1
2 3 4 5
DB
J9
TP15 TP16
VDD
VDD VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TP17
TP12
TP14
TP18
TP23
TP24
TP25
TP26
TP19
GND GND GND
TP20
0
R1
0R2
0R4
0
R5
0
R6
0
R7
0R8
1
2
3
J18
39357-0003
GND
VDD
VSS
1 2 3
J5
1 2 3
J4
1 2 3
J3
1
2
J1
TSM-102-01-L-SV
1 2
J13
TSM-102-01-L-SV
5 4 1 2 3 6 7 8 9 10
J16
OSTTE100161
TP4 TP5 TP6 TP7 TP8TP3TP2
47µF
C4
10µF
C5
1µF
C6
47µF
C1
10µF
C2
1µF
C3
GND
VDD
VSS
TP1 TP9
GND GND GNDGND GND GND
0
R3
www.ti.com Bill of Materials, PCB Layout, and Schematics
9
SBAU255A–January 2016–Revised March 2016
Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated
MUX36D04EVM-PDK
4.3 Schematic
Figure 4 and Figure 5 show the EVM electrical and mechanical schematics, respectively.
Figure 4. Schematic: Electrical
Figure 5. Schematic: Mechanical

STANDARD TERMS AND CONDITIONS FOR EVALUATION MODULES
1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, or
documentation (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms and conditions set forth herein.
Acceptance of the EVM is expressly subject to the following terms and conditions.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms and conditions that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms and conditions do not apply to Software. The warranty, if any, for Software is covered in the applicable Software
License Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for any defects that are caused by neglect, misuse or mistreatment
by an entity other than TI, including improper installation or testing, or for any EVMs that have been altered or modified in any
way by an entity other than TI. Moreover, TI shall not be liable for any defects that result from User's design, specifications or
instructions for such EVMs. Testing and other quality control techniques are used to the extent TI deems necessary or as
mandated by government requirements. TI does not test all parameters of each EVM.
2.3 If any EVM fails to conform to the warranty set forth above, TI's sole liability shall be at its option to repair or replace such EVM,
or credit User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the
warranty period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to
repair or replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall
be warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
3Regulatory Notices:
3.1 United States
3.1.1 Notice applicable to EVMs not FCC-Approved:
This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit
to determine whether to incorporate such items in a finished product and software developers to write software applications for
use with the end product. This kit is not a finished product and when assembled may not be resold or otherwise marketed unless
all required FCC equipment authorizations are first obtained. Operation is subject to the condition that this product not cause
harmful interference to licensed radio stations and that this product accept harmful interference. Unless the assembled kit is
designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must operate under the authority of
an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2 For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER