GigaDevice Semiconductor GD32F30 Series User manual

GigaDevice Semiconductor Inc.
GD32F30x
Arm® Cortex®-M4 32-bit MCU
User Manual
Revision 2.9
( Dec. 2022 )

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Table of Contents
Table of Contents................................................................................................................. 2
List of Figures ....................................................................................................................19
List of Table ........................................................................................................................ 26
1. System and memory architecture ............................................................................ 30
1.1. Arm® Cortex®-M4processor...........................................................................................30
1.2. System architecture .....................................................................................................31
1.3. Memory map...............................................................................................................34
1.3.1. Bit-banding...............................................................................................................................................38
1.3.2. On-chip SRAM memory ........................................................................................................................39
1.3.3. On-chip flash memory overview..........................................................................................................39
1.4. Boot configuration.......................................................................................................39
1.5. Device electronic signature ...........................................................................................40
1.5.1. Memory density information.................................................................................................................41
1.5.2. Unique device ID (96 bits)....................................................................................................................41
1.6. System configuration registers ......................................................................................42
2. Flash memory controller (FMC) ................................................................................43
2.1. Introduction................................................................................................................43
2.2. Main features..............................................................................................................43
2.3. Function description.....................................................................................................43
2.3.1. Flash memory architecture...................................................................................................................43
2.3.2. Read operations......................................................................................................................................44
2.3.3. Unlock the FMC_CTLx registers.........................................................................................................44
2.3.4. Page erase...............................................................................................................................................45
2.3.5. Mass erase...............................................................................................................................................46
2.3.6. Main flash programming........................................................................................................................48
2.3.7. Option bytes Erase.................................................................................................................................49
2.3.8. Option bytes modify................................................................................................................................50
2.3.9. Option bytes description........................................................................................................................50
2.3.10. Page erase/program protection...........................................................................................................51
2.3.11. Security protection..................................................................................................................................52
2.4. FMC registers ..............................................................................................................53
2.4.1. Wait state register (FMC_WS).............................................................................................................53
2.4.2. Unlock key register 0(FMC_KEY0).....................................................................................................53
2.4.3. Option byte unlock key register (FMC_OBKEY) .............................................................................54
2.4.4. Status register 0 (FMC_STAT0)..........................................................................................................54

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2.4.5. Control register 0(FMC_CTL0)............................................................................................................55
2.4.6. Address register 0 (FMC_ADDR0).....................................................................................................56
2.4.7. Option byte status register (FMC_OBSTAT)....................................................................................57
2.4.8. Erase/Program Protection register (FMC_WP)...............................................................................57
2.4.9. Unlock key register 1(FMC_KEY1).....................................................................................................58
2.4.10. Status register 1 (FMC_STAT1)..........................................................................................................58
2.4.11. Control register 1(FMC_CTL1)............................................................................................................59
2.4.12. Address register 1 (FMC_ADDR1).....................................................................................................60
2.4.13. Wait state enable register (FMC_WSEN) .........................................................................................60
2.4.14. Product ID register (FMC_PID)...........................................................................................................61
3. Power management unit (PMU) ................................................................................ 62
3.1. Overview....................................................................................................................62
3.2. Characteristics.............................................................................................................62
3.3. Function overview .......................................................................................................62
3.3.1. Backup domain........................................................................................................................................63
3.3.2. VDD / VDDA power domain......................................................................................................................64
3.3.3. 1.2V power domain................................................................................................................................66
3.3.4. Power saving modes..............................................................................................................................66
3.4. PMU registers..............................................................................................................70
3.4.1. Control register (PMU_CTL) ................................................................................................................70
3.4.2. Control and status register (PMU_CS)..............................................................................................72
4. Backup registers (BKP).............................................................................................. 74
4.1. Introduction................................................................................................................74
4.2. Main features..............................................................................................................74
4.3. Function description.....................................................................................................74
4.3.1. RTC clock calibration.............................................................................................................................74
4.3.2. Tamper detection....................................................................................................................................74
4.4. BKP registers...............................................................................................................76
4.4.1. Backup data register x (BKP_DATAx) (x= 0..41).............................................................................76
4.4.2. RTC signal output control register (BKP_OCTL).............................................................................76
4.4.3. Tamper pin control register (BKP_TPCTL).......................................................................................77
4.4.4. Tamper control and status register (BKP_TPCS)............................................................................77
5. Reset and clock unit (RCU) ....................................................................................... 79
High- and extra-density eset and clock control unit (RCU) ...........................................................79
5.1. Reset controlunit (RCTL)...............................................................................................79
5.1.1. Overview...................................................................................................................................................79
5.1.2. Function overview...................................................................................................................................79
5.2. Clock control unit (CCTL)........................................................................................80

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5.2.1. Overview...................................................................................................................................................80
5.2.2. Characteristics.........................................................................................................................................82
5.2.3. Function overview...................................................................................................................................82
5.3. Register definition....................................................................................................86
5.3.1. Control register (RCU_CTL).................................................................................................................86
5.3.2. Clock configuration register 0 (RCU_CFG0)....................................................................................87
5.3.3. Clock interrupt register (RCU_INT)....................................................................................................91
5.3.4. APB2 reset register (RCU_APB2RST)..............................................................................................94
5.3.5. APB1 reset register (RCU_APB1RST)..............................................................................................96
5.3.6. AHB enable register (RCU_AHBEN).................................................................................................99
5.3.7. APB2 enable register (RCU_APB2EN)...........................................................................................100
5.3.8. APB1 enable register (RCU_APB1EN)...........................................................................................102
5.3.9. Backup domain control register (RCU_BDCTL)............................................................................105
5.3.10. Reset source/clock register (RCU_RSTSCK)................................................................................107
5.3.11. Clock configuration register 1 (RCU_CFG1)..................................................................................108
5.3.12. Deep-sleep mode voltage register (RCU_DSV)............................................................................109
5.3.13. Additional clock control register (RCU_ADDCTL).........................................................................110
5.3.14. Additional clock interrupt register (RCU_ADDINT).......................................................................110
5.3.15. APB1 additional reset register (RCU_ADDAPB1RST)................................................................111
5.3.16. APB1 additional enable register (RCU_ADDAPB1EN) ...............................................................112
Connectivity line devices: reset and clock control unit (RCU) .....................................................113
5.4. Reset controlunit (RCTL).............................................................................................113
5.4.1. Overview.................................................................................................................................................113
5.4.2. Function overview.................................................................................................................................113
5.5. Clock control unit (CCTL)......................................................................................114
5.5.1. Overview.................................................................................................................................................114
5.5.2. Characteristics.......................................................................................................................................116
5.5.3. Function overview.................................................................................................................................116
5.6. Registerdefinition..................................................................................................121
5.6.1. Control register (RCU_CTL)...............................................................................................................121
5.6.2. Clock configuration register 0 (RCU_CFG0)..................................................................................123
5.6.3. Clock interrupt register (RCU_INT)..................................................................................................126
5.6.4. APB2 reset register (RCU_APB2RST)............................................................................................130
5.6.5. APB1 reset register (RCU_APB1RST)............................................................................................132
5.6.6. AHB enable register (RCU_AHBEN)...............................................................................................135
5.6.7. APB2 enable register (RCU_APB2EN)...........................................................................................136
5.6.8. APB1 enable register (RCU_APB1EN)...........................................................................................139
5.6.9. Backup domain control register (RCU_BDCTL)............................................................................142
5.6.10. Reset source/clock register (RCU_RSTSCK)................................................................................143
5.6.11. AHB reset register (RCU_AHBRST)................................................................................................145
5.6.12. Clock configuration register 1 (RCU_CFG1)..................................................................................145
5.6.13. Deep-sleep mode voltage register (RCU_DSV)............................................................................148

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5.6.14. Additional clock control register (RCU_ADDCTL).........................................................................149
5.6.15. Additional clock interrupt register (RCU_ADDINT).......................................................................150
5.6.16. APB1 additional reset register (RCU_ADDAPB1RST)................................................................150
5.6.17. APB1 additional enable register (RCU_ADDAPB1EN) ...............................................................151
6. Clock trim controller (CTC)...................................................................................... 152
6.1. Overview..................................................................................................................152
6.2. Characteristics...........................................................................................................152
6.3. Function overview .....................................................................................................152
6.3.1. REF sync pulse generator..................................................................................................................153
6.3.2. CTC trim counter...................................................................................................................................153
6.3.3. Frequency evaluation and automatically trim process.................................................................154
6.3.4. Software program guide......................................................................................................................155
6.4. Registerdefinition......................................................................................................157
6.4.1. Control register 0 (CTC_CTL0).........................................................................................................157
6.4.2. Control register 1 (CTC_CTL1).........................................................................................................158
6.4.3. Status register (CTC_STAT)...............................................................................................................159
6.4.4. Interrupt clear register (CTC_INTC).................................................................................................161
7. Interrupt / event controller (EXTI) ...........................................................................163
7.1. Overview ..................................................................................................................163
7.2. Characteristics...........................................................................................................163
7.3. Interrupts function overview.......................................................................................163
7.4. External interrupt and event (EXTI) block diagram..........................................................167
7.5. External Interrupt and Event function overview.............................................................167
7.6. EXTI Register .............................................................................................................170
7.6.1. Interrupt enable register (EXTI_INTEN)..........................................................................................170
7.6.2. Event enable register (EXTI_EVEN)................................................................................................170
7.6.3. Rising edge trigger enable register (EXTI_RTEN)........................................................................171
7.6.4. Falling edge trigger enable register (EXTI_FTEN)........................................................................171
7.6.5. Software interrupt event register (EXTI_SWIEV)..........................................................................171
7.6.6. Pending register (EXTI_PD)...............................................................................................................172
8. General-purpose and alternate-function I/Os (GPIO and AFIO).........................173
8.1. Overview ..................................................................................................................173
8.2. Characteristics...........................................................................................................173
8.3. Function overview......................................................................................................173
8.3.1. GPIO pin configuration........................................................................................................................174
8.3.2. External interrupt/event lines..............................................................................................................175
8.3.3. Alternate functions (AF).......................................................................................................................175
8.3.4. Input configuration................................................................................................................................175

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8.3.5. Output configuration.............................................................................................................................176
8.3.6. Analog configuration............................................................................................................................177
8.3.7. Alternate function (AF) configuration................................................................................................177
8.3.8. GPIO locking function..........................................................................................................................178
8.3.9. GPIO I/O compensation cell...............................................................................................................178
8.4. Remapping function I/O and debug configuration..........................................................178
8.4.1. Introduction.............................................................................................................................................178
8.4.2. Main features.........................................................................................................................................179
8.4.3. JTAG/SWD alternate function remapping.......................................................................................179
8.4.4. ADC AF remapping..............................................................................................................................180
8.4.5. TIMER AF remapping..........................................................................................................................180
8.4.6. USART AF remapping.........................................................................................................................182
8.4.7. I2C0 AF remapping..............................................................................................................................182
8.4.8. SPI/I2S AF remapping.........................................................................................................................183
8.4.9. CAN AF remapping..............................................................................................................................183
8.4.10. Ethernet AF remapping.......................................................................................................................184
8.4.11. CTC AF remapping...............................................................................................................................184
8.4.12. CLK pins AF remapping......................................................................................................................184
8.5. Register definition......................................................................................................186
8.5.1. Port control register 0 (GPIOx_CTL0, x=A..G)..............................................................................186
8.5.2. Port control register 1 (GPIOx_CTL1, x=A..G)..............................................................................188
8.5.3. Port input status register (GPIOx_ISTAT, x=A..G).........................................................................189
8.5.4. Port output control register (GPIOx_OCTL, x=A..G)....................................................................190
8.5.5. Port bit operate register (GPIOx_BOP, x=A..G).............................................................................190
8.5.6. Port bit clear register (GPIOx_BC, x=A..G)....................................................................................191
8.5.7. Port configuration lock register (GPIOx_LOCK, x=A..G).............................................................191
8.5.8. Port bit speed register (GPIOx_ SPD, x=A..G)..............................................................................192
8.5.9. Event control register (AFIO_EC).....................................................................................................193
8.5.10. AFIO port configuration register 0 (AFIO_PCF0)..........................................................................193
8.5.11. EXTI sources selection register 0 (AFIO_EXTISS0)....................................................................200
8.5.12. EXTI sources selection register 1 (AFIO_EXTISS1)....................................................................202
8.5.13. EXTI sources selection register 2 (AFIO_EXTISS2)....................................................................203
8.5.14. EXTI sources selection register 3 (AFIO_EXTISS3)....................................................................204
8.5.15. AFIO port configuration register 1 (AFIO_PCF1)..........................................................................205
8.5.16. IO compensation control register (AFIO_CPSCTL)......................................................................207
9. Cyclic redundancy checks management unit (CRC)........................................... 208
9.1. Overview..................................................................................................................208
9.2. Characteristics...........................................................................................................208
9.3. Function overview .....................................................................................................209
9.4. Registerdefinition......................................................................................................210
9.4.1. Data register (CRC_DATA).................................................................................................................210

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9.4.2. Free data register (CRC_FDATA).....................................................................................................210
9.4.3. Control register (CRC_CTL)...............................................................................................................211
10. Direct memory access controller (DMA) ............................................................212
10.1. Overview...............................................................................................................212
10.2. Characteristics........................................................................................................212
10.3. Block diagram ........................................................................................................213
10.4. Function overview..................................................................................................213
10.4.1. DMA operation.......................................................................................................................................213
10.4.2. Peripheral handshake..........................................................................................................................215
10.4.3. Arbitration...............................................................................................................................................215
10.4.4. Address generation..............................................................................................................................215
10.4.5. Circular mode........................................................................................................................................216
10.4.6. Memory to memory mode...................................................................................................................216
10.4.7. Channel configuration..........................................................................................................................216
10.4.8. Interrupt...................................................................................................................................................216
10.4.9. DMA request mapping.........................................................................................................................217
10.5. Register definition ..............................................................................................221
10.5.1. Interrupt flag register (DMA_INTF)...................................................................................................221
10.5.2. Interrupt flag clear register (DMA_INTC) ........................................................................................222
10.5.3. Channel x control register (DMA_CHxCTL)...................................................................................222
10.5.4. Channel x counter register (DMA_CHxCNT).................................................................................224
10.5.5. Channel x peripheral base address register (DMA_CHxPADDR).............................................225
10.5.6. Channel x memory base address register (DMA_CHxMADDR)...............................................225
11. Debug (DBG)........................................................................................................... 227
11.1. Introduction...........................................................................................................227
11.2. JTAG/SW function description..................................................................................227
11.2.1. Switch JTAG or SW interface.............................................................................................................227
11.2.2. Pin assignment......................................................................................................................................227
11.2.3. JTAG daisy chained structure............................................................................................................228
11.2.4. Debug reset............................................................................................................................................228
11.2.5. JEDEC-106 ID code.............................................................................................................................228
11.3. Debug hold function description...............................................................................228
11.3.1. Debug support for power saving mode............................................................................................228
11.3.2. Debug support for TIMER, I2C, WWDGT, FWDGT and CAN....................................................229
11.4. DBG registers .........................................................................................................230
11.4.1. ID code register (DBG_ID) .................................................................................................................230
11.4.2. Control register 0 (DBG_CTL0).........................................................................................................230
12. Analog-to-digital converter (ADC).......................................................................234
12.1. Overview...............................................................................................................234

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12.2. Characteristics........................................................................................................234
12.3. Pins and internal signals..........................................................................................235
12.4. Functionaloverview................................................................................................236
12.4.1. Foreground calibration function.........................................................................................................236
12.4.2. ADC clock...............................................................................................................................................237
12.4.3. ADC enable............................................................................................................................................237
12.4.4. Routine sequence.................................................................................................................................237
12.4.5. Operation modes ..................................................................................................................................237
12.4.6. Conversion result threshold monitor function.................................................................................240
12.4.7. Data storagemode...............................................................................................................................240
12.4.8. Sample time configuration..................................................................................................................241
12.4.9. External trigger configuration.............................................................................................................241
12.4.10. DMA request......................................................................................................................................242
12.4.11. ADC internal channels.....................................................................................................................242
12.4.12. Programmable resolution (DRES)................................................................................................243
12.4.13. On-chip hardware oversampling...................................................................................................243
12.5. ADC sync mode ......................................................................................................245
12.5.1. Free mode..............................................................................................................................................246
12.5.2. Routine parallel mode..........................................................................................................................246
12.5.3. Routine follow-up fast mode...............................................................................................................247
12.5.4. Routine follow-up slow mode.............................................................................................................247
12.6. ADC interrupts .......................................................................................................248
12.7. ADC registers .........................................................................................................249
12.7.1. Status register (ADC_STAT)..............................................................................................................249
12.7.2. Control register 0 (ADC_CTL0).........................................................................................................250
12.7.3. Control register 1 (ADC_CTL1).........................................................................................................251
12.7.4. Sample time register 0 (ADC_SAMPT0).........................................................................................253
12.7.5. Sample time register 1 (ADC_SAMPT1).........................................................................................254
12.7.6. Watchdog high threshold register (ADC_WDHT)..........................................................................255
12.7.7. Watchdog low threshold register (ADC_WDLT)............................................................................255
12.7.8. Routine sequence register 0 (ADC_RSQ0)....................................................................................256
12.7.9. Routine sequence register 1 (ADC_RSQ1)....................................................................................256
12.7.10. Routine sequence register 2 (ADC_RSQ2) ...............................................................................257
12.7.11. Routine data register (ADC_RDATA)...........................................................................................258
12.7.12. Oversample control register (ADC_OVSAMPCTL)..................................................................258
13. Digital-to-analog converter (DAC) ....................................................................... 261
13.1. Introduction...........................................................................................................261
13.2. Characteristics........................................................................................................261
13.3. Function description ...............................................................................................262
13.3.1. DAC enable............................................................................................................................................262

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13.3.2. DAC output buffer.................................................................................................................................262
13.3.3. DAC data configuration.......................................................................................................................263
13.3.4. DAC trigger.............................................................................................................................................263
13.3.5. DAC workflow........................................................................................................................................263
13.3.6. DAC noise wave....................................................................................................................................263
13.3.7. DAC output calculate...........................................................................................................................264
13.3.8. DMA function..........................................................................................................................................265
13.3.9. DAC concurrent conversion...............................................................................................................265
13.4. DAC registers..........................................................................................................266
13.4.1. Control register (DAC_CTL)...............................................................................................................266
13.4.2. Software trigger register (DAC_SWT)..............................................................................................268
13.4.3. DAC0 12-bit right-aligned data holding register (DAC0_R12DH)..............................................269
13.4.4. DAC0 12-bit left-aligned data holding register (DAC0_L12DH).................................................269
13.4.5. DAC0 8-bit right-aligned data holding register (DAC0_R8DH)..................................................270
13.4.6. DAC1 12-bit right-aligned data holding register (DAC1_R12DH)..............................................270
13.4.7. DAC1 12-bit left-aligned data holding register (DAC1_L12DH).................................................271
13.4.8. DAC1 8-bit right-aligned data holding register (DAC1_R8DH)..................................................271
13.4.9. DAC concurrent mode 12-bit right-aligned data holding register (DACC_R12DH)...............272
13.4.10. DAC concurrent mode 12-bit left-aligned data holding register (DACC_L12DH)..............272
13.4.11. DAC concurrent mode 8-bit right-aligned data holding register (DACC_R8DH)...............273
13.4.12. DAC0 data output register (DAC0_DO)......................................................................................273
13.4.13. DAC1 data output register (DAC1_DO)......................................................................................274
14. Watchdog timer (WDGT) ....................................................................................... 275
14.1. Free watchdog timer (FWDGT)...........................................................................275
14.1.1. Overview.................................................................................................................................................275
14.1.2. Characteristics.......................................................................................................................................275
14.1.3. Function overview.................................................................................................................................275
14.1.4. Register definition.................................................................................................................................278
14.2. Window watchdog timer (WWDGT)....................................................................281
14.2.1. Overview.................................................................................................................................................281
14.2.2. Characteristics.......................................................................................................................................281
14.2.3. Function overview.................................................................................................................................281
14.2.4. Register definition.................................................................................................................................284
15. Real-time Clock(RTC) ............................................................................................ 286
15.1. Overview...............................................................................................................286
15.2. Characteristics........................................................................................................286
15.3. Function overview..................................................................................................286
15.3.1. RTC reset ...............................................................................................................................................287
15.3.2. RTC reading...........................................................................................................................................287
15.3.3. RTC configuration.................................................................................................................................287
15.3.4. RTC flag assertion................................................................................................................................288

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15.4. RTC Register...........................................................................................................290
15.4.1. RTC interrupt enable register(RTC_INTEN)...................................................................................290
15.4.2. RTC control register(RTC_CTL)........................................................................................................290
15.4.3. RTC prescaler high register (RTC_PSCH).....................................................................................291
15.4.4. RTC prescaler low register(RTC_PSCL).........................................................................................292
15.4.5. RTC divider high register (RTC_DIVH)............................................................................................292
15.4.6. RTC divider low register (RTC_DIVL)..............................................................................................292
15.4.7. RTC counter high register(RTC_CNTH)..........................................................................................293
15.4.8. RTC counter low register (RTC_CNTL)...........................................................................................293
15.4.9. RTC alarm high register(RTC_ALRMH)..........................................................................................294
15.4.10. RTC alarm low register (RTC_ALRML).......................................................................................294
16. Timer(TIMERx) ........................................................................................................ 295
16.1. Advanced timer (TIMERx, x=0, 7)..............................................................................296
16.1.1. Overview.................................................................................................................................................296
16.1.2. Characteristics.......................................................................................................................................296
16.1.3. Block diagram........................................................................................................................................297
16.1.4. Function overview.................................................................................................................................298
16.1.5. TIMERx registers(x=0, 7)....................................................................................................................324
16.2. General level0 timer (TIMERx, x=1, 2, 3, 4).................................................................350
16.2.1. Overview.................................................................................................................................................350
16.2.2. Characteristics.......................................................................................................................................350
16.2.3. Block diagram........................................................................................................................................350
16.2.4. Function overview.................................................................................................................................352
16.2.5. TIMERx registers(x=1, 2, 3, 4)...........................................................................................................367
16.3. General level1 timer (TIMERx, x=8, 11)......................................................................388
16.3.1. Overview.................................................................................................................................................388
16.3.2. Characteristics.......................................................................................................................................388
16.3.3. Block diagram........................................................................................................................................389
16.3.4. Function overview.................................................................................................................................390
16.3.5. TIMERx registers(x=8, 11)..................................................................................................................401
16.4. General level2 timer (TIMERx, x=9, 10, 12, 13)............................................................413
16.4.1. Overview.................................................................................................................................................413
16.4.2. Characteristics.......................................................................................................................................413
16.4.3. Block diagram........................................................................................................................................413
16.4.4. Function overview.................................................................................................................................415
16.4.5. TIMERx registers(x=9, 10, 12, 13)....................................................................................................422
16.5. Basic timer (TIMERx, x=5, 6).....................................................................................432
16.5.1. Overview.................................................................................................................................................432
16.5.2. Characteristics.......................................................................................................................................432
16.5.3. Block diagram........................................................................................................................................432
16.5.4. Function overview.................................................................................................................................432

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16.5.5. TIMERx registers(x=5, 6)....................................................................................................................436
17. Universal synchronous/asynchronous receiver /transmitter (USART) ......... 441
17.1. Overview...............................................................................................................441
17.2. Characteristics....................................................................................................441
17.3. Function overview..............................................................................................442
17.3.1. USART frame format............................................................................................................................443
17.3.2. Baud rate generation...........................................................................................................................444
17.3.3. USART transmitter................................................................................................................................444
17.3.4. USART receiver....................................................................................................................................445
17.3.5. Use DMA for data buffer access........................................................................................................447
17.3.6. Hardware flow control..........................................................................................................................448
17.3.7. Multi-processor communication.........................................................................................................449
17.3.8. LIN mode................................................................................................................................................450
17.3.9. Synchronous mode..............................................................................................................................451
17.3.10. IrDA SIR ENDEC mode..................................................................................................................452
17.3.11. Half-duplex communication mode................................................................................................453
17.3.12. Smartcard (ISO7816-3) mode.......................................................................................................453
17.3.13. USART interrupts..............................................................................................................................455
17.4. Register definition ..................................................................................................457
17.4.1. Status register 0 (USART_STAT0)...................................................................................................457
17.4.2. Data register (USART_DATA)............................................................................................................459
17.4.3. Baud rate register (USART_BAUD).................................................................................................459
17.4.4. Control register 0 (USART_CTL0)....................................................................................................460
17.4.5. Control register 1 (USART_CTL1)....................................................................................................462
17.4.6. Control register 2 (USART_CTL2)....................................................................................................463
17.4.7. Guard time and prescaler register (USART_GP)..........................................................................465
17.4.8. Control register 3 (USART_CTL3)....................................................................................................466
17.4.9. Receiver timeout register (USART_RT)..........................................................................................467
17.4.10. Status register 1 (USART_STAT1)...............................................................................................468
18. Inter-integrated circuit interface (I2C).................................................................470
18.1. Overview...............................................................................................................470
18.2. Characteristics........................................................................................................470
18.3. Function overview..................................................................................................470
18.3.1. SDA and SCL lines...............................................................................................................................471
18.3.2. Data validation.......................................................................................................................................472
18.3.3. START and STOP signal.....................................................................................................................472
18.3.4. Clock synchronization..........................................................................................................................472
18.3.5. Arbitration...............................................................................................................................................473
18.3.6. I2C communication flow......................................................................................................................474
18.3.7. Programming model.............................................................................................................................474

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18.3.8. SCL line stretching................................................................................................................................483
18.3.9. Use DMA for data transfer..................................................................................................................484
18.3.10. Packet error checking......................................................................................................................484
18.3.11. SMBus support..................................................................................................................................485
18.3.12. Status, errors and interrupts ..........................................................................................................486
18.4. Register definition ..................................................................................................488
18.4.1. Control register 0 (I2C_CTL0) ...........................................................................................................488
18.4.2. Control register 1 (I2C_CTL1) ...........................................................................................................490
18.4.3. Slave address register 0 (I2C_SADDR0)........................................................................................491
18.4.4. Slave address register 1 (I2C_SADDR1)........................................................................................491
18.4.5. Transfer buffer register (I2C_DATA).................................................................................................492
18.4.6. Transfer status register 0 (I2C_STAT0)...........................................................................................492
18.4.7. Transfer status register 1 (I2C_STAT1)...........................................................................................495
18.4.8. Clock configure register (I2C_CKCFG)...........................................................................................496
18.4.9. Rise time register (I2C_RT)................................................................................................................497
18.4.10. Fast-mode-plus configure register (I2C_FMPCFG).................................................................497
19. Serial peripheral interface/Inter-IC sound (SPI/I2S)..........................................499
19.1. Overview...............................................................................................................499
19.2. Characteristics........................................................................................................499
19.2.1. SPI characteristics................................................................................................................................499
19.2.2. I2S characteristics ................................................................................................................................499
19.3. SPI function overview..............................................................................................500
19.3.1. SPI block diagram.................................................................................................................................500
19.3.2. SPI signal description..........................................................................................................................500
19.3.3. SPI clock timing and data format ......................................................................................................501
19.3.4. NSS function..........................................................................................................................................502
19.3.5. SPI operation modes ...........................................................................................................................503
19.3.6. DMA function..........................................................................................................................................512
19.3.7. CRC function..........................................................................................................................................512
19.3.8. SPI interrupts.........................................................................................................................................512
19.4. I2S function overview..............................................................................................514
19.4.1. I2S block diagram.................................................................................................................................514
19.4.2. I2S signal description...........................................................................................................................514
19.4.3. I2S audio standards .............................................................................................................................515
19.4.4. I2S clock .................................................................................................................................................523
19.4.5. Operation................................................................................................................................................524
19.4.6. DMA function..........................................................................................................................................528
19.4.7. I2S interrupts..........................................................................................................................................528
19.5. Register definition ..................................................................................................530
19.5.1. Control register 0 (SPI_CTL0)...........................................................................................................530
19.5.2. Control register 1 (SPI_CTL1)...........................................................................................................532

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19.5.3. Status register (SPI_STAT) ................................................................................................................533
19.5.4. Data register (SPI_DATA)...................................................................................................................534
19.5.5. CRC polynomial register (SPI_CRCPOLY)....................................................................................535
19.5.6. RX CRC register (SPI_RCRC)..........................................................................................................535
19.5.7. TX CRC register (SPI_TCRC)...........................................................................................................536
19.5.8. I2S control register (SPI_I2SCTL)....................................................................................................537
19.5.9. I2S clock prescaler register (SPI_I2SPSC)....................................................................................538
19.5.10. Quad-SPI mode control register (SPI_QCTL) of SPI0.............................................................539
20. Secure digital input/output interface (SDIO) .....................................................540
20.1. Introduction...........................................................................................................540
20.2. Main features.........................................................................................................540
20.3. SDIO bus topology ..................................................................................................541
20.4. SDIO functional description......................................................................................543
20.4.1. SDIO adapter.........................................................................................................................................544
20.4.2. AHB interface.........................................................................................................................................548
20.5. Card functional description......................................................................................549
20.5.1. Card registers ........................................................................................................................................549
20.5.2. Commands.............................................................................................................................................550
20.5.3. Responses .............................................................................................................................................562
20.5.4. Data packets format.............................................................................................................................565
20.5.5. Two status fields of the card...............................................................................................................567
20.6. Programming sequence...........................................................................................574
20.6.1. Card identification.................................................................................................................................574
20.6.2. No data commands ..............................................................................................................................575
20.6.3. Single block or multiple block write...................................................................................................576
20.6.4. Single block or multiple block read...................................................................................................577
20.6.5. Stream write and stream read (MMC only).....................................................................................578
20.6.6. Erase.......................................................................................................................................................580
20.6.7. Bus width selection...............................................................................................................................580
20.6.8. Protection management......................................................................................................................581
20.6.9. Card Lock/Unlock operation...............................................................................................................581
20.7. Specific operations..................................................................................................584
20.7.1. SD I/O specific operations..................................................................................................................584
20.7.2. CE-ATA specific operations ................................................................................................................587
20.8. SDIO registers.........................................................................................................589
20.8.1. Power control register (SDIO_PWRCTL)........................................................................................589
20.8.2. Clock control register (SDIO_CLKCTL)...........................................................................................589
20.8.3. Command argument register (SDIO_CMDAGMT).......................................................................591
20.8.4. Command control register (SDIO_CMDCTL).................................................................................591
20.8.5. Command index response register (SDIO_RSPCMDIDX).........................................................593

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20.8.6. Response register (SDIO_RESPx x=0..3)......................................................................................593
20.8.7. Data timeout register (SDIO_DATATO)...........................................................................................594
20.8.8. Data length register (SDIO_DATALEN)...........................................................................................594
20.8.9. Data control register (SDIO_DATACTL)..........................................................................................595
20.8.10. Data counter register (SDIO_DATACNT)....................................................................................596
20.8.11. Status register (SDIO_STAT).........................................................................................................597
20.8.12. Interrupt clear register (SDIO_INTC)...........................................................................................598
20.8.13. Interrupt enable register (SDIO_INTEN).....................................................................................599
20.8.14. FIFO counter register (SDIO_FIFOCNT)....................................................................................601
20.8.15. FIFO data register (SDIO_FIFO)..................................................................................................602
21. External memory controller (EXMC) ...................................................................603
21.1. Overview...............................................................................................................603
21.2. Characteristics........................................................................................................603
21.3. Function overview..................................................................................................603
21.3.1. Block diagram........................................................................................................................................603
21.3.2. Basic regulation of EXMC access.....................................................................................................604
21.3.3. External device address mapping.....................................................................................................605
21.3.4. NOR/PSRAM controller.......................................................................................................................608
21.3.5. NAND Flash or PC Card controller...................................................................................................627
21.4. Registers definition.................................................................................................633
21.4.1. NOR/PSRAM controller registers......................................................................................................633
21.4.2. NAND Flash/PC Card controller registers.......................................................................................637
22. Controller area network (CAN).............................................................................644
22.1. Overview...............................................................................................................644
22.2. Characteristics........................................................................................................644
22.3. Function overview..................................................................................................645
22.3.1. Working mode........................................................................................................................................645
22.3.2. Communication modes........................................................................................................................646
22.3.3. Data transmission.................................................................................................................................647
22.3.4. Data reception.......................................................................................................................................649
22.3.5. Filtering function....................................................................................................................................650
22.3.6. Time-triggered communication..........................................................................................................654
22.3.7. Communication parameters...............................................................................................................654
22.3.8. Error flags...............................................................................................................................................656
22.3.9. CAN interrupts.......................................................................................................................................656
22.4. CAN registers .........................................................................................................659
22.4.1. Control register (CAN_CTL)...............................................................................................................659
22.4.2. Status register (CAN_STAT)..............................................................................................................660
22.4.3. Transmit status register (CAN_TSTAT)...........................................................................................662
22.4.4. Receive message FIFO0 register (CAN_RFIFO0).......................................................................665

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22.4.5. Receive message FIFO1 register (CAN_RFIFO1).......................................................................665
22.4.6. Interrupt enable register (CAN_INTEN)...........................................................................................666
22.4.7. Error register (CAN_ERR)..................................................................................................................668
22.4.8. Bit timing register (CAN_BT)..............................................................................................................669
22.4.9. Transmit mailbox identifier register (CAN_TMIx) (x = 0…2).......................................................670
22.4.10. Transmit mailbox property register (CAN_TMPx) (x = 0...2)..................................................670
22.4.11. Transmit mailbox data0 register (CAN_TMDATA0x) (x = 0...2).............................................671
22.4.12. Transmit mailbox data1 register (CAN_TMDATA1x) (x = 0...2).............................................672
22.4.13. Receive FIFO mailbox identifier register (CAN_RFIFOMIx) (x = 0,1)..................................672
22.4.14. Receive FIFO mailbox property register (CAN_RFIFOMPx) (x = 0,1).................................673
22.4.15. Receive FIFO mailbox data0 register (CAN_RFIFOMDATA0x) (x = 0,1)............................673
22.4.16. Receive FIFO mailbox data1 register (CAN_RFIFOMDATA1x) (x = 0,1)............................674
22.4.17. Filter control register (CAN_FCTL) (Just for CAN0).................................................................674
22.4.18. Filter mode configuration register (CAN_FMCFG) (Just for CAN0).....................................675
22.4.19. Filter scale configuration register (CAN_FSCFG) (Just for CAN0).......................................676
22.4.20. Filter associated FIFO register (CAN_FAFIFO) (Just for CAN0) ..........................................676
22.4.21. Filter working register (CAN_FW) (Just for CAN0)...................................................................677
22.4.22. Filter x data y register (CAN_FxDATAy) (x = 0...27, y = 0,1) (Just for CAN0)....................677
23. Ethernet (ENET)...................................................................................................... 679
23.1. Overview...............................................................................................................679
23.2. Characteristics........................................................................................................679
23.2.1. Block diagram........................................................................................................................................680
23.2.2. MAC 802.3 Ethernet packet description..........................................................................................681
23.2.3. Ethernet signal description.................................................................................................................682
23.3. Function overview..................................................................................................684
23.3.1. Interface configuration.........................................................................................................................684
23.3.2. MAC function overview........................................................................................................................688
23.3.3. DMA controller description..................................................................................................................699
23.3.4. MAC statistics counters: MSC...........................................................................................................724
23.3.5. Wake up management: WUM............................................................................................................725
23.3.6. Precision time protocol: PTP..............................................................................................................728
23.3.7. Example for a typical configuration flow of Ethernet.....................................................................732
23.3.8. Ethernet interrupts................................................................................................................................734
23.4. Register definition ..................................................................................................736
23.4.1. MAC configuration register (ENET_MAC_CFG)...........................................................................736
23.4.2. MAC frame filter register (ENET_MAC_FRMF).............................................................................738
23.4.3. MAC hash list high register (ENET_MAC_HLH)...........................................................................740
23.4.4. MAC hash list low register (ENET_MAC_HLL)..............................................................................741
23.4.5. MAC PHY control register (ENET_MAC_PHY_CTL)...................................................................741
23.4.6. MAC PHY data register (ENET_MAC_PHY_DATA).....................................................................742
23.4.7. MAC flow control register (ENET_MAC_FCTL)............................................................................742
23.4.8. MAC VLAN tag register (ENET_MAC_VLT)...................................................................................744

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23.4.9. MAC remote wakeup frame filter register (ENET_MAC_RWFF)...............................................745
23.4.10. MAC wakeup management register (ENET_MAC_WUM).....................................................745
23.4.11. MAC debug register (ENET_MAC_DBG)...................................................................................746
23.4.12. MAC interrupt flag register (ENET_MAC_INTF).......................................................................748
23.4.13. MAC interrupt mask register (ENET_MAC_INTMSK) .............................................................749
23.4.14. MAC address 0 high register (ENET_MAC_ADDR0H)...........................................................750
23.4.15. MAC address 0 low register (ENET_MAC_ADDR0L).............................................................750
23.4.16. MAC address 1 high register (ENET_MAC_ADDR1H)...........................................................751
23.4.17. MAC address 1 low register (ENET_MAC_ADDR1L).............................................................751
23.4.18. MAC address 2 high register (ENET_MAC_ADDR2H)...........................................................752
23.4.19. MAC address 2 low register (ENET_MAC_ADDR2L).............................................................753
23.4.20. MAC address 3 high register (ENET_MAC_ADDR3H)...........................................................753
23.4.21. MAC address 3 low register (ENET_MAC_ADDR3L).............................................................754
23.4.22. MAC flow control threshold register (ENET_MAC_FCTH).....................................................754
23.4.23. MSC control register (ENET_MSC_CTL)...................................................................................755
23.4.24. MSC receive interrupt flag register (ENET_MSC_RINTF)......................................................756
23.4.25. MSC transmit interrupt flag register (ENET_MSC_TINTF).....................................................757
23.4.26. MSC receive interrupt mask register (ENET_MSC_RINTMSK)............................................758
23.4.27. MSC transmit interrupt mask register (ENET_MSC_TINTMSK)...........................................758
23.4.28. MSC transmitted good frames after a single collision counter register
(ENET_MSC_SCCNT)..........................................................................................................................................759
23.4.29. MSC transmitted good frames after more than a single collision counter register
(ENET_MSC_MSCCNT)......................................................................................................................................760
23.4.30. MSC transmitted good frames counter register (ENET_MSC_TGFCNT)...........................760
23.4.31. MSC received frames with CRC error counter register (ENET_MSC_RFCECNT) ..........761
23.4.32. MSC received frames with alignment error counter register (ENET_MSC_RFAECNT)..761
23.4.33. MSC received good unicast frames counter register (ENET_MSC_RGUFCNT)..............762
23.4.34. PTP time stamp control register (ENET_PTP_TSCTL)...........................................................762
23.4.35. PTP subsecond increment register (ENET_PTP_SSINC)......................................................764
23.4.36. PTP time stamp high register (ENET_PTP_TSH)....................................................................765
23.4.37. PTP time stamp low register (ENET_PTP_TSL).......................................................................765
23.4.38. PTP time stamp update high register (ENET_PTP_TSUH)...................................................766
23.4.39. PTP time stamp update low register (ENET_PTP_TSUL)......................................................766
23.4.40. PTP time stamp addend register (ENET_PTP_TSADDEND)................................................767
23.4.41. PTP expected time high register (ENET_PTP_ETH)...............................................................767
23.4.42. PTP expected time low register (ENET_PTP_ETL).................................................................768
23.4.43. PTP time stamp flag register (ENET_PTP_TSF)......................................................................768
23.4.44. PTP PPS control register (ENET_PTP_PPSCTL)....................................................................769
23.4.45. DMA bus control register (ENET_DMA_BCTL).........................................................................769
23.4.46. DMA transmit poll enable register (ENET_DMA_TPEN).........................................................771
23.4.47. DMA receive poll enable register (ENET_DMA_RPEN)..........................................................772
23.4.48. DMA receive descriptor table address register (ENET_DMA_RDTADDR).........................773
23.4.49. DMA transmit descriptor table address register (ENET_DMA_TDTADDR)........................773
23.4.50. DMA status register (ENET_DMA_STAT)...................................................................................774

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23.4.51. DMA control register (ENET_DMA_CTL)...................................................................................777
23.4.52. DMA interrupt enable register (ENET_DMA_INTEN)..............................................................780
23.4.53. DMA missed frame and buffer overflow counter register (ENET_DMA_MFBOCNT).......782
23.4.54. DMA receive state watchdog counter register (ENET_DMA_RSWDC) ..............................783
23.4.55. DMA current transmit descriptor address register (ENET_DMA_CTDADDR)...................783
23.4.56. DMA current receive descriptor address register (ENET_DMA_CRDADDR)....................784
23.4.57. DMA current transmit buffer address register (ENET_DMA_CTBADDR)...........................784
23.4.58. DMA current receive buffer address register (ENET_DMA_CRBADDR)............................785
24. Universal Serial Bus full-speed device interface (USBD)................................ 786
24.1. Overview...............................................................................................................786
24.2. Main features.........................................................................................................786
24.3. Block diagram........................................................................................................786
24.4. Signaldescription ...................................................................................................787
24.5. Clock configuration.................................................................................................787
24.6. Function overview..................................................................................................788
24.6.1. USB endpoints.......................................................................................................................................788
24.6.2. Operation procedure............................................................................................................................790
24.6.3. USB events and interrupts..................................................................................................................793
24.6.4. Operation guide.....................................................................................................................................794
24.7. Registers definition.............................................................................................797
24.7.1. USBD control register (USBD_CTL)................................................................................................797
24.7.2. USBD interrupt flag register (USBD_INTF)....................................................................................799
24.7.3. USBD status register (USBD_STAT)................................................................................................800
24.7.4. USBD device address register (USBD_DADDR)..........................................................................800
24.7.5. USBD buffer address register (USBD_BADDR)............................................................................801
24.7.6. USBD endpoint x control and status register (USBD_EPxCS), x=[0..7]..................................801
24.7.7. USBD endpoint x transmission buffer address register (USBD_EPxTBADDR), x can be in
[0..7] 803
24.7.8. USBD endpoint x transmission buffer byte count register (USBD_EPxTBCNT), x can be in
[0..7] 803
24.7.9. USBD endpoint x reception buffer address register (USBD_EPxRBADDR), x can be in
[0..7] 804
24.7.10. USBD endpoint x reception buffer byte count register (USBD_EPxRBCNT), x can be in
[0..7] 804
24.7.11. USBD LPM control and status register (USBD_LPMCS).......................................................805
25. Universal serial bus full-speed interface (USBFS) ...........................................806
25.1. Overview...............................................................................................................806
25.2. Characteristics........................................................................................................806
25.3. Block diagram........................................................................................................807

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25.4. Signaldescription ...................................................................................................807
25.5. Function overview..................................................................................................807
25.5.1. USBFS clocks and working modes ..................................................................................................807
25.5.2. USB host function.................................................................................................................................809
25.5.3. USB device function.............................................................................................................................811
25.5.4. OTG function overview........................................................................................................................812
25.5.5. Data FIFO...............................................................................................................................................813
25.5.6. Operation guide.....................................................................................................................................815
25.6. Interrupts..............................................................................................................820
25.7. Registerdefinition ..................................................................................................822
25.7.1. Global control and status registers...................................................................................................822
25.7.2. Host control and status registers.......................................................................................................843
25.7.3. Device control and status registers ..................................................................................................855
25.7.4. Power and clock control register (USBFS_PWRCLKCTL).........................................................879
26. Revision history .....................................................................................................880

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List of Figures
Figure 1-1. The structure of the Cortex®-M4 processor...............................................................31
Figure 1-2. GD32F303 series system architecture.......................................................................33
Figure 1-3. GD32F305 and GD32F307 series system architecture ................................................34
Figure 2-1. Process of page erase operation..............................................................................46
Figure 2-2. Process of mass erase operation .............................................................................47
Figure 2-3. Process of word program operation .........................................................................49
Figure 3-1. Power supply overview............................................................................................63
Figure 3-2. Waveform of thePOR / PDR.....................................................................................65
Figure 3-3. Waveform of the LVD threshold................................................................................65
Figure 5-1. The system reset circuit...........................................................................................80
Figure 5-2. Clock tree ...............................................................................................................81
Figure 5-3. HXTAL clock source ................................................................................................82
Figure 5-4. HXTAL clock source in bypass mode........................................................................83
Figure 5-4. The system reset circuit.........................................................................................114
Figure 5-5. Clock tree .............................................................................................................115
Figure 5-6. HXTAL clock source ..............................................................................................117
Figure 5-4. HXTAL clock source in bypass mode......................................................................117
Figure 6-1. CTC overview........................................................................................................153
Figure 6-2. CTC trim counter...................................................................................................154
Figure 7-1. Block diagram of EXTI ...........................................................................................167
Figure 8-1. Basic structure ofa standard I/O port bit.................................................................174
Figure 8-2. Input configuration................................................................................................176
Figure 8-3. Output configuration.............................................................................................176
Figure 8-4. Analog configuration.............................................................................................177
Figure 8-5. Alternate function configuration.............................................................................178
Figure 9-1. Block diagram of CRC calculation unit....................................................................209
Figure 10-1. Block diagram of DMA.........................................................................................213
Figure 10-2. Handshake mechanism........................................................................................215
Figure 10-3. DMA interrupt logic..............................................................................................217
Figure 10-4. DMA0 requestmapping........................................................................................218
Figure 10-5. DMA1 requestmapping........................................................................................219
Figure 12-1. ADCmodule block diagram..................................................................................236
Figure 12-2. Single operationmode.........................................................................................237
Figure 12-3. Continuous operation mode.................................................................................238
Figure 12-4. Scan operation mode, continuous disable.............................................................239
Figure 12-5. Scan operation mode, continuous enable..............................................................239
Figure 12-6. Discontinuous operationmode.............................................................................240
Figure 12-9. 12-bit Data storage mode.....................................................................................241
Figure 12-10. 6-bit Data storage mode.....................................................................................241
Figure 12-11. 20-bit to 16-bit result truncation..........................................................................244

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Figure 12-12. Numerical example with 5-bits shift and rounding................................................244
Figure 12-13. ADC sync block diagram....................................................................................246
Figure 12-14. Routine parallel mode on 10 channels.................................................................247
Figure 12-16. Routine follow-up fastmode (the CTNbit of ADCs are set)...................................247
Figure 12-17. Routine follow-up slow mode..............................................................................248
Figure 13-1. DAC block diagram..............................................................................................262
Figure 13-2. DAC LFSR algorithm............................................................................................264
Figure 13-3. DAC triangle noise wave......................................................................................264
Figure 14-1. Free watchdog block diagram...............................................................................276
Figure 14-2. Window watchdog timer block diagram.................................................................281
Figure 14-3. Window watchdog timing diagram........................................................................282
Figure 15-1. Block diagram of RTC..........................................................................................287
Figure 16-1. Advanced timer block diagram.............................................................................297
Figure 16-2. Timing chart of internal clock divided by 1............................................................298
Figure 16-3. Timing chart of PSC value change from 0 to 2 .......................................................299
Figure 16-4. Timing chart of up countingmode, PSC=0/2..........................................................300
Figure 16-5. Timing chart of up counting mode, change TIMERx_CAR on the go........................301
Figure 16-6. Timing chart of down counting mode,PSC=0/2......................................................302
Figure 16-7. Timing chart of down counting mode, change TIMERx_CARon the go ...................303
Figure 16-8. Center-aligned counter timechart..........................................................................304
Figure 16-9. Repetition timechart for center-aligned counter.....................................................305
Figure 16-10. Repetition timechart for up-counter.....................................................................305
Figure 16-11. Repetition timechart for down-counter ................................................................306
Figure 16-12. Channel input capture principle..........................................................................307
Figure 16-13. Output-compare under three modes....................................................................309
Figure 16-14. EAPWM timechart..............................................................................................310
Figure 16-15. CAPWM timechart..............................................................................................310
Figure 16-16. Complementary output with dead-time insertion..................................................313
Figure 16-17. Output behavior in response to a break(The break high active).............................314
Figure 16-18. Counter behavior with CI0FE0 polarity non-inverted in mode 2.............................315
Figure 16-19. Counter behavior with CI0FE0 polarity inverted in mode 2....................................315
Figure 16-20. Hall sensor is used to BLDC motor .....................................................................316
Figure 16-21. Hall sensor timing between two timers................................................................317
Figure 16-22. Restart mode.....................................................................................................318
Figure 16-23. Pause mode.......................................................................................................319
Figure 16-24. Event mode .......................................................................................................319
Figure 16-25. Single pulse mode TIMERx_CHxCV = 4 TIMERx_CAR=99 .....................................320
Figure 16-26. Timer0 master/slave mode timer example............................................................321
Figure 16-27. Triggering TIMER0 with enable signal of TIMER2 .................................................322
Figure 16-28. Triggering TIMER0 and TIMER2 with TIMER2’s CI0 input ......................................323
Figure 16-29. General Level 0 timer blockdiagram ...................................................................351
Figure 16-30. Timing chart of internal clock divided by 1..........................................................352
Figure 16-31. Timing chart ofPSC value changefrom 0 to 2......................................................353
Figure 16-32. Timing chart of up countingmode, PSC=0/2........................................................354