Texas Instruments TMS320 2806 Series Product manual

TMS320x2806x Microcontrollers
Technical Reference Manual
Literature Number: SPRUH18I
JANUARY 2011 – REVISED JUNE 2022

Read This First.........................................................................................................................................................................37
About This Manual................................................................................................................................................................. 37
Notational Conventions.......................................................................................................................................................... 37
Glossary................................................................................................................................................................................. 37
Related Documentation From Texas Instruments.................................................................................................................. 37
Support Resources................................................................................................................................................................ 37
Trademarks............................................................................................................................................................................ 37
1 System Control and Interrupts............................................................................................................................................ 39
1.1 Flash and OTP Memory Blocks....................................................................................................................................... 40
1.1.1 Flash Memory............................................................................................................................................................40
1.1.2 OTP Memory............................................................................................................................................................. 40
1.1.3 Flash and OTP Power Modes................................................................................................................................... 41
1.1.4 Flash and OTP Registers.......................................................................................................................................... 46
1.2 Code Security Module (CSM).......................................................................................................................................... 52
1.2.1 Functional Description............................................................................................................................................... 52
1.2.2 CSM Impact on Other On-Chip Resources............................................................................................................... 55
1.2.3 Incorporating Code Security in User Applications..................................................................................................... 55
1.2.4 Do's and Don'ts to Protect Security Logic..................................................................................................................60
1.2.5 CSM Features - Summary.........................................................................................................................................60
1.2.6 CSM Status and Control Register............................................................................................................................. 61
1.3 Clocking........................................................................................................................................................................... 62
1.3.1 Clocking and System Control.................................................................................................................................... 62
1.3.2 OSC and PLL Block...................................................................................................................................................69
1.3.3 Low-Power Modes Block........................................................................................................................................... 93
1.3.4 CPU Watchdog Block................................................................................................................................................ 96
1.3.5 32-Bit CPU Timers 0/1/2..........................................................................................................................................102
1.4 General-Purpose Input/Output (GPIO)...........................................................................................................................107
1.4.1 GPIO Module Overview...........................................................................................................................................107
1.4.2 Configuration Overview............................................................................................................................................113
1.4.3 Digital General Purpose I/O Control........................................................................................................................ 115
1.4.4 Input Qualification.................................................................................................................................................... 116
1.4.5 GPIO and Peripheral Multiplexing (MUX)................................................................................................................120
1.4.6 Register Bit Definitions............................................................................................................................................ 124
1.5 Peripheral Frames..........................................................................................................................................................157
1.5.1 Peripheral Frame Registers.....................................................................................................................................157
1.5.2 EALLOW-Protected Registers.................................................................................................................................159
1.5.3 Device Emulation Registers.................................................................................................................................... 163
1.5.4 Write-Followed-by-Read Protection.........................................................................................................................166
1.6 Peripheral Interrupt Expansion (PIE)............................................................................................................................. 167
1.6.1 Overview of the PIE Controller................................................................................................................................ 167
1.6.2 Vector Table Mapping.............................................................................................................................................. 170
1.6.3 Interrupt Sources..................................................................................................................................................... 172
1.6.4 PIE Configuration Registers.................................................................................................................................... 181
1.6.5 PIE Interrupt Registers............................................................................................................................................ 182
1.6.6 External Interrupt Control Registers........................................................................................................................ 192
1.7 VREG/BOR/POR........................................................................................................................................................... 193
1.7.1 On-chip Voltage Regulator (VREG).........................................................................................................................193
1.7.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit................................................................... 194
2 Boot ROM............................................................................................................................................................................ 195
2.1 Boot ROM Memory Map................................................................................................................................................ 196
Table of Contents
www.ti.com Table of Contents
SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
Submit Document Feedback
TMS320x2806x Microcontrollers 3
Copyright © 2022 Texas Instruments Incorporated

2.1.1 On-Chip Boot ROM Math Tables............................................................................................................................. 198
2.1.2 On-Chip Boot ROM IQmath Functions.................................................................................................................... 200
2.1.3 On-Chip Flash API...................................................................................................................................................200
2.1.4 CPU Vector Table.................................................................................................................................................... 200
2.2 Bootloader Features.......................................................................................................................................................202
2.2.1 Bootloader Functional Operation.............................................................................................................................202
2.2.2 Bootloader Device Configuration.............................................................................................................................203
2.2.3 PLL Multiplier and DIVSEL Selection...................................................................................................................... 203
2.2.4 Watchdog Module....................................................................................................................................................203
2.2.5 Taking an ITRAP Interrupt....................................................................................................................................... 204
2.2.6 Internal Pullup Resisters..........................................................................................................................................204
2.2.7 PIE Configuration.................................................................................................................................................... 204
2.2.8 Reserved Memory................................................................................................................................................... 204
2.2.9 Bootloader Modes................................................................................................................................................... 205
2.2.10 Device_Cal.............................................................................................................................................................211
2.2.11 Bootloader Data Stream Structure.........................................................................................................................212
2.2.12 Basic Transfer Procedure...................................................................................................................................... 217
2.2.13 InitBoot Assembly Routine.................................................................................................................................... 218
2.2.14 SelectBootMode Function..................................................................................................................................... 218
2.2.15 CopyData Function................................................................................................................................................220
2.2.16 SCI_Boot Function................................................................................................................................................ 221
2.2.17 Parallel_Boot Function (GPIO).............................................................................................................................. 223
2.2.18 SPI_Boot Function.................................................................................................................................................227
2.2.19 I2C Boot Function..................................................................................................................................................230
2.2.20 eCAN Boot Function..............................................................................................................................................233
2.2.21 ExitBoot Assembly Routine................................................................................................................................... 235
2.3 Building the Boot Table.................................................................................................................................................. 236
2.3.1 The C2000 Hex Utility..............................................................................................................................................236
2.3.2 Example: Preparing a COFF File For eCAN Bootloading....................................................................................... 238
2.4 Bootloader Code Overview............................................................................................................................................ 240
2.4.1 Boot ROM Version and Checksum Information.......................................................................................................240
3 Enhanced Pulse Width Modulator (ePWM) Module.........................................................................................................241
3.1 Introduction.................................................................................................................................................................... 242
3.1.1 EPWM Related Collateral........................................................................................................................................242
3.1.2 Submodule Overview.............................................................................................................................................. 242
3.1.3 Register Mapping.................................................................................................................................................... 247
3.2 ePWM Submodules....................................................................................................................................................... 249
3.2.1 Overview..................................................................................................................................................................249
3.2.2 Time-Base (TB) Submodule.................................................................................................................................... 251
3.2.3 Counter-Compare (CC) Submodule........................................................................................................................ 260
3.2.4 Action-Qualifier (AQ) Submodule............................................................................................................................ 265
3.2.5 Dead-Band Generator (DB) Submodule..................................................................................................................278
3.2.6 PWM-Chopper (PC) Submodule............................................................................................................................. 282
3.2.7 Trip-Zone (TZ) Submodule...................................................................................................................................... 286
3.2.8 Event-Trigger (ET) Submodule................................................................................................................................292
3.2.9 Digital Compare (DC) Submodule........................................................................................................................... 297
3.3 Applications to Power Topologies.................................................................................................................................. 302
3.3.1 Overview of Multiple Modules..................................................................................................................................302
3.3.2 Key Configuration Capabilities................................................................................................................................ 303
3.3.3 Controlling Multiple Buck Converters With Independent Frequencies.................................................................... 304
3.3.4 Controlling Multiple Buck Converters With Same Frequencies............................................................................... 307
3.3.5 Controlling Multiple Half H-Bridge (HHB) Converters..............................................................................................310
3.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)............................................................................ 312
3.3.7 Practical Applications Using Phase Control Between PWM Modules..................................................................... 316
3.3.8 Controlling a 3-Phase Interleaved DC/DC Converter.............................................................................................. 318
3.3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter........................................................................ 321
3.3.10 Controlling a Peak Current Mode Controlled Buck Module................................................................................... 324
3.3.11 Controlling H-Bridge LLC Resonant Converter......................................................................................................326
3.4 Registers........................................................................................................................................................................ 328
3.4.1 Time-Base Submodule Registers............................................................................................................................ 328
3.4.2 Counter-Compare Submodule Registers................................................................................................................ 336
Table of Contents www.ti.com
4TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated

3.4.3 Action-Qualifier Submodule Registers.....................................................................................................................342
3.4.4 Dead-Band Submodule Registers........................................................................................................................... 347
3.4.5 Trip-Zone Submodule Control and Status Registers............................................................................................... 350
3.4.6 Event-Trigger Submodule Registers........................................................................................................................359
3.4.7 PWM-Chopper Submodule Control Register...........................................................................................................365
3.4.8 Digital Compare Submodule Registers................................................................................................................... 367
3.4.9 Proper Interrupt Initialization Procedure.................................................................................................................. 375
4 High-Resolution Pulse Width Modulator (HRPWM).........................................................................................................377
4.1 Introduction.................................................................................................................................................................... 378
4.2 Operational Description of HRPWM...............................................................................................................................379
4.2.1 Controlling the HRPWM Capabilities.......................................................................................................................380
4.2.2 Configuring the HRPWM......................................................................................................................................... 383
4.2.3 Principle of Operation.............................................................................................................................................. 384
4.2.4 Scale Factor Optimizing Software (SFO)................................................................................................................ 392
4.2.5 HRPWM Examples Using Optimized Assembly Code............................................................................................ 392
4.3 SFO Library Software - SFO_TI_Build_V6.lib................................................................................................................397
4.3.1 Scale Factor Optimizer Function - int SFO()........................................................................................................... 397
4.3.2 Software Usage....................................................................................................................................................... 398
4.3.3 SFO Library Version Software Differences..............................................................................................................400
4.4 HRPWM Registers......................................................................................................................................................... 401
4.4.1 HRPWM Configuration (HRCNFG) Register........................................................................................................... 401
4.4.2 High Resolution Micro Step (HRMSTEP) Register..................................................................................................402
4.4.3 High Resolution Period Control (HRPCTL) Register............................................................................................... 404
5 High-Resolution Capture (HRCAP) Module......................................................................................................................405
5.1 Introduction.................................................................................................................................................................... 406
5.1.1 Features.................................................................................................................................................................. 406
5.1.2 HRCAP Related Collateral...................................................................................................................................... 406
5.2 Description..................................................................................................................................................................... 406
5.3 Operational Details.........................................................................................................................................................407
5.3.1 HRCAP Clocking..................................................................................................................................................... 407
5.3.2 HRCAP Modes of Operation................................................................................................................................... 408
5.3.3 HRCAP Interrupts....................................................................................................................................................412
5.4 HRCAP Calibration Library............................................................................................................................................ 413
5.4.1 HRCAP Calibration Library Functions..................................................................................................................... 414
5.4.2 HRCAP Calibration Library Software Usage........................................................................................................... 419
5.5 HRCAP Register Descriptions....................................................................................................................................... 421
5.5.1 HRCAP Control Register (HCCTL)..........................................................................................................................422
5.5.2 HRCAP Interrupt Flag Register (HCIFR).................................................................................................................423
5.5.3 HRCAP Interrupt Clear Register (HCICLR).............................................................................................................424
5.5.4 HRCAP Interrupt Force Register (HCIFRC)............................................................................................................ 425
5.5.5 HRCAP Counter Register (HCCOUNTER)............................................................................................................. 426
5.5.6 HRCAP Capture Counter On Rising Edge 0 Register (HCCAPCNTRISE0)........................................................... 427
5.5.7 HRCAP Capture Counter On Falling Edge 0 Register (HCCAPCNTFALL0).......................................................... 427
5.5.8 HRCAP Capture Counter On Rising Edge 1 Register (HCCAPCNTRISE1)........................................................... 428
5.5.9 HRCAP Capture Counter On Falling Edge 1 Register (HCCAPCNTFALL1).......................................................... 428
6 Enhanced Capture (eCAP)................................................................................................................................................. 429
6.1 Introduction.................................................................................................................................................................... 430
6.1.1 Features.................................................................................................................................................................. 430
6.1.2 ECAP Related Collateral......................................................................................................................................... 430
6.2 Description..................................................................................................................................................................... 430
6.3 Capture and APWM Operating Mode............................................................................................................................ 432
6.4 Capture Mode Description............................................................................................................................................. 434
6.4.1 Event Prescaler....................................................................................................................................................... 435
6.4.2 Edge Polarity Select and Qualifier...........................................................................................................................436
6.4.3 Continuous/One-Shot Control................................................................................................................................. 436
6.4.4 32-Bit Counter and Phase Control...........................................................................................................................437
6.4.5 CAP1-CAP4 Registers............................................................................................................................................ 437
6.4.6 Interrupt Control.......................................................................................................................................................438
6.4.7 DMA Interrupt.......................................................................................................................................................... 439
6.4.8 Shadow Load and Lockout Control......................................................................................................................... 440
6.4.9 APWM Mode Operation...........................................................................................................................................440
www.ti.com Table of Contents
SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
Submit Document Feedback
TMS320x2806x Microcontrollers 5
Copyright © 2022 Texas Instruments Incorporated

6.5 Application of the eCAP Module.................................................................................................................................... 442
6.5.1 Example 1 - Absolute Time-Stamp Operation Rising Edge Trigger.........................................................................442
6.5.2 Example 2 - Absolute Time-Stamp Operation Rising and Falling Edge Trigger......................................................443
6.5.3 Example 3 - Time Difference (Delta) Operation Rising Edge Trigger...................................................................... 444
6.5.4 Example 4 - Time Difference (Delta) Operation Rising and Falling Edge Trigger................................................... 445
6.6 Application of the APWM Mode..................................................................................................................................... 446
6.6.1 Example 1 - Simple PWM Generation (Independent Channel/s)............................................................................ 446
6.7 eCAP Registers..............................................................................................................................................................446
6.7.1 ECAP Base Address Table......................................................................................................................................446
6.7.2 ECAP_REGS Registers.......................................................................................................................................... 447
7 Enhanced Quadrature Encoder Pulse (eQEP)................................................................................................................. 461
7.1 Introduction.................................................................................................................................................................... 462
7.1.1 EQEP Related Collateral......................................................................................................................................... 464
7.2 Configuring Device Pins.................................................................................................................................................464
7.3 Description..................................................................................................................................................................... 465
7.3.1 EQEP Inputs............................................................................................................................................................465
7.3.2 Functional Description............................................................................................................................................. 466
7.3.3 eQEP Memory Map................................................................................................................................................. 467
7.4 Quadrature Decoder Unit (QDU)....................................................................................................................................468
7.4.1 Position Counter Input Modes................................................................................................................................. 468
7.4.2 eQEP Input Polarity Selection................................................................................................................................. 471
7.4.3 Position-Compare Sync Output............................................................................................................................... 471
7.5 Position Counter and Control Unit (PCCU).................................................................................................................... 471
7.5.1 Position Counter Operating Modes......................................................................................................................... 471
7.5.2 Position Counter Latch............................................................................................................................................ 474
7.5.3 Position Counter Initialization.................................................................................................................................. 476
7.5.4 eQEP Position-compare Unit...................................................................................................................................476
7.6 eQEP Edge Capture Unit............................................................................................................................................... 478
7.7 eQEP Watchdog.............................................................................................................................................................482
7.8 eQEP Unit Timer Base................................................................................................................................................... 482
7.9 eQEP Interrupt Structure................................................................................................................................................483
7.10 eQEP Registers........................................................................................................................................................... 483
7.10.1 eQEP Base Addresses..........................................................................................................................................483
7.10.2 EQEP_REGS Registers........................................................................................................................................ 484
8 Analog-to-Digital Converter (ADC)....................................................................................................................................509
8.1 Introduction.................................................................................................................................................................... 510
8.1.1 Features.................................................................................................................................................................. 510
8.1.2 ADC Related Collateral........................................................................................................................................... 510
8.1.3 Block Diagram......................................................................................................................................................... 512
8.2 SOC Principle of Operation............................................................................................................................................513
8.2.1 ADC Acquisition (Sample and Hold) Window..........................................................................................................514
8.2.2 Trigger Operation.....................................................................................................................................................519
8.2.3 Channel Selection................................................................................................................................................... 519
8.3 ONESHOT Single Conversion Support..........................................................................................................................519
8.4 ADC Conversion Priority................................................................................................................................................ 520
8.5 Sequential Sampling Mode............................................................................................................................................ 523
8.6 Simultaneous Sampling Mode....................................................................................................................................... 523
8.7 EOC and Interrupt Operation......................................................................................................................................... 524
8.8 Power-Up Sequence...................................................................................................................................................... 525
8.9 ADC Calibration............................................................................................................................................................. 525
8.9.1 Factory Settings and Calibration Function...............................................................................................................525
8.9.2 ADC Zero Offset Calibration....................................................................................................................................525
8.9.3 ADC Full Scale Gain Calibration............................................................................................................................. 526
8.9.4 ADC Bias Current Calibration..................................................................................................................................526
8.10 Internal/External Reference Voltage Selection.............................................................................................................526
8.10.1 Internal Reference Voltage.................................................................................................................................... 526
8.10.2 External Reference Voltage...................................................................................................................................527
8.11 ADC Timings................................................................................................................................................................ 527
8.12 Internal Temperature Sensor........................................................................................................................................532
8.12.1 Transfer Function...................................................................................................................................................532
8.13 ADC Registers............................................................................................................................................................. 534
Table of Contents www.ti.com
6TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated

8.13.1 ADC Control Register 1 (ADCCTL1)..................................................................................................................... 535
8.13.2 ADC Control Register 2 (ADCCTL2)..................................................................................................................... 537
8.13.3 ADC Interrupt Registers........................................................................................................................................ 538
8.13.4 ADC Start of Conversion Priority Control Register (SOCPRICTL)........................................................................ 545
8.13.5 ADC SOC Registers.............................................................................................................................................. 547
8.13.6 ADC Calibration Registers.....................................................................................................................................556
8.13.7 Comparator Hysteresis Control Register (COMPHYSTCTL)................................................................................ 557
8.13.8 ADC Revision Register (ADCREV)....................................................................................................................... 558
8.13.9 ADC RESULT0-RESULT15 Registers (ADCRESULTx)........................................................................................ 558
9 Comparator (COMP)........................................................................................................................................................... 559
9.1 Introduction.................................................................................................................................................................... 560
9.1.1 Features.................................................................................................................................................................. 560
9.1.2 Block Diagram......................................................................................................................................................... 560
9.2 Comparator Function..................................................................................................................................................... 561
9.3 DAC Reference.............................................................................................................................................................. 561
9.4 Ramp Generator Input................................................................................................................................................... 562
9.5 Initialization.................................................................................................................................................................... 563
9.6 Digital Domain Manipulation.......................................................................................................................................... 563
9.7 Comparator Registers.................................................................................................................................................... 564
9.7.1 Comparator Control (COMPCTL) Register..............................................................................................................565
9.7.2 Compare Output Status (COMPSTS) Register....................................................................................................... 566
9.7.3 DAC Control (DACCTL) Register............................................................................................................................ 566
9.7.4 DAC Value (DACVAL) Register............................................................................................................................... 567
9.7.5 Ramp Generator Maximum Reference Active (RAMPMAXREF_ACTIVE) Register...............................................567
9.7.6 Ramp Generator Maximum Reference Shadow (RAMPMAXREF_SHDW) Register............................................. 567
9.7.7 Ramp Generator Decrement Value Active (RAMPDECVAL_ACTIVE) Register..................................................... 568
9.7.8 Ramp Generator Decrement Value Shadow (RAMPDECVAL_SHDW) Register.................................................... 568
9.7.9 Ramp Generator Status (RAMPSTS) Register....................................................................................................... 568
10 Control Law Accelerator (CLA)........................................................................................................................................569
10.1 Introduction.................................................................................................................................................................. 570
10.1.1 Features................................................................................................................................................................ 570
10.1.2 CLA Related Collateral.......................................................................................................................................... 570
10.1.3 Block Diagram....................................................................................................................................................... 571
10.2 CLA Interface............................................................................................................................................................... 572
10.2.1 CLA Memory..........................................................................................................................................................572
10.2.2 CLA Memory Bus.................................................................................................................................................. 573
10.2.3 Shared Peripherals and EALLOW Protection........................................................................................................573
10.2.4 CLA Tasks and Interrupt Vectors........................................................................................................................... 574
10.3 CLA and CPU Arbitration............................................................................................................................................. 575
10.3.1 CLA Message RAM............................................................................................................................................... 575
10.3.2 CLA Program Memory...........................................................................................................................................576
10.3.3 CLA Data Memory................................................................................................................................................. 576
10.3.4 Peripheral Registers (ePWM, HRPWM, Comparator, eCAP, eQEP).................................................................... 577
10.4 CLA Configuration and Debug..................................................................................................................................... 578
10.4.1 Building a CLA Application.................................................................................................................................... 578
10.4.2 Typical CLA Initialization Sequence...................................................................................................................... 579
10.4.3 Debugging CLA Code............................................................................................................................................580
10.4.4 CLA Illegal Opcode Behavior................................................................................................................................ 581
10.4.5 Resetting the CLA................................................................................................................................................. 582
10.5 Pipeline........................................................................................................................................................................ 582
10.5.1 Pipeline Overview..................................................................................................................................................582
10.5.2 CLA Pipeline Alignment.........................................................................................................................................583
10.5.3 Parallel Instructions............................................................................................................................................... 587
10.6 Instruction Set.............................................................................................................................................................. 588
10.6.1 Instruction Descriptions......................................................................................................................................... 588
10.6.2 Addressing Modes and Encoding..........................................................................................................................589
10.6.3 Instructions............................................................................................................................................................ 591
10.7 CLA Registers.............................................................................................................................................................. 709
10.7.1 Register Memory Mapping.................................................................................................................................... 709
10.7.2 Task Interrupt Vector Registers............................................................................................................................. 710
10.7.3 Configuration Registers......................................................................................................................................... 711
www.ti.com Table of Contents
SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
Submit Document Feedback
TMS320x2806x Microcontrollers 7
Copyright © 2022 Texas Instruments Incorporated

10.7.4 Execution Registers...............................................................................................................................................724
11 Direct Memory Access (DMA) Module............................................................................................................................ 727
11.1 Introduction...................................................................................................................................................................728
11.2 DMA Overview..............................................................................................................................................................728
11.3 Architecture.................................................................................................................................................................. 729
11.3.1 Block Diagram........................................................................................................................................................729
11.3.2 Peripheral Interrupt Event Trigger Sources........................................................................................................... 730
11.3.3 DMA Bus................................................................................................................................................................731
11.4 Pipeline Timing and Throughput...................................................................................................................................732
11.5 CPU Arbitration.............................................................................................................................................................733
11.6 Channel Priority............................................................................................................................................................733
11.6.1 Round-Robin Mode................................................................................................................................................733
11.6.2 Channel 1 High Priority Mode................................................................................................................................734
11.7 Address Pointer and Transfer Control.......................................................................................................................... 735
11.8 Overrun Detection Feature...........................................................................................................................................739
11.9 DMA Registers............................................................................................................................................................. 740
11.9.1 DMA Control Register (DMACTRL) — EALLOW Protected.................................................................................. 741
11.9.2 Debug Control Register (DEBUGCTRL) — EALLOW Protected...........................................................................743
11.9.3 Revision Register (REVISION).............................................................................................................................. 743
11.9.4 Priority Control Register 1 (PRIORITYCTRL1) — EALLOW Protected.................................................................744
11.9.5 Priority Status Register (PRIORITYSTAT)............................................................................................................. 745
11.9.6 Mode Register (MODE) — EALLOW Protected.................................................................................................... 746
11.9.7 Control Register (CONTROL) — EALLOW Protected...........................................................................................748
11.9.8 Burst Size Register (BURST_SIZE) — EALLOW Protected..................................................................................750
11.9.9 BURST_COUNT Register......................................................................................................................................750
11.9.10 Source Burst Step Register Size (SRC_BURST_STEP) — EALLOW Protected................................................751
11.9.11 Destination Burst Step Register Size (DST_BURST_STEP) — EALLOW Protected..........................................752
11.9.12 Transfer Size Register (TRANSFER_SIZE) — EALLOW Protected................................................................... 752
11.9.13 Transfer Count Register (TRANSFER_COUNT)................................................................................................. 753
11.9.14 Source Transfer Step Size Register (SRC_TRANSFER_STEP) — EALLOW Protected....................................753
11.9.15 Destination Transfer Step Size Register (DST_TRANSFER_STEP) — EALLOW Protected............................. 754
11.9.16 Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE) — EALLOW protected)...............................755
11.9.17 Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT)............................................................. 755
11.9.18 Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP) — EALLOW Protected.................... 756
11.9.19 Shadow Source Begin and Current Address Pointer Registers (SRC_BEG_ADDR_SHADOW/
DST_BEG_ADDR_SHADOW) — All EALLOW Protected............................................................................................757
11.9.20 Active Source Begin and Current Address Pointer Registers (SRC_BEG_ADDR/DST_BEG_ADDR)............... 757
11.9.21 Shadow Destination Begin and Current Address Pointer Registers (SRC_ADDR_SHADOW/
DST_ADDR_SHADOW) — All EALLOW Protected..................................................................................................... 758
11.9.22 Active Destination Begin and Current Address Pointer Registers (SRC_ADDR/DST_ADDR)............................758
12 Serial Peripheral Interface (SPI)...................................................................................................................................... 759
12.1 Introduction.................................................................................................................................................................. 760
12.1.1 Features................................................................................................................................................................ 760
12.1.2 Block Diagram....................................................................................................................................................... 761
12.2 System-Level Integration............................................................................................................................................. 762
12.2.1 SPI Module Signals............................................................................................................................................... 762
12.2.2 Configuring Device Pins........................................................................................................................................ 762
12.2.3 SPI Interrupts.........................................................................................................................................................763
12.2.4 DMA Support......................................................................................................................................................... 764
12.3 SPI Operation...............................................................................................................................................................766
12.3.1 Introduction to Operation....................................................................................................................................... 766
12.3.2 Master Mode..........................................................................................................................................................768
12.3.3 Slave Mode............................................................................................................................................................768
12.3.4 Data Format...........................................................................................................................................................769
12.3.5 Baud Rate Selection..............................................................................................................................................770
12.3.6 SPI Clocking Schemes.......................................................................................................................................... 771
12.3.7 SPI FIFO Description.............................................................................................................................................772
12.3.8 SPI 3-Wire Mode Description................................................................................................................................ 773
12.4 Programming Procedure.............................................................................................................................................. 775
12.4.1 Initialization Upon Reset........................................................................................................................................775
12.4.2 Configuring the SPI............................................................................................................................................... 775
Table of Contents www.ti.com
8TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated

12.4.3 Data Transfer Example..........................................................................................................................................776
12.4.4 SPI 3-Wire Mode Code Examples.........................................................................................................................777
12.4.5 SPI STEINV Bit in Digital Audio Transfers.............................................................................................................778
12.5 SPI Registers............................................................................................................................................................... 779
12.5.1 SPI Base Addresses..............................................................................................................................................779
12.5.2 SPI_REGS Registers............................................................................................................................................ 779
13 Serial Communications Interface (SCI).......................................................................................................................... 799
13.1 Introduction.................................................................................................................................................................. 800
13.1.1 Features................................................................................................................................................................ 800
13.1.2 SCI Related Collateral........................................................................................................................................... 801
13.1.3 Block Diagram....................................................................................................................................................... 801
13.2 Architecture.................................................................................................................................................................. 801
13.3 SCI Module Signal Summary....................................................................................................................................... 801
13.4 Configuring Device Pins...............................................................................................................................................802
13.5 Multiprocessor and Asynchronous Communication Modes......................................................................................... 803
13.6 SCI Programmable Data Format..................................................................................................................................803
13.7 SCI Multiprocessor Communication.............................................................................................................................804
13.7.1 Recognizing the Address Byte.............................................................................................................................. 804
13.7.2 Controlling the SCI TX and RX Features...............................................................................................................804
13.7.3 Receipt Sequence................................................................................................................................................. 804
13.8 Idle-Line Multiprocessor Mode..................................................................................................................................... 805
13.8.1 Idle-Line Mode Steps.............................................................................................................................................805
13.8.2 Block Start Signal.................................................................................................................................................. 805
13.8.3 Wake-UP Temporary (WUT) Flag..........................................................................................................................806
13.8.4 Receiver Operation................................................................................................................................................806
13.9 Address-Bit Multiprocessor Mode................................................................................................................................ 807
13.9.1 Sending an Address.............................................................................................................................................. 807
13.10 SCI Communication Format.......................................................................................................................................808
13.10.1 Receiver Signals in Communication Modes........................................................................................................ 808
13.10.2 Transmitter Signals in Communication Modes.................................................................................................... 809
13.11 SCI Port Interrupts......................................................................................................................................................810
13.12 SCI Baud Rate Calculations.......................................................................................................................................810
13.13 SCI Enhanced Features............................................................................................................................................. 811
13.13.1 SCI FIFO Description...........................................................................................................................................811
13.13.2 SCI Auto-Baud.....................................................................................................................................................813
13.13.3 Autobaud-Detect Sequence................................................................................................................................ 813
13.14 SCI Registers............................................................................................................................................................. 814
13.14.1 SCI Base Addresses........................................................................................................................................... 814
13.14.2 SCI_REGS Registers.......................................................................................................................................... 814
14 Inter-Integrated Circuit Module (I2C)...............................................................................................................................833
14.1 Introduction.................................................................................................................................................................. 834
14.1.1 I2C Related Collateral........................................................................................................................................... 834
14.1.2 Features................................................................................................................................................................ 835
14.1.3 Features Not Supported........................................................................................................................................ 835
14.1.4 Functional Overview.............................................................................................................................................. 836
14.1.5 Clock Generation...................................................................................................................................................837
14.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)......................................................................................... 838
14.2 Configuring Device Pins...............................................................................................................................................839
14.3 I2C Module Operational Details................................................................................................................................... 839
14.3.1 Input and Output Voltage Levels........................................................................................................................... 839
14.3.2 Data Validity...........................................................................................................................................................839
14.3.3 Operating Modes................................................................................................................................................... 839
14.3.4 I2C Module START and STOP Conditions............................................................................................................ 843
14.3.5 Non-repeat Mode versus Repeat Mode................................................................................................................ 844
14.3.6 Serial Data Formats...............................................................................................................................................845
14.3.7 Clock Synchronization........................................................................................................................................... 847
14.3.8 Arbitration.............................................................................................................................................................. 848
14.3.9 Digital Loopback Mode.......................................................................................................................................... 849
14.3.10 NACK Bit Generation...........................................................................................................................................850
14.4 Interrupt Requests Generated by the I2C Module....................................................................................................... 851
14.4.1 Basic I2C Interrupt Requests.................................................................................................................................851
www.ti.com Table of Contents
SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
Submit Document Feedback
TMS320x2806x Microcontrollers 9
Copyright © 2022 Texas Instruments Incorporated

14.4.2 I2C FIFO Interrupts................................................................................................................................................853
14.5 Resetting or Disabling the I2C Module.........................................................................................................................853
14.6 I2C Registers............................................................................................................................................................... 853
14.6.1 I2C Base Address Table........................................................................................................................................ 853
14.6.2 I2C_REGS Registers.............................................................................................................................................854
15 Multichannel Buffered Serial Port (McBSP)................................................................................................................... 877
15.1 Introduction.................................................................................................................................................................. 878
15.1.1 Features of the McBSP......................................................................................................................................... 878
15.1.2 McBSP Pins/Signals..............................................................................................................................................879
15.2 McBSP Operation........................................................................................................................................................ 880
15.2.1 Data Transfer Process of McBSP..........................................................................................................................880
15.2.2 Companding (Compressing and Expanding) Data................................................................................................ 881
15.2.3 Clocking and Framing Data................................................................................................................................... 883
15.2.4 Frame Phases....................................................................................................................................................... 885
15.3 McBSP Sample Rate Generator.................................................................................................................................. 890
15.3.1 Block Diagram....................................................................................................................................................... 890
15.3.2 Frame Synchronization Generation in the Sample Rate Generator...................................................................... 893
15.3.3 Synchronizing Sample Rate Generator Outputs to an External Clock.................................................................. 893
15.3.4 Reset and Initialization Procedure for the Sample Rate Generator.......................................................................895
15.4 McBSP Exception/Error Conditions............................................................................................................................. 896
15.4.1 Types of Errors...................................................................................................................................................... 896
15.4.2 Overrun in the Receiver.........................................................................................................................................897
15.4.3 Unexpected Receive Frame-Synchronization Pulse............................................................................................. 898
15.4.4 Overwrite in the Transmitter.................................................................................................................................. 900
15.4.5 Unexpected Transmit Frame-Synchronization Pulse............................................................................................ 902
15.5 Multichannel Selection Modes..................................................................................................................................... 904
15.5.1 Channels, Blocks, and Partitions...........................................................................................................................904
15.5.2 Multichannel Selection...........................................................................................................................................905
15.5.3 Configuring a Frame for Multichannel Selection....................................................................................................905
15.5.4 Using Two Partitions..............................................................................................................................................905
15.5.5 Using Eight Partitions............................................................................................................................................ 907
15.5.6 Receive Multichannel Selection Mode...................................................................................................................908
15.5.7 Transmit Multichannel Selection Modes................................................................................................................ 909
15.6 SPI Operation Using the Clock Stop Mode.................................................................................................................. 912
15.6.1 SPI Protocol...........................................................................................................................................................912
15.6.2 Clock Stop Mode................................................................................................................................................... 912
15.6.3 Bits Used to Enable and Configure the Clock Stop Mode..................................................................................... 913
15.6.4 Clock Stop Mode Timing Diagrams....................................................................................................................... 914
15.6.5 Procedure for Configuring a McBSP for SPI Operation.........................................................................................916
15.6.6 McBSP as the SPI Master..................................................................................................................................... 917
15.6.7 McBSP as an SPI Slave........................................................................................................................................ 918
15.7 Receiver Configuration.................................................................................................................................................919
15.7.1 Programming the McBSP Registers for the Desired Receiver Operation............................................................. 919
15.7.2 Resetting and Enabling the Receiver.................................................................................................................... 920
15.7.3 Set the Receiver Pins to Operate as McBSP Pins................................................................................................ 920
15.7.4 Enable/Disable the Digital Loopback Mode...........................................................................................................921
15.7.5 Enable/Disable the Clock Stop Mode.................................................................................................................... 921
15.7.6 Enable/Disable the Receive Multichannel Selection Mode................................................................................... 922
15.7.7 Choose One or Two Phases for the Receive Frame............................................................................................. 922
15.7.8 Set the Receive Word Length(s)............................................................................................................................923
15.7.9 Set the Receive Frame Length..............................................................................................................................923
15.7.10 Enable/Disable the Receive Frame-Synchronization Ignore Function................................................................ 924
15.7.11 Set the Receive Companding Mode.................................................................................................................... 925
15.7.12 Set the Receive Data Delay................................................................................................................................ 926
15.7.13 Set the Receive Sign-Extension and Justification Mode..................................................................................... 928
15.7.14 Set the Receive Interrupt Mode...........................................................................................................................929
15.7.15 Set the Receive Frame-Synchronization Mode................................................................................................... 930
15.7.16 Set the Receive Frame-Synchronization Polarity................................................................................................ 932
15.7.17 Set the Receive Clock Mode............................................................................................................................... 934
15.7.18 Set the Receive Clock Polarity............................................................................................................................ 935
15.7.19 Set the SRG Clock Divide-Down Value............................................................................................................... 936
Table of Contents www.ti.com
10 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated