Texas Instruments TMS320 2806 Series Product manual

TMS320x2806x Microcontrollers
Technical Reference Manual
Literature Number: SPRUH18I
JANUARY 2011 – REVISED JUNE 2022

Read This First.........................................................................................................................................................................37
About This Manual................................................................................................................................................................. 37
Notational Conventions.......................................................................................................................................................... 37
Glossary................................................................................................................................................................................. 37
Related Documentation From Texas Instruments.................................................................................................................. 37
Support Resources................................................................................................................................................................ 37
Trademarks............................................................................................................................................................................ 37
1 System Control and Interrupts............................................................................................................................................ 39
1.1 Flash and OTP Memory Blocks....................................................................................................................................... 40
1.1.1 Flash Memory............................................................................................................................................................40
1.1.2 OTP Memory............................................................................................................................................................. 40
1.1.3 Flash and OTP Power Modes................................................................................................................................... 41
1.1.4 Flash and OTP Registers.......................................................................................................................................... 46
1.2 Code Security Module (CSM).......................................................................................................................................... 52
1.2.1 Functional Description............................................................................................................................................... 52
1.2.2 CSM Impact on Other On-Chip Resources............................................................................................................... 55
1.2.3 Incorporating Code Security in User Applications..................................................................................................... 55
1.2.4 Do's and Don'ts to Protect Security Logic..................................................................................................................60
1.2.5 CSM Features - Summary.........................................................................................................................................60
1.2.6 CSM Status and Control Register............................................................................................................................. 61
1.3 Clocking........................................................................................................................................................................... 62
1.3.1 Clocking and System Control.................................................................................................................................... 62
1.3.2 OSC and PLL Block...................................................................................................................................................69
1.3.3 Low-Power Modes Block........................................................................................................................................... 93
1.3.4 CPU Watchdog Block................................................................................................................................................ 96
1.3.5 32-Bit CPU Timers 0/1/2..........................................................................................................................................102
1.4 General-Purpose Input/Output (GPIO)...........................................................................................................................107
1.4.1 GPIO Module Overview...........................................................................................................................................107
1.4.2 Configuration Overview............................................................................................................................................113
1.4.3 Digital General Purpose I/O Control........................................................................................................................ 115
1.4.4 Input Qualification.................................................................................................................................................... 116
1.4.5 GPIO and Peripheral Multiplexing (MUX)................................................................................................................120
1.4.6 Register Bit Definitions............................................................................................................................................ 124
1.5 Peripheral Frames..........................................................................................................................................................157
1.5.1 Peripheral Frame Registers.....................................................................................................................................157
1.5.2 EALLOW-Protected Registers.................................................................................................................................159
1.5.3 Device Emulation Registers.................................................................................................................................... 163
1.5.4 Write-Followed-by-Read Protection.........................................................................................................................166
1.6 Peripheral Interrupt Expansion (PIE)............................................................................................................................. 167
1.6.1 Overview of the PIE Controller................................................................................................................................ 167
1.6.2 Vector Table Mapping.............................................................................................................................................. 170
1.6.3 Interrupt Sources..................................................................................................................................................... 172
1.6.4 PIE Configuration Registers.................................................................................................................................... 181
1.6.5 PIE Interrupt Registers............................................................................................................................................ 182
1.6.6 External Interrupt Control Registers........................................................................................................................ 192
1.7 VREG/BOR/POR........................................................................................................................................................... 193
1.7.1 On-chip Voltage Regulator (VREG).........................................................................................................................193
1.7.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit................................................................... 194
2 Boot ROM............................................................................................................................................................................ 195
2.1 Boot ROM Memory Map................................................................................................................................................ 196
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2.1.1 On-Chip Boot ROM Math Tables............................................................................................................................. 198
2.1.2 On-Chip Boot ROM IQmath Functions.................................................................................................................... 200
2.1.3 On-Chip Flash API...................................................................................................................................................200
2.1.4 CPU Vector Table.................................................................................................................................................... 200
2.2 Bootloader Features.......................................................................................................................................................202
2.2.1 Bootloader Functional Operation.............................................................................................................................202
2.2.2 Bootloader Device Configuration.............................................................................................................................203
2.2.3 PLL Multiplier and DIVSEL Selection...................................................................................................................... 203
2.2.4 Watchdog Module....................................................................................................................................................203
2.2.5 Taking an ITRAP Interrupt....................................................................................................................................... 204
2.2.6 Internal Pullup Resisters..........................................................................................................................................204
2.2.7 PIE Configuration.................................................................................................................................................... 204
2.2.8 Reserved Memory................................................................................................................................................... 204
2.2.9 Bootloader Modes................................................................................................................................................... 205
2.2.10 Device_Cal.............................................................................................................................................................211
2.2.11 Bootloader Data Stream Structure.........................................................................................................................212
2.2.12 Basic Transfer Procedure...................................................................................................................................... 217
2.2.13 InitBoot Assembly Routine.................................................................................................................................... 218
2.2.14 SelectBootMode Function..................................................................................................................................... 218
2.2.15 CopyData Function................................................................................................................................................220
2.2.16 SCI_Boot Function................................................................................................................................................ 221
2.2.17 Parallel_Boot Function (GPIO).............................................................................................................................. 223
2.2.18 SPI_Boot Function.................................................................................................................................................227
2.2.19 I2C Boot Function..................................................................................................................................................230
2.2.20 eCAN Boot Function..............................................................................................................................................233
2.2.21 ExitBoot Assembly Routine................................................................................................................................... 235
2.3 Building the Boot Table.................................................................................................................................................. 236
2.3.1 The C2000 Hex Utility..............................................................................................................................................236
2.3.2 Example: Preparing a COFF File For eCAN Bootloading....................................................................................... 238
2.4 Bootloader Code Overview............................................................................................................................................ 240
2.4.1 Boot ROM Version and Checksum Information.......................................................................................................240
3 Enhanced Pulse Width Modulator (ePWM) Module.........................................................................................................241
3.1 Introduction.................................................................................................................................................................... 242
3.1.1 EPWM Related Collateral........................................................................................................................................242
3.1.2 Submodule Overview.............................................................................................................................................. 242
3.1.3 Register Mapping.................................................................................................................................................... 247
3.2 ePWM Submodules....................................................................................................................................................... 249
3.2.1 Overview..................................................................................................................................................................249
3.2.2 Time-Base (TB) Submodule.................................................................................................................................... 251
3.2.3 Counter-Compare (CC) Submodule........................................................................................................................ 260
3.2.4 Action-Qualifier (AQ) Submodule............................................................................................................................ 265
3.2.5 Dead-Band Generator (DB) Submodule..................................................................................................................278
3.2.6 PWM-Chopper (PC) Submodule............................................................................................................................. 282
3.2.7 Trip-Zone (TZ) Submodule...................................................................................................................................... 286
3.2.8 Event-Trigger (ET) Submodule................................................................................................................................292
3.2.9 Digital Compare (DC) Submodule........................................................................................................................... 297
3.3 Applications to Power Topologies.................................................................................................................................. 302
3.3.1 Overview of Multiple Modules..................................................................................................................................302
3.3.2 Key Configuration Capabilities................................................................................................................................ 303
3.3.3 Controlling Multiple Buck Converters With Independent Frequencies.................................................................... 304
3.3.4 Controlling Multiple Buck Converters With Same Frequencies............................................................................... 307
3.3.5 Controlling Multiple Half H-Bridge (HHB) Converters..............................................................................................310
3.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)............................................................................ 312
3.3.7 Practical Applications Using Phase Control Between PWM Modules..................................................................... 316
3.3.8 Controlling a 3-Phase Interleaved DC/DC Converter.............................................................................................. 318
3.3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter........................................................................ 321
3.3.10 Controlling a Peak Current Mode Controlled Buck Module................................................................................... 324
3.3.11 Controlling H-Bridge LLC Resonant Converter......................................................................................................326
3.4 Registers........................................................................................................................................................................ 328
3.4.1 Time-Base Submodule Registers............................................................................................................................ 328
3.4.2 Counter-Compare Submodule Registers................................................................................................................ 336
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3.4.3 Action-Qualifier Submodule Registers.....................................................................................................................342
3.4.4 Dead-Band Submodule Registers........................................................................................................................... 347
3.4.5 Trip-Zone Submodule Control and Status Registers............................................................................................... 350
3.4.6 Event-Trigger Submodule Registers........................................................................................................................359
3.4.7 PWM-Chopper Submodule Control Register...........................................................................................................365
3.4.8 Digital Compare Submodule Registers................................................................................................................... 367
3.4.9 Proper Interrupt Initialization Procedure.................................................................................................................. 375
4 High-Resolution Pulse Width Modulator (HRPWM).........................................................................................................377
4.1 Introduction.................................................................................................................................................................... 378
4.2 Operational Description of HRPWM...............................................................................................................................379
4.2.1 Controlling the HRPWM Capabilities.......................................................................................................................380
4.2.2 Configuring the HRPWM......................................................................................................................................... 383
4.2.3 Principle of Operation.............................................................................................................................................. 384
4.2.4 Scale Factor Optimizing Software (SFO)................................................................................................................ 392
4.2.5 HRPWM Examples Using Optimized Assembly Code............................................................................................ 392
4.3 SFO Library Software - SFO_TI_Build_V6.lib................................................................................................................397
4.3.1 Scale Factor Optimizer Function - int SFO()........................................................................................................... 397
4.3.2 Software Usage....................................................................................................................................................... 398
4.3.3 SFO Library Version Software Differences..............................................................................................................400
4.4 HRPWM Registers......................................................................................................................................................... 401
4.4.1 HRPWM Configuration (HRCNFG) Register........................................................................................................... 401
4.4.2 High Resolution Micro Step (HRMSTEP) Register..................................................................................................402
4.4.3 High Resolution Period Control (HRPCTL) Register............................................................................................... 404
5 High-Resolution Capture (HRCAP) Module......................................................................................................................405
5.1 Introduction.................................................................................................................................................................... 406
5.1.1 Features.................................................................................................................................................................. 406
5.1.2 HRCAP Related Collateral...................................................................................................................................... 406
5.2 Description..................................................................................................................................................................... 406
5.3 Operational Details.........................................................................................................................................................407
5.3.1 HRCAP Clocking..................................................................................................................................................... 407
5.3.2 HRCAP Modes of Operation................................................................................................................................... 408
5.3.3 HRCAP Interrupts....................................................................................................................................................412
5.4 HRCAP Calibration Library............................................................................................................................................ 413
5.4.1 HRCAP Calibration Library Functions..................................................................................................................... 414
5.4.2 HRCAP Calibration Library Software Usage........................................................................................................... 419
5.5 HRCAP Register Descriptions....................................................................................................................................... 421
5.5.1 HRCAP Control Register (HCCTL)..........................................................................................................................422
5.5.2 HRCAP Interrupt Flag Register (HCIFR).................................................................................................................423
5.5.3 HRCAP Interrupt Clear Register (HCICLR).............................................................................................................424
5.5.4 HRCAP Interrupt Force Register (HCIFRC)............................................................................................................ 425
5.5.5 HRCAP Counter Register (HCCOUNTER)............................................................................................................. 426
5.5.6 HRCAP Capture Counter On Rising Edge 0 Register (HCCAPCNTRISE0)........................................................... 427
5.5.7 HRCAP Capture Counter On Falling Edge 0 Register (HCCAPCNTFALL0).......................................................... 427
5.5.8 HRCAP Capture Counter On Rising Edge 1 Register (HCCAPCNTRISE1)........................................................... 428
5.5.9 HRCAP Capture Counter On Falling Edge 1 Register (HCCAPCNTFALL1).......................................................... 428
6 Enhanced Capture (eCAP)................................................................................................................................................. 429
6.1 Introduction.................................................................................................................................................................... 430
6.1.1 Features.................................................................................................................................................................. 430
6.1.2 ECAP Related Collateral......................................................................................................................................... 430
6.2 Description..................................................................................................................................................................... 430
6.3 Capture and APWM Operating Mode............................................................................................................................ 432
6.4 Capture Mode Description............................................................................................................................................. 434
6.4.1 Event Prescaler....................................................................................................................................................... 435
6.4.2 Edge Polarity Select and Qualifier...........................................................................................................................436
6.4.3 Continuous/One-Shot Control................................................................................................................................. 436
6.4.4 32-Bit Counter and Phase Control...........................................................................................................................437
6.4.5 CAP1-CAP4 Registers............................................................................................................................................ 437
6.4.6 Interrupt Control.......................................................................................................................................................438
6.4.7 DMA Interrupt.......................................................................................................................................................... 439
6.4.8 Shadow Load and Lockout Control......................................................................................................................... 440
6.4.9 APWM Mode Operation...........................................................................................................................................440
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6.5 Application of the eCAP Module.................................................................................................................................... 442
6.5.1 Example 1 - Absolute Time-Stamp Operation Rising Edge Trigger.........................................................................442
6.5.2 Example 2 - Absolute Time-Stamp Operation Rising and Falling Edge Trigger......................................................443
6.5.3 Example 3 - Time Difference (Delta) Operation Rising Edge Trigger...................................................................... 444
6.5.4 Example 4 - Time Difference (Delta) Operation Rising and Falling Edge Trigger................................................... 445
6.6 Application of the APWM Mode..................................................................................................................................... 446
6.6.1 Example 1 - Simple PWM Generation (Independent Channel/s)............................................................................ 446
6.7 eCAP Registers..............................................................................................................................................................446
6.7.1 ECAP Base Address Table......................................................................................................................................446
6.7.2 ECAP_REGS Registers.......................................................................................................................................... 447
7 Enhanced Quadrature Encoder Pulse (eQEP)................................................................................................................. 461
7.1 Introduction.................................................................................................................................................................... 462
7.1.1 EQEP Related Collateral......................................................................................................................................... 464
7.2 Configuring Device Pins.................................................................................................................................................464
7.3 Description..................................................................................................................................................................... 465
7.3.1 EQEP Inputs............................................................................................................................................................465
7.3.2 Functional Description............................................................................................................................................. 466
7.3.3 eQEP Memory Map................................................................................................................................................. 467
7.4 Quadrature Decoder Unit (QDU)....................................................................................................................................468
7.4.1 Position Counter Input Modes................................................................................................................................. 468
7.4.2 eQEP Input Polarity Selection................................................................................................................................. 471
7.4.3 Position-Compare Sync Output............................................................................................................................... 471
7.5 Position Counter and Control Unit (PCCU).................................................................................................................... 471
7.5.1 Position Counter Operating Modes......................................................................................................................... 471
7.5.2 Position Counter Latch............................................................................................................................................ 474
7.5.3 Position Counter Initialization.................................................................................................................................. 476
7.5.4 eQEP Position-compare Unit...................................................................................................................................476
7.6 eQEP Edge Capture Unit............................................................................................................................................... 478
7.7 eQEP Watchdog.............................................................................................................................................................482
7.8 eQEP Unit Timer Base................................................................................................................................................... 482
7.9 eQEP Interrupt Structure................................................................................................................................................483
7.10 eQEP Registers........................................................................................................................................................... 483
7.10.1 eQEP Base Addresses..........................................................................................................................................483
7.10.2 EQEP_REGS Registers........................................................................................................................................ 484
8 Analog-to-Digital Converter (ADC)....................................................................................................................................509
8.1 Introduction.................................................................................................................................................................... 510
8.1.1 Features.................................................................................................................................................................. 510
8.1.2 ADC Related Collateral........................................................................................................................................... 510
8.1.3 Block Diagram......................................................................................................................................................... 512
8.2 SOC Principle of Operation............................................................................................................................................513
8.2.1 ADC Acquisition (Sample and Hold) Window..........................................................................................................514
8.2.2 Trigger Operation.....................................................................................................................................................519
8.2.3 Channel Selection................................................................................................................................................... 519
8.3 ONESHOT Single Conversion Support..........................................................................................................................519
8.4 ADC Conversion Priority................................................................................................................................................ 520
8.5 Sequential Sampling Mode............................................................................................................................................ 523
8.6 Simultaneous Sampling Mode....................................................................................................................................... 523
8.7 EOC and Interrupt Operation......................................................................................................................................... 524
8.8 Power-Up Sequence...................................................................................................................................................... 525
8.9 ADC Calibration............................................................................................................................................................. 525
8.9.1 Factory Settings and Calibration Function...............................................................................................................525
8.9.2 ADC Zero Offset Calibration....................................................................................................................................525
8.9.3 ADC Full Scale Gain Calibration............................................................................................................................. 526
8.9.4 ADC Bias Current Calibration..................................................................................................................................526
8.10 Internal/External Reference Voltage Selection.............................................................................................................526
8.10.1 Internal Reference Voltage.................................................................................................................................... 526
8.10.2 External Reference Voltage...................................................................................................................................527
8.11 ADC Timings................................................................................................................................................................ 527
8.12 Internal Temperature Sensor........................................................................................................................................532
8.12.1 Transfer Function...................................................................................................................................................532
8.13 ADC Registers............................................................................................................................................................. 534
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8.13.1 ADC Control Register 1 (ADCCTL1)..................................................................................................................... 535
8.13.2 ADC Control Register 2 (ADCCTL2)..................................................................................................................... 537
8.13.3 ADC Interrupt Registers........................................................................................................................................ 538
8.13.4 ADC Start of Conversion Priority Control Register (SOCPRICTL)........................................................................ 545
8.13.5 ADC SOC Registers.............................................................................................................................................. 547
8.13.6 ADC Calibration Registers.....................................................................................................................................556
8.13.7 Comparator Hysteresis Control Register (COMPHYSTCTL)................................................................................ 557
8.13.8 ADC Revision Register (ADCREV)....................................................................................................................... 558
8.13.9 ADC RESULT0-RESULT15 Registers (ADCRESULTx)........................................................................................ 558
9 Comparator (COMP)........................................................................................................................................................... 559
9.1 Introduction.................................................................................................................................................................... 560
9.1.1 Features.................................................................................................................................................................. 560
9.1.2 Block Diagram......................................................................................................................................................... 560
9.2 Comparator Function..................................................................................................................................................... 561
9.3 DAC Reference.............................................................................................................................................................. 561
9.4 Ramp Generator Input................................................................................................................................................... 562
9.5 Initialization.................................................................................................................................................................... 563
9.6 Digital Domain Manipulation.......................................................................................................................................... 563
9.7 Comparator Registers.................................................................................................................................................... 564
9.7.1 Comparator Control (COMPCTL) Register..............................................................................................................565
9.7.2 Compare Output Status (COMPSTS) Register....................................................................................................... 566
9.7.3 DAC Control (DACCTL) Register............................................................................................................................ 566
9.7.4 DAC Value (DACVAL) Register............................................................................................................................... 567
9.7.5 Ramp Generator Maximum Reference Active (RAMPMAXREF_ACTIVE) Register...............................................567
9.7.6 Ramp Generator Maximum Reference Shadow (RAMPMAXREF_SHDW) Register............................................. 567
9.7.7 Ramp Generator Decrement Value Active (RAMPDECVAL_ACTIVE) Register..................................................... 568
9.7.8 Ramp Generator Decrement Value Shadow (RAMPDECVAL_SHDW) Register.................................................... 568
9.7.9 Ramp Generator Status (RAMPSTS) Register....................................................................................................... 568
10 Control Law Accelerator (CLA)........................................................................................................................................569
10.1 Introduction.................................................................................................................................................................. 570
10.1.1 Features................................................................................................................................................................ 570
10.1.2 CLA Related Collateral.......................................................................................................................................... 570
10.1.3 Block Diagram....................................................................................................................................................... 571
10.2 CLA Interface............................................................................................................................................................... 572
10.2.1 CLA Memory..........................................................................................................................................................572
10.2.2 CLA Memory Bus.................................................................................................................................................. 573
10.2.3 Shared Peripherals and EALLOW Protection........................................................................................................573
10.2.4 CLA Tasks and Interrupt Vectors........................................................................................................................... 574
10.3 CLA and CPU Arbitration............................................................................................................................................. 575
10.3.1 CLA Message RAM............................................................................................................................................... 575
10.3.2 CLA Program Memory...........................................................................................................................................576
10.3.3 CLA Data Memory................................................................................................................................................. 576
10.3.4 Peripheral Registers (ePWM, HRPWM, Comparator, eCAP, eQEP).................................................................... 577
10.4 CLA Configuration and Debug..................................................................................................................................... 578
10.4.1 Building a CLA Application.................................................................................................................................... 578
10.4.2 Typical CLA Initialization Sequence...................................................................................................................... 579
10.4.3 Debugging CLA Code............................................................................................................................................580
10.4.4 CLA Illegal Opcode Behavior................................................................................................................................ 581
10.4.5 Resetting the CLA................................................................................................................................................. 582
10.5 Pipeline........................................................................................................................................................................ 582
10.5.1 Pipeline Overview..................................................................................................................................................582
10.5.2 CLA Pipeline Alignment.........................................................................................................................................583
10.5.3 Parallel Instructions............................................................................................................................................... 587
10.6 Instruction Set.............................................................................................................................................................. 588
10.6.1 Instruction Descriptions......................................................................................................................................... 588
10.6.2 Addressing Modes and Encoding..........................................................................................................................589
10.6.3 Instructions............................................................................................................................................................ 591
10.7 CLA Registers.............................................................................................................................................................. 709
10.7.1 Register Memory Mapping.................................................................................................................................... 709
10.7.2 Task Interrupt Vector Registers............................................................................................................................. 710
10.7.3 Configuration Registers......................................................................................................................................... 711
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10.7.4 Execution Registers...............................................................................................................................................724
11 Direct Memory Access (DMA) Module............................................................................................................................ 727
11.1 Introduction...................................................................................................................................................................728
11.2 DMA Overview..............................................................................................................................................................728
11.3 Architecture.................................................................................................................................................................. 729
11.3.1 Block Diagram........................................................................................................................................................729
11.3.2 Peripheral Interrupt Event Trigger Sources........................................................................................................... 730
11.3.3 DMA Bus................................................................................................................................................................731
11.4 Pipeline Timing and Throughput...................................................................................................................................732
11.5 CPU Arbitration.............................................................................................................................................................733
11.6 Channel Priority............................................................................................................................................................733
11.6.1 Round-Robin Mode................................................................................................................................................733
11.6.2 Channel 1 High Priority Mode................................................................................................................................734
11.7 Address Pointer and Transfer Control.......................................................................................................................... 735
11.8 Overrun Detection Feature...........................................................................................................................................739
11.9 DMA Registers............................................................................................................................................................. 740
11.9.1 DMA Control Register (DMACTRL) — EALLOW Protected.................................................................................. 741
11.9.2 Debug Control Register (DEBUGCTRL) — EALLOW Protected...........................................................................743
11.9.3 Revision Register (REVISION).............................................................................................................................. 743
11.9.4 Priority Control Register 1 (PRIORITYCTRL1) — EALLOW Protected.................................................................744
11.9.5 Priority Status Register (PRIORITYSTAT)............................................................................................................. 745
11.9.6 Mode Register (MODE) — EALLOW Protected.................................................................................................... 746
11.9.7 Control Register (CONTROL) — EALLOW Protected...........................................................................................748
11.9.8 Burst Size Register (BURST_SIZE) — EALLOW Protected..................................................................................750
11.9.9 BURST_COUNT Register......................................................................................................................................750
11.9.10 Source Burst Step Register Size (SRC_BURST_STEP) — EALLOW Protected................................................751
11.9.11 Destination Burst Step Register Size (DST_BURST_STEP) — EALLOW Protected..........................................752
11.9.12 Transfer Size Register (TRANSFER_SIZE) — EALLOW Protected................................................................... 752
11.9.13 Transfer Count Register (TRANSFER_COUNT)................................................................................................. 753
11.9.14 Source Transfer Step Size Register (SRC_TRANSFER_STEP) — EALLOW Protected....................................753
11.9.15 Destination Transfer Step Size Register (DST_TRANSFER_STEP) — EALLOW Protected............................. 754
11.9.16 Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE) — EALLOW protected)...............................755
11.9.17 Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT)............................................................. 755
11.9.18 Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP) — EALLOW Protected.................... 756
11.9.19 Shadow Source Begin and Current Address Pointer Registers (SRC_BEG_ADDR_SHADOW/
DST_BEG_ADDR_SHADOW) — All EALLOW Protected............................................................................................757
11.9.20 Active Source Begin and Current Address Pointer Registers (SRC_BEG_ADDR/DST_BEG_ADDR)............... 757
11.9.21 Shadow Destination Begin and Current Address Pointer Registers (SRC_ADDR_SHADOW/
DST_ADDR_SHADOW) — All EALLOW Protected..................................................................................................... 758
11.9.22 Active Destination Begin and Current Address Pointer Registers (SRC_ADDR/DST_ADDR)............................758
12 Serial Peripheral Interface (SPI)...................................................................................................................................... 759
12.1 Introduction.................................................................................................................................................................. 760
12.1.1 Features................................................................................................................................................................ 760
12.1.2 Block Diagram....................................................................................................................................................... 761
12.2 System-Level Integration............................................................................................................................................. 762
12.2.1 SPI Module Signals............................................................................................................................................... 762
12.2.2 Configuring Device Pins........................................................................................................................................ 762
12.2.3 SPI Interrupts.........................................................................................................................................................763
12.2.4 DMA Support......................................................................................................................................................... 764
12.3 SPI Operation...............................................................................................................................................................766
12.3.1 Introduction to Operation....................................................................................................................................... 766
12.3.2 Master Mode..........................................................................................................................................................768
12.3.3 Slave Mode............................................................................................................................................................768
12.3.4 Data Format...........................................................................................................................................................769
12.3.5 Baud Rate Selection..............................................................................................................................................770
12.3.6 SPI Clocking Schemes.......................................................................................................................................... 771
12.3.7 SPI FIFO Description.............................................................................................................................................772
12.3.8 SPI 3-Wire Mode Description................................................................................................................................ 773
12.4 Programming Procedure.............................................................................................................................................. 775
12.4.1 Initialization Upon Reset........................................................................................................................................775
12.4.2 Configuring the SPI............................................................................................................................................... 775
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12.4.3 Data Transfer Example..........................................................................................................................................776
12.4.4 SPI 3-Wire Mode Code Examples.........................................................................................................................777
12.4.5 SPI STEINV Bit in Digital Audio Transfers.............................................................................................................778
12.5 SPI Registers............................................................................................................................................................... 779
12.5.1 SPI Base Addresses..............................................................................................................................................779
12.5.2 SPI_REGS Registers............................................................................................................................................ 779
13 Serial Communications Interface (SCI).......................................................................................................................... 799
13.1 Introduction.................................................................................................................................................................. 800
13.1.1 Features................................................................................................................................................................ 800
13.1.2 SCI Related Collateral........................................................................................................................................... 801
13.1.3 Block Diagram....................................................................................................................................................... 801
13.2 Architecture.................................................................................................................................................................. 801
13.3 SCI Module Signal Summary....................................................................................................................................... 801
13.4 Configuring Device Pins...............................................................................................................................................802
13.5 Multiprocessor and Asynchronous Communication Modes......................................................................................... 803
13.6 SCI Programmable Data Format..................................................................................................................................803
13.7 SCI Multiprocessor Communication.............................................................................................................................804
13.7.1 Recognizing the Address Byte.............................................................................................................................. 804
13.7.2 Controlling the SCI TX and RX Features...............................................................................................................804
13.7.3 Receipt Sequence................................................................................................................................................. 804
13.8 Idle-Line Multiprocessor Mode..................................................................................................................................... 805
13.8.1 Idle-Line Mode Steps.............................................................................................................................................805
13.8.2 Block Start Signal.................................................................................................................................................. 805
13.8.3 Wake-UP Temporary (WUT) Flag..........................................................................................................................806
13.8.4 Receiver Operation................................................................................................................................................806
13.9 Address-Bit Multiprocessor Mode................................................................................................................................ 807
13.9.1 Sending an Address.............................................................................................................................................. 807
13.10 SCI Communication Format.......................................................................................................................................808
13.10.1 Receiver Signals in Communication Modes........................................................................................................ 808
13.10.2 Transmitter Signals in Communication Modes.................................................................................................... 809
13.11 SCI Port Interrupts......................................................................................................................................................810
13.12 SCI Baud Rate Calculations.......................................................................................................................................810
13.13 SCI Enhanced Features............................................................................................................................................. 811
13.13.1 SCI FIFO Description...........................................................................................................................................811
13.13.2 SCI Auto-Baud.....................................................................................................................................................813
13.13.3 Autobaud-Detect Sequence................................................................................................................................ 813
13.14 SCI Registers............................................................................................................................................................. 814
13.14.1 SCI Base Addresses........................................................................................................................................... 814
13.14.2 SCI_REGS Registers.......................................................................................................................................... 814
14 Inter-Integrated Circuit Module (I2C)...............................................................................................................................833
14.1 Introduction.................................................................................................................................................................. 834
14.1.1 I2C Related Collateral........................................................................................................................................... 834
14.1.2 Features................................................................................................................................................................ 835
14.1.3 Features Not Supported........................................................................................................................................ 835
14.1.4 Functional Overview.............................................................................................................................................. 836
14.1.5 Clock Generation...................................................................................................................................................837
14.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)......................................................................................... 838
14.2 Configuring Device Pins...............................................................................................................................................839
14.3 I2C Module Operational Details................................................................................................................................... 839
14.3.1 Input and Output Voltage Levels........................................................................................................................... 839
14.3.2 Data Validity...........................................................................................................................................................839
14.3.3 Operating Modes................................................................................................................................................... 839
14.3.4 I2C Module START and STOP Conditions............................................................................................................ 843
14.3.5 Non-repeat Mode versus Repeat Mode................................................................................................................ 844
14.3.6 Serial Data Formats...............................................................................................................................................845
14.3.7 Clock Synchronization........................................................................................................................................... 847
14.3.8 Arbitration.............................................................................................................................................................. 848
14.3.9 Digital Loopback Mode.......................................................................................................................................... 849
14.3.10 NACK Bit Generation...........................................................................................................................................850
14.4 Interrupt Requests Generated by the I2C Module....................................................................................................... 851
14.4.1 Basic I2C Interrupt Requests.................................................................................................................................851
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14.4.2 I2C FIFO Interrupts................................................................................................................................................853
14.5 Resetting or Disabling the I2C Module.........................................................................................................................853
14.6 I2C Registers............................................................................................................................................................... 853
14.6.1 I2C Base Address Table........................................................................................................................................ 853
14.6.2 I2C_REGS Registers.............................................................................................................................................854
15 Multichannel Buffered Serial Port (McBSP)................................................................................................................... 877
15.1 Introduction.................................................................................................................................................................. 878
15.1.1 Features of the McBSP......................................................................................................................................... 878
15.1.2 McBSP Pins/Signals..............................................................................................................................................879
15.2 McBSP Operation........................................................................................................................................................ 880
15.2.1 Data Transfer Process of McBSP..........................................................................................................................880
15.2.2 Companding (Compressing and Expanding) Data................................................................................................ 881
15.2.3 Clocking and Framing Data................................................................................................................................... 883
15.2.4 Frame Phases....................................................................................................................................................... 885
15.3 McBSP Sample Rate Generator.................................................................................................................................. 890
15.3.1 Block Diagram....................................................................................................................................................... 890
15.3.2 Frame Synchronization Generation in the Sample Rate Generator...................................................................... 893
15.3.3 Synchronizing Sample Rate Generator Outputs to an External Clock.................................................................. 893
15.3.4 Reset and Initialization Procedure for the Sample Rate Generator.......................................................................895
15.4 McBSP Exception/Error Conditions............................................................................................................................. 896
15.4.1 Types of Errors...................................................................................................................................................... 896
15.4.2 Overrun in the Receiver.........................................................................................................................................897
15.4.3 Unexpected Receive Frame-Synchronization Pulse............................................................................................. 898
15.4.4 Overwrite in the Transmitter.................................................................................................................................. 900
15.4.5 Unexpected Transmit Frame-Synchronization Pulse............................................................................................ 902
15.5 Multichannel Selection Modes..................................................................................................................................... 904
15.5.1 Channels, Blocks, and Partitions...........................................................................................................................904
15.5.2 Multichannel Selection...........................................................................................................................................905
15.5.3 Configuring a Frame for Multichannel Selection....................................................................................................905
15.5.4 Using Two Partitions..............................................................................................................................................905
15.5.5 Using Eight Partitions............................................................................................................................................ 907
15.5.6 Receive Multichannel Selection Mode...................................................................................................................908
15.5.7 Transmit Multichannel Selection Modes................................................................................................................ 909
15.6 SPI Operation Using the Clock Stop Mode.................................................................................................................. 912
15.6.1 SPI Protocol...........................................................................................................................................................912
15.6.2 Clock Stop Mode................................................................................................................................................... 912
15.6.3 Bits Used to Enable and Configure the Clock Stop Mode..................................................................................... 913
15.6.4 Clock Stop Mode Timing Diagrams....................................................................................................................... 914
15.6.5 Procedure for Configuring a McBSP for SPI Operation.........................................................................................916
15.6.6 McBSP as the SPI Master..................................................................................................................................... 917
15.6.7 McBSP as an SPI Slave........................................................................................................................................ 918
15.7 Receiver Configuration.................................................................................................................................................919
15.7.1 Programming the McBSP Registers for the Desired Receiver Operation............................................................. 919
15.7.2 Resetting and Enabling the Receiver.................................................................................................................... 920
15.7.3 Set the Receiver Pins to Operate as McBSP Pins................................................................................................ 920
15.7.4 Enable/Disable the Digital Loopback Mode...........................................................................................................921
15.7.5 Enable/Disable the Clock Stop Mode.................................................................................................................... 921
15.7.6 Enable/Disable the Receive Multichannel Selection Mode................................................................................... 922
15.7.7 Choose One or Two Phases for the Receive Frame............................................................................................. 922
15.7.8 Set the Receive Word Length(s)............................................................................................................................923
15.7.9 Set the Receive Frame Length..............................................................................................................................923
15.7.10 Enable/Disable the Receive Frame-Synchronization Ignore Function................................................................ 924
15.7.11 Set the Receive Companding Mode.................................................................................................................... 925
15.7.12 Set the Receive Data Delay................................................................................................................................ 926
15.7.13 Set the Receive Sign-Extension and Justification Mode..................................................................................... 928
15.7.14 Set the Receive Interrupt Mode...........................................................................................................................929
15.7.15 Set the Receive Frame-Synchronization Mode................................................................................................... 930
15.7.16 Set the Receive Frame-Synchronization Polarity................................................................................................ 932
15.7.17 Set the Receive Clock Mode............................................................................................................................... 934
15.7.18 Set the Receive Clock Polarity............................................................................................................................ 935
15.7.19 Set the SRG Clock Divide-Down Value............................................................................................................... 936
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15.7.20 Set the SRG Clock Synchronization Mode..........................................................................................................937
15.7.21 Set the SRG Clock Mode (Choose an Input Clock).............................................................................................937
15.7.22 Set the SRG Input Clock Polarity........................................................................................................................ 938
15.8 Transmitter Configuration.............................................................................................................................................938
15.8.1 Programming the McBSP Registers for the Desired Transmitter Operation......................................................... 938
15.8.2 Resetting and Enabling the Transmitter................................................................................................................ 939
15.8.3 Set the Transmitter Pins to Operate as McBSP Pins............................................................................................ 940
15.8.4 Enable/Disable the Digital Loopback Mode...........................................................................................................940
15.8.5 Enable/Disable the Clock Stop Mode.................................................................................................................... 940
15.8.6 Enable/Disable Transmit Multichannel Selection...................................................................................................941
15.8.7 Choose One or Two Phases for the Transmit Frame............................................................................................ 942
15.8.8 Set the Transmit Word Length(s)...........................................................................................................................942
15.8.9 Set the Transmit Frame Length............................................................................................................................. 943
15.8.10 Enable/Disable the Transmit Frame-Synchronization Ignore Function............................................................... 944
15.8.11 Set the Transmit Companding Mode................................................................................................................... 945
15.8.12 Set the Transmit Data Delay................................................................................................................................946
15.8.13 Set the Transmit DXENA Mode........................................................................................................................... 948
15.8.14 Set the Transmit Interrupt Mode.......................................................................................................................... 948
15.8.15 Set the Transmit Frame-Synchronization Mode.................................................................................................. 949
15.8.16 Set the Transmit Frame-Synchronization Polarity............................................................................................... 950
15.8.17 Set the SRG Frame-Synchronization Period and Pulse Width............................................................................951
15.8.18 Set the Transmit Clock Mode.............................................................................................................................. 952
15.8.19 Set the Transmit Clock Polarity........................................................................................................................... 952
15.9 Emulation and Reset Considerations...........................................................................................................................954
15.9.1 McBSP Emulation Mode........................................................................................................................................954
15.9.2 Resetting and Initializing McBSP...........................................................................................................................954
15.10 Data Packing Examples............................................................................................................................................. 956
15.10.1 Data Packing Using Frame Length and Word Length......................................................................................... 956
15.10.2 Data Packing Using Word Length and the Frame-Synchronization Ignore Function.......................................... 958
15.11 McBSP_REGS Registers........................................................................................................................................... 959
16 Controller Area Network (CAN)....................................................................................................................................... 999
16.1 Introduction................................................................................................................................................................ 1000
16.1.1 Features.............................................................................................................................................................. 1000
16.1.2 ECAN Related Collateral..................................................................................................................................... 1000
16.1.3 Block Diagram..................................................................................................................................................... 1001
16.2 eCAN Compatibility With Other TI CAN Modules...................................................................................................... 1001
16.3 CAN Network and Module..........................................................................................................................................1002
16.3.1 CAN Protocol Overview.......................................................................................................................................1002
16.4 eCAN Controller Overview......................................................................................................................................... 1004
16.4.1 Standard CAN Controller (SCC) Mode................................................................................................................1004
16.4.2 Memory Map........................................................................................................................................................1005
16.5 Message Objects....................................................................................................................................................... 1007
16.6 Message Mailbox....................................................................................................................................................... 1007
16.6.1 Transmit Mailbox................................................................................................................................................. 1009
16.6.2 Receive Mailbox.................................................................................................................................................. 1010
16.6.3 CAN Module Operation in Normal Configuration.................................................................................................1010
16.7 eCAN Configuration................................................................................................................................................... 1010
16.7.1 CAN Module Initialization.................................................................................................................................... 1010
16.7.2 Steps to Configure eCAN.................................................................................................................................... 1014
16.7.3 Handling of Remote Frame Mailboxes................................................................................................................ 1016
16.7.4 Interrupts............................................................................................................................................................. 1017
16.7.5 CAN Power-Down Mode..................................................................................................................................... 1022
16.8 Acceptance Filter....................................................................................................................................................... 1023
16.8.1 Local-Acceptance Masks (CANLAM).................................................................................................................. 1024
16.9 eCAN Registers......................................................................................................................................................... 1025
16.9.1 Mailbox Enable Register (CANME)..................................................................................................................... 1025
16.9.2 Mailbox-Direction Register (CANMD)..................................................................................................................1025
16.9.3 Transmission-Request Set Register (CANTRS)..................................................................................................1026
16.9.4 Transmission-Request-Reset Register (CANTRR)............................................................................................. 1027
16.9.5 Transmission-Acknowledge Register (CANTA)................................................................................................... 1027
16.9.6 Abort-Acknowledge Register (CANAA)............................................................................................................... 1028
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16.9.7 Received-Message-Pending Register (CANRMP).............................................................................................. 1028
16.9.8 Received-Message-Lost Register (CANRML).....................................................................................................1029
16.9.9 Remote-Frame-Pending Register (CANRFP)..................................................................................................... 1029
16.9.10 Global Acceptance Mask Register (CANGAM)................................................................................................. 1031
16.9.11 Master Control Register (CANMC).................................................................................................................... 1032
16.9.12 Bit-Timing Configuration Register (CANBTC)....................................................................................................1035
16.9.13 Error and Status Register (CANES).................................................................................................................. 1037
16.9.14 CAN Error Counter Registers (CANTEC/CANREC)..........................................................................................1039
16.9.15 Interrupt Registers............................................................................................................................................. 1040
16.9.16 Overwrite Protection Control Register (CANOPC)............................................................................................ 1045
16.9.17 eCAN I/O Control Registers (CANTIOC, CANRIOC)........................................................................................ 1046
16.9.18 Timer Management Unit.................................................................................................................................... 1047
16.9.19 Mailbox Layout.................................................................................................................................................. 1050
16.10 Message Data Registers (CANMDL, CANMDH)..................................................................................................... 1053
17 Universal Serial Bus (USB) Controller..........................................................................................................................1055
17.1 Introduction................................................................................................................................................................ 1056
17.1.1 Features.............................................................................................................................................................. 1056
17.1.2 USB Related Collateral........................................................................................................................................1058
17.2 Functional Description................................................................................................................................................1058
17.2.1 Operation as a Device......................................................................................................................................... 1058
17.2.2 Operation as a Host.............................................................................................................................................1062
17.2.3 DMA Operation....................................................................................................................................................1066
17.2.4 Address/Data Bus Bridge.................................................................................................................................... 1066
17.3 Initialization and Configuration................................................................................................................................... 1068
17.3.1 Pin Configuration................................................................................................................................................. 1068
17.3.2 Endpoint Configuration........................................................................................................................................ 1069
17.4 USB Global Interrupts................................................................................................................................................ 1069
17.5 USB Registers............................................................................................................................................................1069
17.5.1 USB Device Functional Address Register (USBFADDR), offset 0x000...............................................................1072
17.5.2 USB Power Management Register (USBPOWER), offset 0x001........................................................................1073
17.5.3 USB Transmit Interrupt Status Register (USBTXIS), offset 0x002...................................................................... 1075
17.5.4 USB Receive Interrupt Status Register (USBRXIS), offset 0x004.......................................................................1076
17.5.5 USB Transmit Interrupt Enable Register (USBTXIE), offset 0x006..................................................................... 1077
17.5.6 USB Receive Interrupt Enable Register (USBRXIE), offset 0x008......................................................................1078
17.5.7 USB General Interrupt Status Register (USBIS), offset 0x00A........................................................................... 1079
17.5.8 USB Interrupt Enable Register (USBIE), offset 0x00B........................................................................................ 1081
17.5.9 USB Frame Value Register (USBFRAME), offset 0x00C....................................................................................1083
17.5.10 USB Endpoint Index Register (USBEPIDX), offset 0x00E................................................................................ 1083
17.5.11 USB Test Mode Register (USBTEST), offset 0x00F..........................................................................................1084
17.5.12 USB FIFO Endpoint n Register (USBFIFO[0]-USBFIFO[3])..............................................................................1086
17.5.13 USB Device Control Register (USBDEVCTL), offset 0x060..............................................................................1087
17.5.14 USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ), offset 0x062................................................. 1089
17.5.15 USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ), offset 0x063..................................................1090
17.5.16 USB Transmit FIFO Start Address Register (USBTXFIFOADD), offset 0x064................................................. 1091
17.5.17 USB Receive FIFO Start Address Register (USBRXFIFOADD), offset 0x066..................................................1092
17.5.18 USB Connect Timing Register (USBCONTIM), offset 0x07A............................................................................1093
17.5.19 USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF), offset 0x07D....................1094
17.5.20 USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF), offset 0x07E................... 1094
17.5.21 USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[0]-USBTXFUNCADDR[3])..... 1095
17.5.22 USB Transmit Hub Address Endpoint n Registers (USBTXHUBADDR[0]-USBTXHUBADDR[3]).................... 1096
17.5.23 USB Transmit Hub Port Endpoint n Registers (USBTXHUBPORT[0]-USBTXHUBPORT[3])........................... 1097
17.5.24 USB Receive Functional Address Endpoint n Registers (USBRXFUNCADDR[1]-USBRXFUNCADDR[3)...... 1098
17.5.25 USB Receive Hub Address Endpoint n Registers (USBRXHUBADDR[1]-USBRXHUBADDR[3)..................... 1099
17.5.26 USB Receive Hub Port Endpoint n Registers (USBRXHUBPORT[1]-USBRXHUBPORT[3])........................... 1100
17.5.27 USB Maximum Transmit Data Endpoint n Registers (USBTXMAXP[1]-USBTXMAXP[3])................................ 1101
17.5.28 USB Control and Status Endpoint 0 Low Register (USBCSRL0), offset 0x102.................................................1102
17.5.29 USB Control and Status Endpoint 0 High Register (USBCSRH0), offset 0x103............................................... 1105
17.5.30 USB Receive Byte Count Endpoint 0 Register (USBCOUNT0), offset 0x108...................................................1107
17.5.31 USB Type Endpoint 0 Register (USBTYPE0), offset 0x10A.............................................................................. 1107
17.5.32 USB NAK Limit Register (USBNAKLMT), offset 0x10B.....................................................................................1108
17.5.33 USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[1]-USBTXCSRL[3).......................1109
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17.5.34 USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[1]-USBTXCSRH[3]).................... 1112
17.5.35 USB Maximum Receive Data Endpoint n Registers (USBRXMAXP[1]-USBRXMAXP[3])................................ 1114
17.5.36 USB Receive Control and Status Endpoint n Low Register (USBRXCSRL[1]-USBRXCSRL[3)....................... 1115
17.5.37 USB Receive Control and Status Endpoint n High Register (USBRXCSRH[1]-USBRXCSRH[3]).................... 1118
17.5.38 USB Receive Byte Count Endpoint n Registers (USBRXCOUNT[1]-USBRXCOUNT[3).................................. 1120
17.5.39 USB Host Transmit Configure Type Endpoint n Register (USBTXTYPE[1]-USBTXTYPE[3])...........................1121
17.5.40 USB Host Transmit Interval Endpoint n Register (USBTXINTERVAL[1]USBTXINTERVAL[3]).........................1122
17.5.41 USB Host Configure Receive Type Endpoint n Register (USBRXTYPE[1]-USBRXTYPE[3])........................... 1123
17.5.42 USB Host Receive Polling Interval Endpoint n Register (USBRXINTERVAL[1]-USBRXINTERVAL[3])............ 1124
17.5.43 USB Request Packet Count in Block Transfer Endpoint n Registers (USBRQPKTCOUNT[1]-
USBRQPKTCOUNT[3)................................................................................................................................................1125
17.5.44 USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS), offset 0x340........................... 1126
17.5.45 USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS), offset 0x342...........................1127
17.5.46 USB External Power Control Register (USBEPC), offset 0x400....................................................................... 1128
17.5.47 USB External Power Control Raw Interrupt Status Register (USBEPCRIS), offset 0x404................................1130
17.5.48 USB External Power Control Interrupt Mask Register (USBEPCIM), offset 0x408........................................... 1131
17.5.49 USB External Power Control Interrupt Status and Clear Register (USBEPCISC), offset 0x40C.......................1132
17.5.50 USB Device RESUME Raw Interrupt Status Register (USBDRRIS), offset 0x410........................................... 1133
17.5.51 USB Device RESUME Raw Interrupt Mask Register (USBDRIM), offset 0x414...............................................1134
17.5.52 USB Device RESUME Interrupt Status and Clear Register (USBDRISC), offset 0x418...................................1135
17.5.53 USB General-Purpose Control and Status Register (USBGPCS), offset 0x41C...............................................1136
17.5.54 USB DMA Select Register (USBDMASEL), offset 0x450..................................................................................1137
18 Revision History..............................................................................................................................................................1139
List of Figures
Figure 1-1. Flash Power Mode State Diagram.......................................................................................................................... 42
Figure 1-2. Flash Pipeline..........................................................................................................................................................44
Figure 1-3. Flash Configuration Access Flow Diagram............................................................................................................. 45
Figure 1-4. Flash Options Register (FOPT)...............................................................................................................................47
Figure 1-5. Flash Power Register (FPWR)................................................................................................................................ 47
Figure 1-6. Flash Status Register (FSTATUS)...........................................................................................................................48
Figure 1-7. Flash Standby Wait Register (FSTDBYWAIT).........................................................................................................49
Figure 1-8. Flash Standby to Active Wait Counter Register (FACTIVEWAIT)........................................................................... 49
Figure 1-9. Flash Wait-State Register (FBANKWAIT)............................................................................................................... 50
Figure 1-10. OTP Wait-State Register (FOTPWAIT)................................................................................................................. 51
Figure 1-11. Password Match Flow (PMF).................................................................................................................................57
Figure 1-12. CSM Status and Control Register (CSMSCR)...................................................................................................... 61
Figure 1-13. Clock and Reset Domains.....................................................................................................................................62
Figure 1-14. Peripheral Clock Control 0 Register (PCLKCR0).................................................................................................. 63
Figure 1-15. Peripheral Clock Control 1 Register (PCLKCR1).................................................................................................. 65
Figure 1-16. Peripheral Clock Control 2 Register (PCLKCR2).................................................................................................. 67
Figure 1-17. Peripheral Clock Control 3 Register (PCLKCR3).................................................................................................. 68
Figure 1-18. Low-Speed Peripheral Clock Prescaler Register (LOSPCP)................................................................................ 69
Figure 1-19. Clocking Options................................................................................................................................................... 70
Figure 1-20. Internal Oscillator Trim n (INTOSCnTRIM) Register............................................................................................. 71
Figure 1-21. Clocking (XCLK) Register..................................................................................................................................... 72
Figure 1-22. Clock Control (CLKCTL) Register......................................................................................................................... 73
Figure 1-23. OSC and PLL Block.............................................................................................................................................. 76
Figure 1-24. PLLCR Change Procedure Flow Chart................................................................................................................. 77
Figure 1-25. PLLCR Register Layout.........................................................................................................................................78
Figure 1-26. PLL Status Register (PLLSTS)..............................................................................................................................79
Figure 1-27. PLL Lock Period (PLLLOCKPRD) Register.......................................................................................................... 81
Figure 1-28. PLL2 Input and Output Configurations.................................................................................................................. 82
Figure 1-29. PLL2 Configuration (PLL2CTL) Register...............................................................................................................82
Figure 1-30. PLL2 Multiplier (PLL2MULT) Register...................................................................................................................83
Figure 1-31. PLL2 Lock Status (PLL2STS) Register................................................................................................................. 83
Figure 1-32. SYSCLK2 Clock Counter (SYSCLK2CNTR) Register.......................................................................................... 84
Figure 1-33. EPWM DMA/CLA Configuration (EPWMCFG) Register....................................................................................... 84
Figure 1-34. Clocking and Reset Logic......................................................................................................................................85
Figure 1-35. Clock Fail Interrupt................................................................................................................................................ 88
Figure 1-36. NMI Configuration (NMICFG) Register................................................................................................................. 89
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Figure 1-37. NMI Flag (NMIFLG) Register.................................................................................................................................90
Figure 1-38. NMI Flag Clear (NMIFLGCLR) Register................................................................................................................90
Figure 1-39. NMI Flag Force (NMIFLGFRC) Register...............................................................................................................91
Figure 1-40. NMI Watchdog Counter (NMIWDCNT) Register................................................................................................... 91
Figure 1-41. NMI Watchdog Period (NMIWDPRD) Register..................................................................................................... 92
Figure 1-42. XCLKOUT Generation...........................................................................................................................................93
Figure 1-43. Low-Power Mode Control 0 Register (LPMCR0).................................................................................................. 95
Figure 1-44. CPU Watchdog Module......................................................................................................................................... 96
Figure 1-45. System Control and Status Register (SCSR)........................................................................................................99
Figure 1-46. Watchdog Counter Register (WDCNTR).............................................................................................................100
Figure 1-47. Watchdog Reset Key Register (WDKEY)............................................................................................................100
Figure 1-48. Watchdog Control Register (WDCR)...................................................................................................................101
Figure 1-49. CPU-Timers.........................................................................................................................................................102
Figure 1-50. CPU-Timer Interrupts Signals and Output Signal................................................................................................102
Figure 1-51. TIMERxTIM Register (x = 0, 1, 2)........................................................................................................................104
Figure 1-52. TIMERxTIMH Register (x = 0, 1, 2).....................................................................................................................104
Figure 1-53. TIMERxPRD Register (x = 0, 1, 2)...................................................................................................................... 105
Figure 1-54. TIMERxPRDH Register (x = 0, 1, 2)....................................................................................................................105
Figure 1-55. TIMERxTCR Register (x = 0, 1, 2)...................................................................................................................... 105
Figure 1-56. TIMERxTPR Register (x = 0, 1, 2).......................................................................................................................107
Figure 1-57. TIMERxTPRH Register (x = 0, 1, 2)....................................................................................................................107
Figure 1-58. General GPIO Multiplexing Diagram................................................................................................................... 108
Figure 1-59. GPIO32, GPIO33 Multiplexing Diagram..............................................................................................................109
Figure 1-60. JTAG Port/GPIO Multiplexing.............................................................................................................................. 110
Figure 1-61. JTAGDEBUG Register (Address 0x702A, EALLOW protected).......................................................................... 111
Figure 1-62. Analog/GPIO Multiplexing....................................................................................................................................112
Figure 1-63. Input Qualification Using a Sampling Window.....................................................................................................117
Figure 1-64. Input Qualifier Clock Cycles.................................................................................................................................119
Figure 1-65. GPIO Port A MUX 1 (GPAMUX1) Register......................................................................................................... 124
Figure 1-66. GPIO Port A MUX 2 (GPAMUX2) Register......................................................................................................... 127
Figure 1-67. GPIO Port B MUX 1 (GPBMUX1) Register......................................................................................................... 130
Figure 1-68. GPIO Port B MUX 2 (GPBMUX2) Register......................................................................................................... 132
Figure 1-69. Analog I/O MUX (AIOMUX1) Register................................................................................................................ 134
Figure 1-70. GPIO Port A Qualification Control (GPACTRL) Register.....................................................................................135
Figure 1-71. GPIO Port B Qualification Control (GPBCTRL) Register.................................................................................... 136
Figure 1-72. GPIO A Control Register 2 Register (GPACTRL2)..............................................................................................137
Figure 1-73. GPIO Port A Qualification Select 1 (GPAQSEL1) Register.................................................................................138
Figure 1-74. GPIO Port A Qualification Select 2 (GPAQSEL2) Register.................................................................................139
Figure 1-75. GPIO Port B Qualification Select 1 (GPBQSEL1) Register.................................................................................140
Figure 1-76. GPIO Port B Qualification Select 2 (GPBQSEL2) Register.................................................................................141
Figure 1-77. GPIO Port A Direction (GPADIR) Register..........................................................................................................142
Figure 1-78. GPIO Port B Direction (GPBDIR) Register..........................................................................................................143
Figure 1-79. Analog I/O DIR (AIODIR) Register...................................................................................................................... 144
Figure 1-80. GPIO Port A Pullup Disable (GPAPUD) Registers..............................................................................................145
Figure 1-81. GPIO Port B Pullup Disable (GPBPUD) Registers..............................................................................................146
Figure 1-82. GPIO Port A Data (GPADAT) Register................................................................................................................147
Figure 1-83. GPIO Port B Data (GPBDAT) Register................................................................................................................148
Figure 1-84. Analog I/O DAT (AIODAT) Register.....................................................................................................................149
Figure 1-85. GPIO Port A Set, Clear and Toggle (GPASET, GPACLEAR, GPATOGGLE) Registers......................................150
Figure 1-86. GPIO Port B Set, Clear and Toggle (GPBSET, GPBCLEAR, GPBTOGGLE) Registers.....................................152
Figure 1-87. Analog I/O Toggle (AIOSET, AIOCLEAR, AIOTOGGLE) Register......................................................................154
Figure 1-88. GPIO XINTn Interrupt Select (GPIOXINTnSEL) Registers................................................................................. 155
Figure 1-89. GPIO Low Power Mode Wakeup Select (GPIOLPMSEL) Register.....................................................................156
Figure 1-90. Device Configuration (DEVICECNF) Register.................................................................................................... 163
Figure 1-91. Part ID Register...................................................................................................................................................164
Figure 1-92. REVID Register................................................................................................................................................... 165
Figure 1-93. Overview: Multiplexing of Interrupts Using the PIE Block................................................................................... 167
Figure 1-94. Typical PIE/CPU Interrupt Response - INTx.y.....................................................................................................169
Figure 1-95. Reset Flow Diagram............................................................................................................................................171
Figure 1-96. PIE Interrupt Sources and External Interrupts XINT1/XINT2/XINT3................................................................... 172
Figure 1-97. Multiplexed Interrupt Request Flow Diagram...................................................................................................... 175
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Figure 1-98. PIECTRL Register (Address 0xCE0).................................................................................................................. 182
Figure 1-99. PIE Interrupt Acknowledge Register (PIEACK) Register (Address 0xCE1)........................................................ 182
Figure 1-100. PIEIFRx Register (x = 1 to 12).......................................................................................................................... 183
Figure 1-101. PIEIERx Register (x = 1 to 12).......................................................................................................................... 184
Figure 1-102. Interrupt Flag Register (IFR) — CPU Register..................................................................................................185
Figure 1-103. Interrupt Enable Register (IER) — CPU Register............................................................................................. 188
Figure 1-104. Debug Interrupt Enable Register (DBGIER) — CPU Register.......................................................................... 190
Figure 1-105. External Interrupt n Control Register (XINTnCR).............................................................................................. 192
Figure 1-106. External Interrupt n Counter (XINTnCTR) (Address 7078h)............................................................................. 193
Figure 1-107. BOR Configuration (BORCFG) Register........................................................................................................... 194
Figure 2-1. F2806x Memory Map of On-Chip ROM.................................................................................................................196
Figure 2-2. F2806xM/2806xF Memory Map of On-Chip ROM.................................................................................................197
Figure 2-3. Vector Table Map...................................................................................................................................................200
Figure 2-4. Bootloader Flow Diagram......................................................................................................................................202
Figure 2-5. Boot ROM Stack....................................................................................................................................................204
Figure 2-6. Boot ROM Function Overview...............................................................................................................................206
Figure 2-7. Bootloader Basic Transfer Procedure................................................................................................................... 217
Figure 2-8. Overview of InitBoot Assembly Function...............................................................................................................218
Figure 2-9. Overview of the SelectBootMode Function........................................................................................................... 219
Figure 2-10. Overview of Get_mode() Function...................................................................................................................... 220
Figure 2-11. Overview of CopyData Function..........................................................................................................................221
Figure 2-12. Overview of SCI Bootloader Operation............................................................................................................... 221
Figure 2-13. Overview of SCI_Boot Function.......................................................................................................................... 222
Figure 2-14. Overview of SCI_GetWordData Function............................................................................................................223
Figure 2-15. Overview of Parallel GPIO Bootloader Operation............................................................................................... 223
Figure 2-16. Parallel GPIO Boot Loader Handshake Protocol................................................................................................ 224
Figure 2-17. Parallel GPIO Mode Overview............................................................................................................................ 225
Figure 2-18. Parallel GPIO Mode - Host Transfer Flow........................................................................................................... 225
Figure 2-19. 8-Bit Parallel GetWord Function..........................................................................................................................226
Figure 2-20. SPI Loader.......................................................................................................................................................... 227
Figure 2-21. Data Transfer From EEPROM Flow.................................................................................................................... 229
Figure 2-22. Overview of SPIA_GetWordData Function..........................................................................................................229
Figure 2-23. EEPROM Device at Address 0x50......................................................................................................................230
Figure 2-24. Overview of I2C_Boot Function...........................................................................................................................231
Figure 2-25. Random Read..................................................................................................................................................... 232
Figure 2-26. Sequential Read..................................................................................................................................................232
Figure 2-27. Overview of eCAN-A bootloader Operation........................................................................................................ 233
Figure 2-28. ExitBoot Procedure Flow.....................................................................................................................................235
Figure 3-1. Multiple ePWM Modules........................................................................................................................................244
Figure 3-2. Submodules and Signal Connections for an ePWM Module.................................................................................245
Figure 3-3. ePWM Submodules and Critical Internal Signal Interconnects............................................................................. 246
Figure 3-4. Time-Base Submodule Block Diagram..................................................................................................................251
Figure 3-5. Time-Base Submodule Signals and Registers...................................................................................................... 252
Figure 3-6. Time-Base Frequency and Period.........................................................................................................................254
Figure 3-7. Time-Base Counter Synchronization Scheme 1....................................................................................................255
Figure 3-8. Time-Base Up-Count Mode Waveforms................................................................................................................257
Figure 3-9. Time-Base Down-Count Mode Waveforms........................................................................................................... 258
Figure 3-10. Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down On Synchronization Event...........258
Figure 3-11. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up On Synchronization Event................259
Figure 3-12. Counter-Compare Submodule............................................................................................................................ 260
Figure 3-13. Detailed View of the Counter-Compare Submodule............................................................................................260
Figure 3-14. Counter-Compare Event Waveforms in Up-Count Mode.................................................................................... 263
Figure 3-15. Counter-Compare Events in Down-Count Mode.................................................................................................263
Figure 3-16. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down On Synchronization
Event.................................................................................................................................................................................... 264
Figure 3-17. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up On Synchronization
Event.................................................................................................................................................................................... 264
Figure 3-18. Action-Qualifier Submodule.................................................................................................................................265
Figure 3-19. Action-Qualifier Submodule Inputs and Outputs................................................................................................. 266
Figure 3-20. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs..............................................................267
Figure 3-21. Up-Down-Count Mode Symmetrical Waveform...................................................................................................270
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Figure 3-22. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and EPWMxB—Active
High......................................................................................................................................................................................271
Figure 3-23. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and EPWMxB—Active
Low.......................................................................................................................................................................................272
Figure 3-24. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA......................274
Figure 3-25. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Active Low.......................................................................................................................................................275
Figure 3-26. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Complementary...............................................................................................................................................276
Figure 3-27. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active Low277
Figure 3-28. Dead-Band Submodule....................................................................................................................................... 278
Figure 3-29. Configuration Options for the Dead-Band Submodule........................................................................................ 279
Figure 3-30. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)......................................................................... 281
Figure 3-31. PWM-Chopper Submodule................................................................................................................................. 282
Figure 3-32. PWM-Chopper Submodule Operational Details..................................................................................................283
Figure 3-33. Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only................................................283
Figure 3-34. PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses...............284
Figure 3-35. PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining Pulses.. 285
Figure 3-36. Trip-Zone Submodule..........................................................................................................................................286
Figure 3-37. Trip-Zone Submodule Mode Control Logic..........................................................................................................290
Figure 3-38. Trip-Zone Submodule Interrupt Logic..................................................................................................................291
Figure 3-39. Event-Trigger Submodule....................................................................................................................................292
Figure 3-40. Event-Trigger Submodule Inter-Connectivity of ADC Start of Conversion.......................................................... 293
Figure 3-41. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs.......................................................... 293
Figure 3-42. Event-Trigger Interrupt Generator....................................................................................................................... 295
Figure 3-43. Event-Trigger SOCA Pulse Generator................................................................................................................ 296
Figure 3-44. Event-Trigger SOCB Pulse Generator................................................................................................................ 296
Figure 3-45. Digital-Compare Submodule High-Level Block Diagram.....................................................................................297
Figure 3-46. DCAEVT1 Event Triggering.................................................................................................................................299
Figure 3-47. DCAEVT2 Event Triggering.................................................................................................................................299
Figure 3-48. DCBEVT1 Event Triggering.................................................................................................................................300
Figure 3-49. DCBEVT2 Event Triggering.................................................................................................................................300
Figure 3-50. Event Filtering..................................................................................................................................................... 301
Figure 3-51. Blanking Window Timing Diagram.......................................................................................................................302
Figure 3-52. Simplified ePWM Module.................................................................................................................................... 302
Figure 3-53. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave......................................................... 303
Figure 3-54. Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 ................................................................. 304
Figure 3-55. Buck Waveforms for Figure 3-54 (Note: Only three bucks shown here)............................................................. 305
Figure 3-56. Control of Four Buck Stages. (Note: FPWM2 = N x FPWM1).................................................................................. 307
Figure 3-57. Buck Waveforms for Figure 3-56 (Note: FPWM2 = FPWM1)).................................................................................. 308
Figure 3-58. Control of Two Half-H Bridge Stages (FPWM2 = N x FPWM1)................................................................................ 310
Figure 3-59. Half-H Bridge Waveforms for Figure 3-58 (Note: Here FPWM2 = FPWM1 )............................................................ 311
Figure 3-60. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control..............................................313
Figure 3-61. 3-Phase Inverter Waveforms for Figure 3-60 (Only One Inverter Shown).......................................................... 314
Figure 3-62. Configuring Two PWM Modules for Phase Control............................................................................................. 316
Figure 3-63. Timing Waveforms Associated With Phase Control Between 2 Modules............................................................317
Figure 3-64. Control of a 3-Phase Interleaved DC/DC Converter........................................................................................... 318
Figure 3-65. 3-Phase Interleaved DC/DC Converter Waveforms for Figure 3-64 .................................................................. 319
Figure 3-66. Controlling a Full-H Bridge Stage (FPWM2 = FPWM1) ........................................................................................... 321
Figure 3-67. ZVS Full-H Bridge Waveforms............................................................................................................................ 322
Figure 3-68. Peak Current Mode Control of a Buck Converter................................................................................................324
Figure 3-69. Peak Current Mode Control Waveforms for Figure 3-68 .................................................................................... 324
Figure 3-70. Control of Two Resonant Converter Stages........................................................................................................326
Figure 3-71. H-Bridge LLC Resonant Converter PWM Waveforms.........................................................................................326
Figure 3-72. Time-Base Control Register (TBCTL)................................................................................................................. 328
Figure 3-73. Time-Base Status Register (TBSTS)...................................................................................................................330
Figure 3-74. Time-Base Phase High Resolution Register (TBPHSHR)...................................................................................331
Figure 3-75. Time-Base Phase Register (TBPHS).................................................................................................................. 331
Figure 3-76. Time-Base Counter Register (TBCTR)................................................................................................................332
Figure 3-77. Time-Base Period Register (TBPRD)..................................................................................................................332
Figure 3-78. Time Base Period High Resolution Register (TBPRDHR).................................................................................. 333
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Figure 3-79. Time-Base Period High Resolution Mirror Register (TBPRDHRM).....................................................................334
Figure 3-80. Time-Base Period Mirror Register (TBPRDM).................................................................................................... 335
Figure 3-81. Counter-Compare Control (CMPCTL) Register.................................................................................................. 336
Figure 3-82. Compare A High Resolution (CMPAHR) Register...............................................................................................337
Figure 3-83. Counter-Compare A (CMPA) Register................................................................................................................ 338
Figure 3-84. Counter-Compare B (CMPB) Register................................................................................................................ 339
Figure 3-85. Compare A High-Resolution Mirror (CMPAHRM) Register................................................................................. 340
Figure 3-86. Counter-Compare A Mirror (CMPAM) Register...................................................................................................341
Figure 3-87. Action-Qualifier Output A Control Register (AQCTLA)........................................................................................342
Figure 3-88. Action-Qualifier Output B Control Register (AQCTLB)........................................................................................343
Figure 3-89. Action-Qualifier Software Force Register (AQSFRC)..........................................................................................345
Figure 3-90. Action-Qualifier Continuous Software Force Register (AQCSFRC)....................................................................346
Figure 3-91. Dead-Band Generator Control (DBCTL) Register...............................................................................................347
Figure 3-92. Dead-Band Generator Rising Edge Delay (DBRED) Register............................................................................ 349
Figure 3-93. Dead-Band Generator Falling Edge Delay (DBFED) Register............................................................................349
Figure 3-94. Trip-Zone Select Register (TZSEL)..................................................................................................................... 350
Figure 3-95. Trip Zone Digital Compare Event Select Register (TZDCSEL)........................................................................... 351
Figure 3-96. Trip-Zone Control Register (TZCTL)................................................................................................................... 353
Figure 3-97. Trip-Zone Enable Interrupt Register (TZEINT).................................................................................................... 354
Figure 3-98. Trip-Zone Flag Register (TZFLG)........................................................................................................................355
Figure 3-99. Trip-Zone Clear Register (TZCLR)...................................................................................................................... 357
Figure 3-100. Trip-Zone Force Register (TZFRC)................................................................................................................... 358
Figure 3-101. Event-Trigger Selection Register (ETSEL)........................................................................................................359
Figure 3-102. Event-Trigger Prescale Register (ETPS)...........................................................................................................360
Figure 3-103. Event-Trigger Flag Register (ETFLG)............................................................................................................... 362
Figure 3-104. Event-Trigger Clear Register (ETCLR)..............................................................................................................363
Figure 3-105. Event-Trigger Force Register (ETFRC).............................................................................................................364
Figure 3-106. PWM-Chopper Control (PCCTL) Register........................................................................................................ 365
Figure 3-107. Digital Compare Trip Select (DCTRIPSEL) Register.........................................................................................367
Figure 3-108. Digital Compare A Control (DCACTL) Register................................................................................................ 369
Figure 3-109. Digital Compare B Control (DCBCTL) Register................................................................................................ 370
Figure 3-110. Digital Compare Filter Control (DCFCTL) Register........................................................................................... 371
Figure 3-111. Digital Compare Capture Control (DCCAPCTL) Register..................................................................................372
Figure 3-112. Digital Compare Filter Offset (DCFOFFSET) Register......................................................................................373
Figure 3-113. Digital Compare Filter Offset Counter (DCFOFFSETCNT) Register.................................................................373
Figure 3-114. Digital Compare Filter Window (DCFWINDOW) Register................................................................................. 374
Figure 3-115. Digital Compare Filter Window Counter (DCFWINDOWCNT) Register............................................................ 374
Figure 3-116. Digital Compare Counter Capture (DCCAP) Register.......................................................................................375
Figure 4-1. Resolution Calculations for Conventionally Generated PWM............................................................................... 378
Figure 4-2. Operating Logic Using MEP.................................................................................................................................. 379
Figure 4-3. HRPWM Extension Registers and Memory Configuration.................................................................................... 380
Figure 4-4. HRPWM System Interface.................................................................................................................................... 381
Figure 4-5. HRPWM Block Diagram........................................................................................................................................ 382
Figure 4-6. Required PWM Waveform for a Requested Duty = 30.0%....................................................................................384
Figure 4-7. Low % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0).................................................................. 387
Figure 4-8. High % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0)..................................................................388
Figure 4-9. Up-Count Duty Cycle Range Limitation Example (HRPCTL[HRPE]=1)................................................................388
Figure 4-10. Up-Down Count Duty Cycle Range Limitation Example (HRPCTL[HRPE]=1)....................................................389
Figure 4-11. Simple Buck Controlled Converter Using a Single PWM.....................................................................................393
Figure 4-12. PWM Waveform Generated for Simple Buck Controlled Converter.................................................................... 393
Figure 4-13. Simple Reconstruction Filter for a PWM Based DAC..........................................................................................395
Figure 4-14. PWM Waveform Generated for the PWM DAC Function.................................................................................... 395
Figure 4-15. HRPWM Configuration (HRCNFG) Register.......................................................................................................401
Figure 4-16. High Resolution Micro Step (HRMSTEP) Register............................................................................................. 402
Figure 4-17. High Resolution Period Control (HRPCTL) Register...........................................................................................404
Figure 5-1. HRCAP Module System Block Diagram................................................................................................................406
Figure 5-2. HRCAP Block Diagram......................................................................................................................................... 407
Figure 5-3. HCCAPCLK Generation........................................................................................................................................ 408
Figure 5-4. HCCOUNTER Behavior During High Pulse Width Capture.................................................................................. 408
Figure 5-5. Rise versus Fall Capture Events........................................................................................................................... 409
Figure 5-6. High Pulse Width Normal Mode Capture.............................................................................................................. 410
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Figure 5-7. Low Pulse Width Normal Mode Capture............................................................................................................... 410
Figure 5-8. HRCAP High-Resolution Mode Operating Logic................................................................................................... 411
Figure 5-9. Interrupts in HRCAP Module................................................................................................................................. 412
Figure 5-10. LowPulseWidth0 Capture on RISE and FALL Events......................................................................................... 415
Figure 5-11. HighPulseWidth0/1 Capture on RISE and FALL Events......................................................................................416
Figure 5-12. PeriodWidthRise0 and PeriodWidthFall0 Capture on RISE and FALL Events....................................................418
Figure 5-13. HRCAP Control Register (HCCTL)..................................................................................................................... 422
Figure 5-14. HRCAP Interrupt Flag Register (HCIFR).............................................................................................................423
Figure 5-15. HRCAP Interrupt Clear Register (HCICLR).........................................................................................................424
Figure 5-16. HRCAP Interrupt Force Register (HCIFRC)........................................................................................................425
Figure 5-17. HRCAP Counter Register (HCCOUNTER)......................................................................................................... 426
Figure 5-18. HRCAP Capture Counter On Rising Edge 0 Register (HCCAPCNTRISE0).......................................................427
Figure 5-19. HRCAP Capture Counter On Falling Edge 0 Register (HCCAPCNTFALL0)...................................................... 427
Figure 5-20. HRCAP Capture Counter On Rising Edge 1 Register (HCCAPCNTRISE1).......................................................428
Figure 5-21. HRCAP Capture Counter On Falling Edge 1 Register (HCCAPCNTFALL1)...................................................... 428
Figure 6-1. Multiple eCAP Modules In A C28x System........................................................................................................... 431
Figure 6-2. Capture and APWM Modes of Operation..............................................................................................................432
Figure 6-3. Counter Compare and PRD Effects on the eCAP Output in APWM Mode........................................................... 433
Figure 6-4. eCAP Block Diagram.............................................................................................................................................434
Figure 6-5. Event Prescale Control..........................................................................................................................................435
Figure 6-6. Prescale Function Waveforms...............................................................................................................................435
Figure 6-7. Details of the Continuous/One-shot Block.............................................................................................................436
Figure 6-8. Details of the Counter and Synchronization Block................................................................................................ 437
Figure 6-9. Interrupts in eCAP Module.................................................................................................................................... 439
Figure 6-10. PWM Waveform Details Of APWM Mode Operation...........................................................................................440
Figure 6-11. Time-Base Frequency and Period Calculation.................................................................................................... 441
Figure 6-12. Capture Sequence for Absolute Time-stamp and Rising Edge Detect................................................................442
Figure 6-13. Capture Sequence for Absolute Time-stamp With Rising and Falling Edge Detect............................................443
Figure 6-14. Capture Sequence for Delta Mode Time-stamp and Rising Edge Detect........................................................... 444
Figure 6-15. Capture Sequence for Delta Mode Time-stamp With Rising and Falling Edge Detect....................................... 445
Figure 6-16. PWM Waveform Details of APWM Mode Operation........................................................................................... 446
Figure 6-17. TSCTR Register.................................................................................................................................................. 448
Figure 6-18. CTRPHS Register............................................................................................................................................... 448
Figure 6-19. CAP1 Register.....................................................................................................................................................449
Figure 6-20. CAP2 Register.....................................................................................................................................................449
Figure 6-21. CAP3 Register.....................................................................................................................................................450
Figure 6-22. CAP4 Register.....................................................................................................................................................450
Figure 6-23. ECCTL1 Register................................................................................................................................................ 451
Figure 6-24. ECCTL2 Register................................................................................................................................................ 453
Figure 6-25. ECEINT Register.................................................................................................................................................455
Figure 6-26. ECFLG Register.................................................................................................................................................. 457
Figure 6-27. ECCLR Register..................................................................................................................................................459
Figure 6-28. ECFRC Register..................................................................................................................................................460
Figure 7-1. Optical Encoder Disk.............................................................................................................................................462
Figure 7-2. QEP Encoder Output Signal for Forward/Reverse Movement.............................................................................. 462
Figure 7-3. Index Pulse Example.............................................................................................................................................463
Figure 7-4. Functional Block Diagram of the eQEP Peripheral............................................................................................... 466
Figure 7-5. Functional Block Diagram of Decoder Unit........................................................................................................... 468
Figure 7-6. Quadrature Decoder State Machine......................................................................................................................469
Figure 7-7. Quadrature-clock and Direction Decoding............................................................................................................ 470
Figure 7-8. Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or 0xF9F)........................... 472
Figure 7-9. Position Counter Underflow/Overflow (QPOSMAX = 4)........................................................................................473
Figure 7-10. Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1)......................................................................475
Figure 7-11. Strobe Event Latch (QEPCTL[SEL] = 1)............................................................................................................. 475
Figure 7-12. eQEP Position-compare Unit.............................................................................................................................. 476
Figure 7-13. eQEP Position-compare Event Generation Points..............................................................................................477
Figure 7-14. eQEP Position-compare Sync Output Pulse Stretcher....................................................................................... 477
Figure 7-15. eQEP Edge Capture Unit.................................................................................................................................... 479
Figure 7-16. Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010)...................................................480
Figure 7-17. eQEP Edge Capture Unit - Timing Details.......................................................................................................... 480
Figure 7-18. eQEP Watchdog Timer........................................................................................................................................482
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Figure 7-19. eQEP Unit Timer Base........................................................................................................................................ 482
Figure 7-20. eQEP Interrupt Generation..................................................................................................................................483
Figure 7-21. QPOSCNT Register............................................................................................................................................ 486
Figure 7-22. QPOSINIT Register.............................................................................................................................................486
Figure 7-23. QPOSMAX Register............................................................................................................................................487
Figure 7-24. QPOSCMP Register............................................................................................................................................487
Figure 7-25. QPOSILAT Register............................................................................................................................................ 487
Figure 7-26. QPOSSLAT Register...........................................................................................................................................488
Figure 7-27. QPOSLAT Register............................................................................................................................................. 488
Figure 7-28. QUTMR Register.................................................................................................................................................488
Figure 7-29. QUPRD Register................................................................................................................................................. 489
Figure 7-30. QWDTMR Register..............................................................................................................................................489
Figure 7-31. QWDPRD Register..............................................................................................................................................490
Figure 7-32. QDECCTL Register.............................................................................................................................................491
Figure 7-33. QEPCTL Register................................................................................................................................................493
Figure 7-34. QCAPCTL Register............................................................................................................................................. 496
Figure 7-35. QPOSCTL Register.............................................................................................................................................497
Figure 7-36. QEINT Register................................................................................................................................................... 498
Figure 7-37. QFLG Register.................................................................................................................................................... 500
Figure 7-38. QCLR Register.................................................................................................................................................... 502
Figure 7-39. QFRC Register....................................................................................................................................................504
Figure 7-40. QEPSTS Register............................................................................................................................................... 506
Figure 7-41. QCTMR Register.................................................................................................................................................507
Figure 7-42. QCPRD Register................................................................................................................................................. 507
Figure 7-43. QCTMRLAT Register...........................................................................................................................................508
Figure 7-44. QCPRDLAT Register...........................................................................................................................................508
Figure 8-1. ADC Block Diagram.............................................................................................................................................. 512
Figure 8-2. SOC Block Diagram.............................................................................................................................................. 513
Figure 8-3. ADCINx Input Model..............................................................................................................................................515
Figure 8-4. ONESHOT Single Conversion.............................................................................................................................. 519
Figure 8-5. Round Robin Priority Example.............................................................................................................................. 521
Figure 8-6. High Priority Example............................................................................................................................................522
Figure 8-7. Interrupt Structure................................................................................................................................................. 524
Figure 8-8. Timing Example For Sequential Mode / Late Interrupt Pulse................................................................................ 527
Figure 8-9. Timing Example For Sequential Mode / Early Interrupt Pulse...............................................................................528
Figure 8-10. Timing Example For Simultaneous Mode / Late Interrupt Pulse......................................................................... 529
Figure 8-11. Timing Example For Simultaneous Mode / Early Interrupt Pulse........................................................................ 530
Figure 8-12. Timing Example for NONOVERLAP Mode..........................................................................................................531
Figure 8-13. Temperature Sensor Transfer Function...............................................................................................................532
Figure 8-14. ADC Control Register 1 (ADCCTL1)................................................................................................................... 535
Figure 8-15. ADC Control Register 2 (ADCCTL2)................................................................................................................... 537
Figure 8-16. ADC Interrupt Flag Register (ADCINTFLG)........................................................................................................ 538
Figure 8-17. ADC Interrupt Flag Clear Register (ADCINTFLGCLR)....................................................................................... 539
Figure 8-18. ADC Interrupt Overflow Register (ADCINTOVF).................................................................................................540
Figure 8-19. ADC Interrupt Overflow Clear Register (ADCINTOVFCLR)................................................................................541
Figure 8-20. Interrupt Select 1 and 2 Register (INTSEL1N2).................................................................................................. 542
Figure 8-21. Interrupt Select 3 and 4 Register (INTSEL3N4).................................................................................................. 542
Figure 8-22. Interrupt Select 5 and 6 Register (INTSEL5N6).................................................................................................. 542
Figure 8-23. Interrupt Select 7 and 8 Register (INTSEL7N8).................................................................................................. 543
Figure 8-24. Interrupt Select 9 and 10 Register (INTSEL9N10).............................................................................................. 543
Figure 8-25. ADC Start of Conversion Priority Control Register (SOCPRICTL)......................................................................545
Figure 8-26. ADC Sample Mode Register (ADCSAMPLEMODE)...........................................................................................547
Figure 8-27. ADC Interrupt Trigger SOC Select 1 Register (ADCINTSOCSEL1)....................................................................549
Figure 8-28. ADC Interrupt Trigger SOC Select 2 Register (ADCINTSOCSEL2)....................................................................549
Figure 8-29. ADC SOC Flag 1 Register (ADCSOCFLG1).......................................................................................................550
Figure 8-30. ADC SOC Force 1 Register (ADCSOCFRC1).................................................................................................... 551
Figure 8-31. ADC SOC Overflow 1 Register (ADCSOCOVF1)............................................................................................... 552
Figure 8-32. ADC SOC Overflow Clear 1 Register (ADCSOCOVFCLR1).............................................................................. 552
Figure 8-33. ADC SOC0-SOC15 Control Registers (ADCSOCxCTL).....................................................................................553
Figure 8-34. ADC Reference/Gain Trim Register (ADCREFTRIM)......................................................................................... 556
Figure 8-35. ADC Offset Trim Register (ADCOFFTRIM).........................................................................................................556
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Figure 8-36. Comparator Hysteresis Control Register (COMPHYSTCTL).............................................................................. 557
Figure 8-37. ADC Revision Register (ADCREV)..................................................................................................................... 558
Figure 8-38. ADC RESULT0-RESULT15 Registers (ADCRESULTx)......................................................................................558
Figure 9-1. Comparator Block Diagram................................................................................................................................... 560
Figure 9-2. Comparator........................................................................................................................................................... 561
Figure 9-3. Ramp Generator Block Diagram........................................................................................................................... 562
Figure 9-4. Ramp Generator Behavior.................................................................................................................................... 563
Figure 9-5. Comparator Control (COMPCTL) Register........................................................................................................... 565
Figure 9-6. Compare Output Status (COMPSTS) Register..................................................................................................... 566
Figure 9-7. DAC Control (DACCTL) Register.......................................................................................................................... 566
Figure 9-8. DAC Value (DACVAL) Register............................................................................................................................. 567
Figure 9-9. Ramp Generator Maximum Reference Active (RAMPMAXREF_ACTIVE) Register............................................ 567
Figure 9-10. Ramp Generator Maximum Reference Shadow (RAMPMAXREF_SHDW) Register......................................... 567
Figure 9-11. Ramp Generator Decrement Value Active (RAMPDECVAL_ACTIVE) Register................................................. 568
Figure 9-12. Ramp Generator Decrement Value Shadow (RAMPDECVAL_SHDW) Register................................................568
Figure 9-13. Ramp Generator Status (RAMPSTS) Register................................................................................................... 568
Figure 10-1. CLA (Type 0) Block Diagram...............................................................................................................................571
Figure 10-2. Task Interrupt Vector (MVECT1/2/3/4/5/6/7/8) Register...................................................................................... 710
Figure 10-3. Control Register (MCTL)......................................................................................................................................711
Figure 10-4. Memory Configuration Register (MMEMCFG).................................................................................................... 712
Figure 10-5. CLA Peripheral Interrupt Source Select 1 Register (MPISRCSEL1)...................................................................714
Figure 10-6. Interrupt Flag Register (MIFR)............................................................................................................................ 716
Figure 10-7. Interrupt Overflow Flag Register (MIOVF)...........................................................................................................717
Figure 10-8. Interrupt Force Register (MIFRC)........................................................................................................................718
Figure 10-9. Interrupt Flag Clear Register (MICLR)................................................................................................................ 719
Figure 10-10. Interrupt Overflow Flag Clear Register (MICLROVF)........................................................................................720
Figure 10-11. Interrupt Enable Register (MIER)...................................................................................................................... 721
Figure 10-12. Interrupt Run Status Register (MIRUN).............................................................................................................723
Figure 10-13. Program Counter (MPC)................................................................................................................................... 724
Figure 10-14. CLA Status Register (MSTF).............................................................................................................................724
Figure 11-1. DMA Block Diagram............................................................................................................................................ 729
Figure 11-2. Peripheral Interrupt Trigger Input Diagram.......................................................................................................... 730
Figure 11-3. 4-Stage Pipeline DMA Transfer........................................................................................................................... 732
Figure 11-4. 4-Stage Pipeline With One Read Stall (McBSP as source).................................................................................732
Figure 11-5. DMA State Diagram.............................................................................................................................................738
Figure 11-6. Overrun Detection Logic......................................................................................................................................739
Figure 11-7. DMA Control Register (DMACTRL).....................................................................................................................741
Figure 11-8. Debug Control Register (DEBUGCTRL)..............................................................................................................743
Figure 11-9. Revision Register (REVISION)............................................................................................................................743
Figure 11-10. Priority Control Register 1 (PRIORITYCTRL1)..................................................................................................744
Figure 11-11. Priority Status Register (PRIORITYSTAT)......................................................................................................... 745
Figure 11-12. Mode Register (MODE)..................................................................................................................................... 746
Figure 11-13. Control Register (CONTROL)............................................................................................................................748
Figure 11-14. Burst Size Register (BURST_SIZE).................................................................................................................. 750
Figure 11-15. Burst Count Register (BURST_COUNT)...........................................................................................................750
Figure 11-16. Source Burst Step Size Register (SRC_BURST_STEP)...................................................................................751
Figure 11-17. Destination Burst Step Register Size (DST_BURST_STEP)............................................................................ 752
Figure 11-18. Transfer Size Register (TRANSFER_SIZE)...................................................................................................... 752
Figure 11-19. Transfer Count Register (TRANSFER_COUNT)...............................................................................................753
Figure 11-20. Source Transfer Step Size Register (SRC_TRANSFER_STEP)...................................................................... 753
Figure 11-21. Destination Transfer Step Size Register (DST_TRANSFER_STEP)................................................................ 754
Figure 11-22. Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE).................................................................. 755
Figure 11-23. Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT)...........................................................755
Figure 11-24. Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP).......................................................756
Figure 11-25. Shadow Source Begin and Current Address Pointer Registers (SRC_BEG_ADDR_SHADOW/
DST_BEG_ADDR_SHADOW).............................................................................................................................................757
Figure 11-26. Active Source Begin and Current Address Pointer Registers (SRC_BEG_ADDR/DST_BEG_ADDR).............757
Figure 11-27. Shadow Destination Begin and Current Address Pointer Registers (SRC_ADDR_SHADOW/
DST_ADDR_SHADOW).......................................................................................................................................................758
Figure 11-28. Active Destination Begin and Current Address Pointer Registers (SRC_ADDR/DST_ADDR)......................... 758
Figure 12-1. SPI CPU Interface............................................................................................................................................... 761
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20 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
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