Description When SMCLK is used as the clock source for the ADC (ADC12CTL1.ADC12SSELx =
11) and CSCTL4.SMCLKOFF = 1, the ADC will stop operating if the ADC clock source is
changed by user software (e.g. in the ISR) from SMCLK to a different clock source. This
issue appears only for the ADC12CTL1.ADC12DIVx settings /3/5/7. The hang state can
be recovered by PUC/POR/BOR/Power cycle.
Workaround 1. Set CSCTL4.SMCLKOFF = 0 before switch ADC clock source.
OR
2. Only use ADC12CTL1.ADC12DIVx as /1, /2, /4, /6, /8
AUXPMM1 AUXPMM Module
Category Functional
Function AUXVCC1/AUXVCC2 can not be switched back to DVCC
Description When the system is running with the AUXVCC1 supply after DVCC/AVCC is lost, if the
AUXVCC1 voltage goes lower than SVSH setting for POR and above BORH level, the
system can not switch back to DVCC after DVCC ramps back up again.
Similarly, when the system is running with the AUXVCC2 supply after DVCC/AVCC is lost,
if the AUXVCC2 voltage goes lower than SVSH setting for POR and above BORH level,
the system can not switch back to DVCC after DVCC ramps back up again.
Workaround When the system is running with the AUXVCC1 supply, use SVMH to monitor AUXVCC1
voltage. When AUXVCC1 is lower than the SVMH setting, the program drives the chip
into LPMx.5. After DVCC ramps up back again, trigger one of the wake up pins. The
power supply could be switched back to DVCC again.
When the system is running with the AUXVCC2 supply, use SVMH to monitor AUXVCC2
voltage. When AUXVCC2 is lower than the SVMH setting, the program drives the chip
into LPMx.5. After DVCC ramps up back again, trigger one of the wake up pins. The
power supply could be switched back to DVCC again.
AUXPMM2 AUXPMM Module
Category Functional
Function Latch-up in AUXPMM
Description Latch-up current can appear at the AUXPMM module supply pins in the following two
scenarios:
Scenario 1: When the AUXPMM is configured for hardware- or software-controlled
switching and the module switches from DVCC to AUXVCC2, latch-up current can
appear at AUXVCC2 at the switching point defined by SVSMHCTL.SVSMHRRL (or
AUXCTL2.AUX0LVLx). The probability for this event to occur depends on:
a) Operating temperature (higher temperatures increase probability)
b) External AUXVCC2 voltage level (higher voltages increase probability)
c) SVSMHRRL level (lower levels increase probability) defining the switching level in
hardware-controlled mode
d) AUX0LVLx level (lower levels increase probability) defining the switching level in
software-controlled mode (applicable to DVCC only)
Scenario 2: When a battery is connected to DVCC, AUXVCC1 or AUXVCC2 as the first
voltage supply, due to the low internal resistance of the battery a very fast rise time is
www.ti.com Advisory Descriptions
SLAZ347AF – OCTOBER 2012 – REVISED MAY 2021
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MSP430F6734 Microcontroller 7
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