Texas Instruments SLVP125 EVM User manual

LDO Linear Regulator Design
Using the Universal SOT23
EVM
August 1999 Mixed Signal Products
User’s Guide
SLVU019

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Information About Cautions and Warnings
iii
Read This First
Preface
Read This First
About This Manual
This user’s guide describes techniques for designing low dropout voltage lin-
earregulators(LDO)usingTI’sSLVP125evaluationmodules(EVM)andTPS
76933 LDOs.
How to Use This Manual
This document contains the following chapters:
- Chapter 1 Introduction
- Chapter 2 EVM Adjustments and Test Points
- Chapter 3 Circuit Design
- Chapter 4 Test Results
Information About Cautions and Warnings
This book may contain cautions and warnings.
This is an example of a caution statement.
A caution statement describes a situation that could potentially
damage your software or equipment.
This is an example of a warning statement.
A warning statement describes a situation that could potentially
cause harm to you.

Related Documentation From Texas Instruments
iv
The information in a caution or a warning is provided for your protection.
Please read each caution and warning carefully.
Related Documentation From Texas Instruments
- TPS760xx, TPS761xx, TPS763xx, TPS764xx, TPS769xx, TPS770xx
data sheets (literature numbers SLVS144B, SLVS178A, SLVS181D,
SLVS180A, SLVS203B, SLVS210B)

Running Title—Attribute Reference
v
Chapter Title—Attribute Reference
Contents
1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Low Dropout Voltage Linear Regulator Circuit Operation 1-2. . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Design Strategy 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Schematic 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Bill of Materials 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Board Layout 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 EVM Adjustments and Test Points 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Adjustment by Switch 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Adjustment by Jumper 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Adjustment by Trimmer 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Adjustment by Programming Header 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Test Setup 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Circuit Design 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Adjusting the TPS76x01/TPS77001 Output Voltage 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Temperature Considerations 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 External Capacitor Requirements – ESR 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Test Results 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Test Results 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Running Title—Attribute Reference
vi
Figures
1–1 Typical LDO Application 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–2 SLVP125 EVM Universal LDO Tester Schematic Diagram 1-4. . . . . . . . . . . . . . . . . . . . . . . . . .
1–3 Top Layer 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–4 Bottom Layer (top view) 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–5 Assembly Drawing (top assembly) 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 Location of Adjustment Parts 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 Test Setup 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 Programming the TPS76x01/TPS77001 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 Resistor Values 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Calculated and Measured Maximum Output Current vs Input Voltage
Without Cooling for TPS76933 in Test Setup 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 ESR and ESL 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 LDO Output Stage With Parasitic Resistances ESR and ESL 3-8. . . . . . . . . . . . . . . . . . . . . . .
3–6 Correlation of Different ESRs and Their Influence to the Regulation of Vout at a
Load Step From Low to High Output Current 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 Rise Time of Function Generator at Gate of MOSFET Q1 (high speed) 4-2. . . . . . . . . . . . . . .
4–2 Rise Time of Function Generator at Gate of MOSFET Q1 (low speed) 4-2. . . . . . . . . . . . . . .
4–3 Transient at Input (Ch1); 4.3 V Input, 3.3 V Output (Ch2) at 100 mA Load,
Cout = 10 mF 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 Delay Time EN →Output High 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–5 Full Load (100 mA) – No Load Transition, ∆Vout, Whole Period 4-4. . . . . . . . . . . . . . . . . . . . .
4–6 Full Load (100 mA) – No Load Transition With Cout = 10 µF Electrolytic 4-4. . . . . . . . . . . . . .
4–7 No Load – Full Load (100 mA) Transition With Cout = 10 µF Electrolytic 4-5. . . . . . . . . . . . . .
Tables
1–1 Summary of LDO Families and Their Features 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–2 SLVP125 EVM Bill of Materials 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 Jumper Functions 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 Trimmer Adjustments 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 Timing Equations 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 Exact Resistor Values 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 E96 Resistor Series 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1
Introduction
Introduction
This user’s guide describes techniques for designing low dropout (LDO)
voltage linear regulators using TI’s SLVP125 evaluation module (EVM) and
TPS76933 LDO. LDOs provide ideal power supplies for rapidly transitioning
DSP loads such as the Texas Instruments TMS320C54x and similar
processors, and fast memory. Low quiescent current and very low dropout
voltage compared to standard LDOs makes the TPS76933 particularly
suitable in battery applications requiring extended lifetime and low cost.
Low noise power supplies, fast transient response, improved efficiency, low
component count, and easy design make LDOs popular in solutions where
switched converters are too noisy and standard linear regulators are too
inefficient.
Topic Page
1.1 Low Dropout Voltage Linear Regulator Circuit Operation 1–2. . . . . . . . .
1.2 Design Strategy 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Schematic 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Bill of Materials 1–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Board Layout 1–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1

Low Dropout Voltage Linear Regulator Circuit Operation
1-2
1.1 Low Dropout Voltage Linear Regulator Circuit Operation
Inthelowdropoutvoltagelinearregulatortopology,aPMOStransistoractsas
a pass element that reduces the normal 1.5-V to 2.5-V collector-to-emitter
drop to about 0.3 V or less. This improvement results in lower power
dissipation and higher efficiency when compared to other regulator designs.
The basic LDO regulator circuit includes the LDO and an output capacitor for
stabilization. Figure 1–1 shows the circuit of a typical LDO application.
Figure 1–1.Typical LDO Application
_
+
Control
_
+
R1
R2
Q1
Vref
LDO
CO
Vout
Load
_
+
VCC
In the LDO application shown in Figure 1–1, the LDO regulates the output
voltage Vout.
If Vout falls below the regulation level, the controller increases the VGS
differential and the PMOS conducts more current, resulting in an increase of
Vout. If Vout exceeds the regulation level, the controller decreases the VGS
differential and the PMOS conducts less current, resulting in a decrease of
Vout. The PMOS pass element acts like an adjustable resistor. The more
negative the gate becomes versus the source, the less the source-drain
resistance becomes, resulting in higher current flow through the PMOS.

Design Strategy
1-3
Introduction
1.2 Design Strategy
The TI SLVP125 EVM provides a circuit to simultaneously compare the
performance of two LDOs in a SOT23 package. The EVM provides proven,
demonstrated reference designs and test modes to aid in choosing and
evaluating LDOs. A programmable high speed transient generator generates
either line or load transients. The transient slew rate, and the impact of the
transients on the load/line are adjustable. A 10x amplifying operational
amplifier (op amp) makes measurements of the dropout voltages easier and
moreaccurate.To avoid influencing each other,eachLDOcanbepoweredby
its own power supply. Jumpers allow settings of minimum/maximum load as
well as device-enable and transient impact functions. There is enough room
on the EVM to evaluate different types of output capacitors including ESR
behaviors. Many test points allow the measuring of input, output, and dropout
voltage.
The EVM is shipped with a TPS76933 that provides a 3.3-V output voltage.
The maximum output current is 100 mA. The 100 mA-output power level is a
reasonable selection criteria for powering DSPs and battery-supplied
applications such as mobile phones and laptop cards.
The TPS760xx, TPS761xx, TPS763xx, TPS764xx, TPS769xx, TPS770xx
LDO family provides several output currents and voltages combined with
options like very low noise or high accuracy.
Table 1–1 summarizes the LDO families and their features.
Table 1–1.Summary of LDO Families and Their Features
TPS760xx TPS761xx TPS763xx TPS764xx TPS769xx TPS770xx
Maximum input voltage range [V] 16 (PNP) 10 (PMOS) 13.5(PMOS)
Maximum output current [mA] 50 100 150 150 100 50
Typical quiescent current [µA] 850 2600 85 17
Typical dropout voltage [mV] 120 210 300 71 35
Typical output noise [µVrms] 190 140 30 190
Accuracy over line, load, and
temperature 3% 2%
PSRR (at 1 kHz, CO= 10 µF,
TJ= 25°C) 60 dB
Package SOT23
External cap > 4.7 µF
Available Voltage Option [V] 3, 3.2, 3.3, 3.8, and 5
1.6, 1.8, 2.5,
2.7, 2.8, 3,
3.3, 3.8, 5,
and adj
2.5, 2.7,
2.8, 3, 3.3 1.2, 1.5, 1.8, 2.5, 2.7, 2.8, 3, 3.3, 5, and adj.
Performance Advantage Low dropout Low quiescent current,
low noise
Low dropout, ultra low
quiescent current, high
accuracy

Schematic
1-4
1.3 Schematic
Figure1–2 shows the SLVP125 EVM Universal LDO Tester (3.3 V output with
TPS76933 as U1) schematic diagram.
Figure 1–2.SLVP125 EVM Universal LDO Tester Schematic Diagram