Texas Instruments bq24292i User manual

User's Guide
SLUUA14A–October 2012–Revised April 2013
bq24190/2/2i/3/6 and bq24292i EVM (PWR021) User’s
Guide
Contents
1 Introduction .................................................................................................................. 2
1.1 EVM Features ...................................................................................................... 2
1.2 I/O Descriptions .................................................................................................... 2
2 Test Summary ............................................................................................................... 4
2.1 Equipment ........................................................................................................... 4
2.2 Equipment Setup ................................................................................................... 5
2.3 Procedure ........................................................................................................... 6
3 PCB Layout Guideline .................................................................................................... 10
4 Board Layout, Schematic, and Bill of Materials ....................................................................... 11
4.1 Board Layout ...................................................................................................... 11
4.2 Schematic ......................................................................................................... 17
4.3 Bill of Materials .................................................................................................... 18
List of Figures
1 Connections of the HPA172 Kit........................................................................................... 5
2 Original Test Setup for PWR021 (bq2419xEVM) ...................................................................... 5
3 Main Window of the bq2419x Evaluation Software .................................................................... 6
4 CHG Mode Ripple and Duty Cycle: VBUS = 5 V, VBAT = 3.7 V.......................................................... 8
5 Boost Mode Ripple and Duty Cycle; VBAT = 3.7 V ...................................................................... 9
6 bq24x9xEVM Top Layer.................................................................................................. 11
7 bq24x9xEVM Second Layer ............................................................................................. 12
8 bq24x9xEVM Third Layer ................................................................................................ 13
9 bq24x9xEVM Bottom Layer.............................................................................................. 14
10 bq24x9xEVM Top Assembly............................................................................................. 15
11 bq24x9xEVM Bottom Assembly......................................................................................... 16
12 bq24x9xEVM Schematic.................................................................................................. 17
List of Tables
1 EVM Connections........................................................................................................... 2
2 Jumper Connections........................................................................................................ 3
3 Recommended Operating Conditions.................................................................................... 3
4 Device ID JEITA Settings.................................................................................................. 9
5 Bill of Materials............................................................................................................. 18
Windows is a trademark of Microsoft Corporation.
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Introduction www.ti.com
1 Introduction
1.1 EVM Features
Refer to the data sheet (SLUSB97) for detailed features and operation.
The bq24x9x evaluation module (EVM) is a complete charger module for evaluating an I2C-controlled
single NVDC-1 charge using the bq24x9x devices.
This EVM doesn’t include the USB-to-GPIO interface board. To evaluate the bq24x9x EVM, a USB-to-
GPIO interface board must be ordered separately. For details, see the bq2419x data sheet (SLUSB97).
1.2 I/O Descriptions
Table 1 lists the jumper connections available on this EVM.
Table 1. EVM Connections
Jack Description
J1–PMID PMID pin connection/Power bank output
J1–VBUS Input: positive terminal
J1–GND Input: negative terminal (ground terminal)
J2-SYS Connected to system
J2-BAT+ Connected to battery pack
J2-GND Ground
J3 USB-to-GPIO connector (USB Interface Adapter Connector - HPA172)
J4–INT INT pin connection
J4– OTG OTG pin connection
J4-CE CE pin connection
J4-GND Ground
J5-TS2 External TS2 pin connection
J5-GND Ground
J6-TS1 External TS1 pin connection
J6-GND Ground
J7 Mini_USB Connector
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www.ti.com Introduction
Table 2 lists the controls and key parameter settings for this EVM.
Table 2. Jumper Connections
Jack Description Factory Setting
JP1 For bq24190/2/2i/3/6 and bq24292i input current setting: bq24190: Not installed
PSEL LOW: Adaptor input bq24190/2/2i/3/6 and bq24292i :
PSEL HIGH: USB input Short PSEL to LOW
JP2 D-/PG pin selection Bq24190: Short D-/PG to D-
bq24190/2/2i/3/6 and bq24292i :
Short D-/PG to PG
JP3 STAT, PG, /CE, INT, OTG pin internal pull-up source (VSYS) jumper Installed
JP4 USB current limit selection pin during buck mode and PSEL is high (JP1- Not installed
High)/Enable pin during boost mode.
In buck mode: OTG = High, IIN limit = 500 mA;
OTG = Low, IIN limit = 100 mA.
The boost mode is activated when the REG01[5:4] = 10 and OTG pin is
HIGH.
JP5 CE pin setting: pull low to enable the charge Not Installed
(GUI also can pull /CE low)
JP6 For bq24190 input current limit setting: bq24190: installed
bq24190/2/2i/3/6 and bq24292i :
Not installed
JP7 TS1 resistor divider pull-up source (REGN) connection Installed
JP8 internal 10k to ground to TS1 Installed
JP9 internal 10k to ground to TS2 Installed
JP10 TS2 pin setting: bq24193: Short TS2 and TS1
bq24190/2/2I/6 and bq24292i: Short
TS2 and TS2-I
Table 3 lists the recommended operating conditions for this EVM.
Table 3. Recommended Operating Conditions
Symbol Description MIN TYP MAX Unit
Supply voltage, VIN Input voltage from AC adapter input 3.9 5/12 17 V
Battery voltage, VBAT Voltage applied at VBAT terminal 0 3.7 4.25 V
Supply current, IAC Maximum input current from AC adapter 0 3 A
input
Output current, IOUT Output current 0 4 A
Operating junction temperature 0 125 °C
range, TJ
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Test Summary www.ti.com
2 Test Summary
Section 2.1 –Section 2.3 explains the equipment, the equipment setup, and the test procedures.
2.1 Equipment
2.1.1 Power Supplies
Power supply #1 (PS#1): a power supply capable of supplying 5 V at 1 A is required. While this part can
handle larger voltage and current, it is not necessary for this procedure.
2.1.2 Load #1 (4-Quadrant Supply, Constant Voltage < 4.5 V)
A 0–20 V/0–5 A, > 30-W system, DC electronic load and setting as constant voltage load mode.
Or:
Kepco load: BOP 20–5M, DC 0 to ±20 V, 0 to ±5 A (or higher)
Or:
Real single-cell battery
2.1.3 Load#2 – Use with Boost Mode
PMID to GND load, 10 Ω, 5 W or greater
2.1.4 Meters
Six Fluke 75 multimeters, (equivalent or better)
Or:
Four equivalent voltage meters and two equivalent current meters.
The current meters must be capable of measuring 5 A+ current.
2.1.5 Computer
A computer with at least one USB port and a USB cable. The bq2419xEVM evaluation software must be
properly installed.
2.1.6 USB-to-GPIO Communication Kit (HPA172-USB Interface Adapter)
2.1.7 Software
Unzip the bq2419xEVM_GUI.zip and double-click on the SETUP.EXE file. Follow the installation steps.
The software supports the Windows™ XP and Windows 7 operating systems.
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J4
To Computer
USB Port
USB Interface
Adapter
I/O
USB
10-pin
Ribbon Cable
‘To EVM’
Texas Instruments
©2006
www.ti.com Test Summary
2.2 Equipment Setup
1. Set PS#1 for 5-V DC, 1-A current limit and then turn off the supply.
2. Connect the output of PS#1 in series with a current meter (multimeter) to J1 (VBUS and GND).
3. Connect a voltage meter across J1 (VBUS) and J1 (GND).
4. Turn on the Load, set to constant voltage mode and output to 2.5 V. Turn off (disable) Load. Connect
Load in series with a current meter (multimeter), ground side, to J2 (BAT+ and GND) as shown in
Figure 2.
5. Connect a voltage meter across J2 (BAT+ and GND).
6. Connect the HPA172 USB interface adapter to the computer with a USB mini-cable and to J3 with the
10-pin ribbon cable. The connections are shown in Figure 1.
Figure 1. Connections of the HPA172 Kit
7. Install shunts as shown in Table 2.
Figure 2. Original Test Setup for PWR021 (bq2419xEVM)
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Test Summary www.ti.com
8. Turn on the computer. Launch the bq2419x evaluation software. The main window of the software is
shown in Figure 3.
Figure 3. Main Window of the bq2419x Evaluation Software
2.3 Procedure
2.3.1 Current Settings
1. Make Sure EQUIPMENT SETUP steps are followed.
ILIM Setting: Set the potentiometer to its lowest value for max input current by connecting an ohm-
meter between point TP9 and ground. Turn the screw on the potentiometer counterclockwise until the
resistance drops to its lowest point (this should be approximately 169 Ω, the value of R7)
2. Launch the BQ2419x EVM GUI software, if not already done
3. Turn on PS#1
Measure →V (J2(SYS), J2(GND)) = 4.10 ±300 mV
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www.ti.com Test Summary
2.3.2 Charge Voltage and Current Regulation of VIN and Device ID Verification
Follow the steps and verify the outputs and IC for the EVM.
2.3.2.1 Software setup (all of Section 2.3.2.1 is done in the GUI):
1. Device address: bq24190/192/192i/193/196 (6B) and bq24292i
2. Click the Read button
3. Select Disabled for I2C Watchdog Timer Limit
4. Set Input Voltage Limit to 4.2 V
5. Set Input Current Limit to 500 mA
6. Set Charge Voltage Limit to 4.208 V
7. Set Fast Charge Current, ICHG to 512 mA
8. Set Pre-Charge Current to 256 mA
9. Deselect Enable Termination (see the following image)
10. Click the Read button twice
Observe →Everything normal at FAULT box
Observe →D1 (STAT) is on, except the bq24192i/292iEVM
Observe →D2 (/PG) is on for bq24190/192/192i/193/196/292iEVM
2.3.2.2 Enable Load#1 from Section 2.2 step 4. Measure the voltage across J2 at two different points:
Measure →V(J2(SYS), J2(GND)) = 3.65 V ±300 mV
Measure →V(J2(BAT), J2(GND)) = 2.5V ±200 mV
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CHG Mode: VBUS = 5 V VBAT = 3.7 V
Vsw
Vsys_AC coupled
Vprnid_AC coupled
C2
C1
C3
Test Summary www.ti.com
2.3.2.3 Increase the Constant Voltage Load to 3.7 VDC
Measure →V(J2(SYS), J2(GND)) = 3.75 V ±200 mV
Measure →IBAT = 500 mA ±200 mA
Measure →V(J2(BAT), J2(GND)) = 3.7 V ±200 mV
2.3.2.4 In the software, set Fast Charge Current, ICHG to 1.012 A
Measure →Iin = 500 mA ±200 mA
2.3.2.5 Verify Scope Measurements (See Figure 4 – 500 ns/div)
C1 (AC coupled 20 mV/div): Vac_PMID (TP20 to GND) – Ripple excluding high frequency spikes < 10 mV
C2 (5 V/div): Vdc_SW (TP2) - Frequency between 1.25 MHz and 1.5 MHz, duty cycle between 73% and
81%
C3 (AC coupled 20 mV/div): Vac_VSYS (TP3 to GND) - excluding high frequency spikes < 15 mV
Figure 4. CHG Mode Ripple and Duty Cycle: VBUS =5V,VBAT = 3.7 V
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Boost Mode: Vbat = 3.7 V
Vsw
Vprnid_AC coupled
C2
C1
www.ti.com Test Summary
2.3.2.6 Switch to Boost Mode
1. Turn off and disconnect PS#1
2. If the constant voltage load connected from BAT+ to GND is not a four-quadrant supply (sources
current) remove the load and use the power source disconnected in step one, set to 3.7 V and 2 A
current limit and connect between BAT+ and GND
3. Apply 10 Ω(5 W or greater) across J5 (PMID(+) to GND(–)
4. Uncheck the OTG Low box in the GUI
5. Select OTG in the Configuration drop-down window
6. Verify VPMID to GND on J5 is between 4.9 V and 5.3 V
7. Verify scope measurement (See Figure 6)
C1 (AC coupled 20 mV/div): Vac_PMID (TP20 to GND) – Ripple excluding high frequency spikes
C2 (5 V/div): Vdc_SW (TP2) - Frequency between 1.2 MHz and 1.7 MHz, Duty cycle between 67%
and 74%
Figure 5. Boost Mode Ripple and Duty Cycle; VBAT = 3.7 V
2.3.2.7 Verify Device ID JEITA shown in software matches Table 4
Table 4. Device ID JEITA Settings
Assembly Number EVM Part Number Device ID JEITA
PWR021-001 bq24190EVM-021 100 Disabled
PWR021-003 bq24192EVM-021 101 Disabled
PWR021-004 bq24192iEVM-021 011 Disabled
PWR021-005 bq24193EVM-021 101 Enabled
PWR021-006 bq24196EVM-021 101 Disabled
PWR021-007 bq24292iEVM-021 011 Disabled
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PCB Layout Guideline www.ti.com
3 PCB Layout Guideline
Minimize the switching node rise and fall times for minimum switching loss. Proper layout of the
components minimizing high-frequency current path loop is important to prevent electrical and magnetic
field radiation and high frequency resonant problems. This PCB layout priority list must be followed in the
order presented for proper layout:
1. Place the input capacitor as close as possible to the PMID and GND pin connections and use the
shortest possible copper trace connection or GND plane.
2. Place the inductor input terminal as close to the SW pin as possible. Minimize the copper area of this
trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the
charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
3. Put an output capacitor near to the inductor and the IC. Tie ground connections to the IC ground with a
short copper trace connection or GND plane.
4. Route analog ground separately from power ground. Connect analog ground and connect power
ground separately. Connect analog ground and power ground together using power pad as the single
ground connection point or use a 0-Ωresistor to tie analog ground to power ground.
5. Use a single ground connection to tie the charger power ground to the charger analog ground just
beneath the IC. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise
coupling.
6. Place decoupling capacitors next to the IC pins and make the trace connection as short as possible.
7. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB
ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground
plane on the other layers.
8. The via size and number should be enough for a given current path.
See the EVM design for the recommended component placement with trace and via locations. For the
QFN information, refer to SCBA017 and SLUA271.
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www.ti.com Board Layout, Schematic, and Bill of Materials
4 Board Layout, Schematic, and Bill of Materials
4.1 Board Layout
Figure 6 through Figure 11 illustrate the board layouts for this EVM.
Figure 6. bq24x9xEVM Top Layer
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Figure 7. bq24x9xEVM Second Layer
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www.ti.com Board Layout, Schematic, and Bill of Materials
Figure 8. bq24x9xEVM Third Layer
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Board Layout, Schematic, and Bill of Materials www.ti.com
Figure 9. bq24x9xEVM Bottom Layer
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Figure 10. bq24x9xEVM Top Assembly
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Figure 11. bq24x9xEVM Bottom Assembly
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VIN
3.4 - 4.4V
BAT+
TS1 TS2
GND
GND
NC
SW
TEST POINTS
INT
OTG
/CE
GND
HI
LO
PSEL
AGND PGND
1
2
3
4
5
Mini_USB
GND GND
System Output
3.9 to 17V
1Not installed
2
PMID
TS2-I
TS1
TS2
2See BOM for component usage
1
11
1
1
2 2 2
2
2
1
11
1
1VBUS
2D+/PSEL
3D-/PG
4STAT
5SCL
6SDA
7INT
8OTG/IUSB
9CE
10ILIM
11 TS1
12TS2
13
BAT
14
BAT
15
SYS
16
SYS
17
PGND
18
PGND
19
SW
20
SW
21
BTST
22
REGN
23
PMID
24
VBUS
25
PWPD
U1
BQ24190xRGE
C5 47nF
C6 4.7uF
C10
1.0uF
R14
2.21k
R7
169
R16
2.21k
R21
30.1k
R22
5.23k
1
2
J6
R18
30.1k
R19
5.23k
1
2
J5
R12 200
R13 200
R10 200
1
2
3
4
J4
JP8 JP9
R20
10.0k
R17
10.0k
1
2
3
J2
TP2
TP10
TP6 TP7 TP8
TP9
TP1
TP3
TP4
TP5
TP12
TP11
D1
LTST-C190GKT
D2
LTST-C190GKT
JP1
JP2
TP13
TP14 TP15 TP16 TP17
JP7
C1
1.0uF
C2
C4
6.8uF
C7
10uF
C8
10uF
C9
0.1uF
C11
10uF
TP18
R8
10.0k
JP5
1
2
3
4
5
6
7
8
9
10
J3
R9
R23
R6
R11
10.0k
JP4
R3
10.0k
R4 200
JP6
R5 10.0k
JP3
R24
768
R15
10.0k
C13
0.1uF
C14
0.1uF
R1
0
R2
0
D3
C15
2.2uF
J7
C3 C12
1
2
3
J1
C16 C17 C18
TP19
JP10
L1
2.2uH
C19
0.1uF
1
1 1
1
1
1
1
1 1 1 1
1
1
1
1
11 1
1
1
1
TS1
TS2
STAT
STAT
D-
PG
PULL-UP
REGN
TS1
REGN
D-
D+/PSEL
D+/PSEL
REGN
STAT
D-/PG
ILIM
SDA SCL
D+/PSEL
PG
INT
OTG /CE TS1 TS2
INT
OTG
/CE
REGN
PULL-UP
PULL-UP
PULL-UP
INT
PULL-UP
/CE
PULL-UP
OTG
SCL
SDA
SCL
D+/PSEL
/CE
OTG
SDA
VBUS
VBUS
D+/PSEL
REGN
D-/PG
PULL-UP
ILIM
TS2
www.ti.com Board Layout, Schematic, and Bill of Materials
4.2 Schematic
Figure 12 illustrates the schematic for this EVM.
Figure 12. bq24x9xEVM Schematic
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4.3 Bill of Materials
Table 5 contains the bill of materials.
Table 5. Bill of Materials
COUNT RefDes Value Description Size Part Number RefDes
-001 -003 -004 -005 -006 -007
1 1 1 1 1 1 C1 1.0uF Capacitor, Ceramic, 25V, X7R, 10% 1206 STD STD
0 0 0 0 0 0 C2 OPEN Capacitor, Ceramic, 0603 STD STD
0 0 0 0 0 0 C3, C12 OPEN Capacitor, Ceramic, 10V, X5R, 10% 1206 STD STD
1 1 1 1 1 1 C4 6.8uF Capacitor, Ceramic, 25V, X5R, 10% 0805 STD STD
1 1 1 1 1 1 C5 47nF Capacitor, Ceramic, 16V, X7R, 10% 0603 STD STD
1 1 1 1 1 1 C6 4.7uF Capacitor, Ceramic, 10V, X5R, 10% 0603 STD STD
2 2 2 2 2 2 C7, C8 10uF Capacitor, Ceramic, 10V X5R, 10% 0805 STD STD
1 1 1 1 1 1 C9 0.1uF Capacitor, Ceramic, 25V, X7R, 10% 0603 STD STD
0 0 0 0 0 0 C13-14, C19 0.1uF Capacitor, Ceramic, 25V, X7R, 10% 0603 STD STD
1 1 1 1 1 1 C10 1.0uF Capacitor, Ceramic, 10V, X7R, 10% 0805 STD STD
1 1 1 1 1 1 C11 10uF Capacitor, Ceramic, 10V, X5R, 10% 0603 STD STD
1 1 1 1 1 1 C15 2.2uF Capacitor, Ceramic, 25V, X5R, 10% 0805 STD STD
0 0 0 0 0 0 C16, C17, C18 47uF Capacitor, Ceramic, 10V, X5R, 20% 1206 STD STD
2 2 2 2 2 2 D1, D2 LTST-C190GKT Diode, LED, Green, 2.1-V, 20-mA, 6-mcd 0603 LTST-C190GKT Lite On
0 0 0 0 0 0 D3 ZLLS350 Diode, Schottky, 1.16A, 40-V SOD-523 ZLLS350TA Zetex
2 2 2 2 2 2 J1,2 ED120/3DS Terminal Block, 3-pin, 15-A, 5.1mm 0.60 x 0.35 inch ED120/3DS OST
1 1 1 1 1 1 J3 N2510-6002RB Connector, Male Straight 2x5 pin, 100mil spacing, 4 Wall 0.338 x 0.788 inch N2510-6002RB 3M
1 1 1 1 1 1 J4 ED555/4DS Terminal Block, 4-pin, 6-A, 3.5mm 0.55 x 0.25 inch ED555/4DS OST
2 2 2 2 2 2 J5-6 PEC02SAAN Header, Male 2-pin, 100mil spacing, 0.100 inch x 2 PEC02SAAN Sullins
1 1 1 1 1 1 J7 56579-0519 Connector, USB-B, Mini, 5-pins 0.354 X 0.307 Inches 56579-0519 Molex
3 3 3 3 3 3 JP1-2, JP10 PEC03SAAN Header, Male 3-pin, 100mil spacing, 0.100 inch x 3 PEC03SAAN Sullins
7 7 7 7 7 7 JP3-9 PEC02SAAN Header, Male 2-pin, 100mil spacing, 0.100 inch x 2 PEC02SAAN Sullins
1 1 1 1 1 1 L1 2.2uH Inductor, SMT, 4.2A, 45.6-milliohm 0.216 x 0.204 inch IHLP2020BZER2R2M01 Vishay
1 1 1 1 1 1 R1 0 Resistor, Chip, 1/16W, 0603 STD STD
1 1 1 1 1 1 R2 0 Resistor, Chip, 0.5W 2010 STD STD
6 6 6 6 6 6 R3 R5 R8 R11 R17 R20 10.0k Resistor, Chip, 1/16W, 1% 0603 STD STD
4 4 4 4 4 4 R4 R10 R12 R13 200 Resistor, Chip, 1/16W, 1% 0603 STD STD
0 0 0 0 0 0 R6 R23 OPEN Resistor, Chip, 1/16W, 0603 STD STD
1 1 1 1 1 1 R7 169 Resistor, Chip, 1/16W, 1% 0603 STD STD
0 1 1 1 1 1 R9 200 Resistor, Chip, 1/16W, 1% 0603 STD STD
2 2 2 2 2 2 R14, R16 2.21k Resistor, Chip, 1/16W, 1% 0603 STD STD
1 1 1 1 1 1 R15 10.0k Potentiometer, 3/8 Cermet, Single-Turn 0.25x0.17 inch 3266W-1-103LF Bourns
0 0 0 1 0 0 R21 6.81k Resistor, Chip, 1/16W, 1% 0603 STD STD
0 0 0 1 0 0 R22 2.26k Resistor, Chip, 1/16W, 1% 0603 STD STD
1 1 1 0 1 1 R21 30.1k Resistor, Chip, 1/16W, 1% 0603 STD STD
1 1 1 0 1 1 R22 5.23k Resistor, Chip, 1/16W, 1% 0603 STD STD
18 bq24190/2/2i/3/6 and bq24292i EVM (PWR021) User’s Guide SLUUA14A–October 2012–Revised April 2013
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www.ti.com Board Layout, Schematic, and Bill of Materials
Table 5. Bill of Materials (continued)
COUNT RefDes Value Description Size Part Number RefDes
-001 -003 -004 -005 -006 -007
1 1 1 1 1 1 R18 30.1k Resistor, Chip, 1/16W, 1% 0603 STD STD
1 1 1 1 1 1 R19 5.23k Resistor, Chip, 1/16W, 1% 0603 STD STD
1 1 1 1 1 1 R24 768 Resistor, Chip, 1/16W, 1% 0603 STD STD
16 16 16 16 16 16 TP1 TP3-11 TP13-17 TP19 5002 Test Point, White, Thru Hole Color Keyed 0.100 x 0.100 inch 5002 Keystone
1 1 1 1 1 1 TP2 131-4244-00 Adaptor, 3.5-mm probe clip ( or 131-5031-00) 0.200 inch 131-4244-00 Tektronix
2 2 2 2 2 2 TP12 TP18 5001 Test Point, Black, Thru Hole Color Keyed 0.100 x 0.100 inch 5001 Keystone
1 0 0 0 0 0 U1 BQ24190RGE IC, I2C Controlled 4A Single Cell USB / Adaptor Charger With Narrow QFN-24 BQ24190RGE TI
VDC Power Path Management and USB OTG
0 0 0 0 0 0 U1 BQ24191RGE IC, I2C Controlled 4A Single Cell USB / Adaptor Charger With Narrow QFN-24 BQ24191RGE TI
VDC Power Path Management
0 1 0 0 0 0 U1 BQ24192RGE IC, I2C Controlled 4A Single Cell USB / Adaptor Charger With Narrow QFN-24 BQ24192RGE TI
VDC Power Path Management and USB OTG
0 0 1 0 0 0 U1 BQ24192IRGE IC, I2C Controlled 4A Single Cell USB / Adaptor Charger With Narrow QFN-24 BQ24192IRGE TI
VDC Power Path Management and USB OTG
0 0 0 1 0 0 U1 BQ24193RGE IC, I2C Controlled 4A Single Cell USB / Adaptor Charger With Narrow QFN-24 BQ24193RGE TI
VDC Power Path Management and USB OTG
0 0 0 0 1 0 U1 BQ24196RGE IC, I2C Controlled 2.5A Single Cell USB / Adaptor Charger With Narrow QFN-24 BQ24196RGE TI
VDC Power Path Management and USB OTG
0 0 0 0 0 1 U1 BQ24292iRGE IC, I2C Controlled 4A Single Cell USB / Adaptor Charger With Narrow QFN-25 BQ24292iRGE TI
VDC Power Path Management and USB OTG
10 10 10 10 10 10 -- Shunt, 100-mil, Black 0.100 929950-00 3M
1 1 1 1 1 1 -- PCB, bq2419xEVM-021, 3"x3" PWR021 Any
1 1 1 1 1 1 -- Label (See note 5) 1.25 x 0.25 inch THT-13-457-10 Brady
4 4 4 4 4 4 - SJ-5303 Rubber foot (see note 6) .044" X 0.20" SJ-5303 3M
Notes: 1. These assemblies are ESD sensitive, observe ESD precautions.
2. These assemblies must be clean and free from flux and all contaminants. Use of no-clean flux is not acceptable.
3. These assemblies must comply with workmanship standards IPC-A-610 Class 2.
4. Ref designators marked with an asterisk ('**') cannot be substituted. All other components can be substituted with equivalent MFG's components.
5. Install label after final wash. Text shall be 8 pt font. Text shall be per Label Information.
6. Install after final wash.
Label Information
Assembly number Text
PWR021-001 bq24190EVM-021
PWR021-003 bq24192EVM-021
PWR021-004 bq24192IEVM-021
PWR021-005 bq24193EVM-021
PWR021-006 bq24196EVM-021
PWR021-007 bq24292iEVM-021
19
SLUUA14A–October 2012–Revised April 2013 bq24190/2/2i/3/6 and bq24292i EVM (PWR021) User’s Guide
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The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims
arising from the handling or use of the goods.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from
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DAMAGES.
Please read the User's Guide and, specifically, the Warnings and Restrictions notice in the User's Guide prior to handling the product. This
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As noted in the EVM User’s Guide and/or EVM itself, this EVM and/or accompanying hardware may or may not be subject to the Federal
Communications Commission (FCC) and Industry Canada (IC) rules.
For EVMs not subject to the above rules, this evaluation board/kit/module is intended for use for ENGINEERING DEVELOPMENT,
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For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant
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This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause
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Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the
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FCC Interference Statement for Class A EVM devices
This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial
environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the
instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to
cause harmful interference in which case the user will be required to correct the interference at his own expense.