Texas Instruments LM5064EVK User manual

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AN-2143 LM5064 Evaluation Kit
User's Guide
SNVA481B–October 2011–Revised January 2020
AN-2143 LM5064 Evaluation Kit
1 Introduction
The LM5064EVK evaluation module provides the power design engineer with a fully functional intelligent
monitoring and protection controller board designed for negative voltage systems. This application note
describes the various functions of the board, how to test and evaluate it, and how to use the GUI design
tool to change the components for a specific application. Use of the advanced telemetry and monitoring
capabilities of this device requires the installation of the Intelligent Power Manager GUI; however, the
LM5064 is capable of acting as a hot-swap and protection circuit without any software installation. Please
check the LM5064 Negative Voltage System Pwr Mgmt & Protection IC with PMBus (SNVS718) for the
latest software and data sheet information.
2 PCB Features
• Operating input voltage range: –36 V to –60 V
• Programmable current limit: set to 16.7 A (CL = VEE or HIGH-Z) or 8.7 A (CL = VDD)
• Q1 power limit: 80W (typical)
• UVLO thresholds: –36 V (falling) and –32 V (rising)
• OVLO thresholds: –60 V (falling) and –56 V (rising)
• Insertion delay: 125 ms
• Fault time-out period: 8 ms
• Restart time: 1.4 s
• Digital isolation circuitry for all PMBusTM signals and PGOOD

UVLO/EN
SCL
PWR
VEE_K
TIMER
PGD
GATE
SDAO
SMBA
ADR0
ADR1
ADR2
VAUX
VDD
OVLO
CL
DIODE
SDAI
VCC
OUT
RETRY
VEE
SENSE
SENSE_ K
VAUXH
VEE_OUT (-)
LM5064
200 kŸ
16.9 kŸ
0.15 µF 1 µF 30.1 kŸ0.003
FDB047N10
GND2 (+)
+
100 µF
60V
5.0SMDJ60A
CMPT3904
191 kŸ
8.25 kŸ
CT CVDD RPWR
VREF
CREF
1 µF
+
CO1 CO2
100 µF
R1
R2
R3
R4
280 kŸ
10.0 kŸ
R5
R6
D1
B3100-13-F
GND1 (+)
VEE (-)
DTEMP Q1
VAUX
RS
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3 Simplified Schematic
Figure 1. Simplified Schematic

UVLO/EN
SCL
PWR
VEE_K
TIMER
PGD
GATE
SDAO
SMBA
ADR0
ADR1
ADR2
VAUX
VDD
OVLO
CL
DIODE
SDAI
VCC
OUT
RETRY
VEE
SENSE
SENSE_ K
VAUXH
VEE_OUT (-)
LM5064
200 kŸ
16.9 kŸ
0.15 µF 1 µF 30.1 kŸ0.003
FDB047N10
GND2 (+)
+
100 µF
10 nF
60V
5.0SMDJ60A
CMPT3904
191 kŸ
8.25 kŸ
J1
SCL_ISO
SDA_ISO
SMBA_ISO
PGD
1
SWITCHES
CONNECTORS
ADR2 ADR1 ADR0 CL RETRY
VDD
HIGH-Z
OVLO
TIMER VDD
CT CVDD RPWR
VREF
CREF
1 µF
RS- RS+
+
CO1 CO2
100 µF
VAUXH
PGD
VEE
OPEN
R1
R2
R2a
R3
R4
280 kŸ
10.0 kŸ
R5
R6
10 kŸ
RP1
ASCL
ASDA
AGND
AVDD
BSCL
BSDA
BGND
BVDD VEE
VDD
1 µF 10 kŸ
RP2
VEE
SDAI/
SDAO
SCL
DGND
DVDD
1 µF
DGND
SDA_ISO
SCL_ISO
C1
C2
Si4800
PS2501-1-A
PS2501-1-A
DGND
DGND
RP4
DVDD
39.0 kŸ
ISOLATION
U3
U4
U1
U1
DGND
DGND
VEE
RP5
DVDD
39.0 kŸ
PGOOD_ISO
SMBA_ISO
RP6
VDD
10.0 kŸ
RP3
VDD
4.99 kŸ
DVDD
J2
SCL_ISO
SDA_ISO
SMBA_ISO
1
DGND
DGND
DVDD
0Ÿ
RS
0Ÿ
RS2
CS
OPEN
D1
B3100-13-F
DRAIN VEE_OUT_S
GND2_S
GND1 (+)
GND1_S
VEE (-)
VEE_S
UVLO/
EN
R8
0Ÿ
R7
0ŸPGD
VEE
PGOOD
SMBA
GATE
CAXH
OPEN
0Ÿ
RAXH
DTEMP
0Ÿ
RIN
CIN
Q1
RS1
VAUX
1
1
1
1000 pF
CD
www.ti.com Getting Started
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Figure 2. Full Evaluation Board Schematic
The schematic for the LM5064 evaluation board is shown in Figure 2. Connections to the PMBus interface
are provided by J2. Banana connectors provide input and output connections. Pins ADR0, ADR1, and
ADR2 are connected to switches that set the PMBus address of the device to one of 27 unique
addresses. Pins RETRY and CL are also connected to switches, allowing for hardware programmability of
the retry and current limit parameters, respectively. Test points are provided to conveniently probe signals
of interest.
4 Getting Started
The LM5064 evaluation kit hardware is shown in Figure 3.

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The LM5064EVK is supplied with the PMBus address set to 0x16 as dictated by the switch configuration
of the ADR0, ADR1, and ADR2 jumper connections.
Figure 3. Connection Illustration
The first step to evaluate the telemetry features of LM5064 is to install the GUI software. The software is
included on a CD in the evaluation kit and is titled PMBManager-x.x.x-xxxxxxxx.exe, where the x
characters indicate the software version and build date. This file should be executed on a PC running
Windows XP or later to install the software. Once the GUI software is installed the hardware should be
configured as shown in Figure 3.
5 Hardware Setup Steps
1. Connect the input supply to the GND1 (+) and VEE (-) banana plugs.
2. Connect the load to the GND2 (+) and VEE_OUT (-) banana plugs.
3. Connect the FTDI dongle to the 10 pin connector (J2) on the left side of the board.
4. Connect the supplied mini USB cable from the FTDI dongle to an USB port on a PC.
When the FTDI dongle is connected for the first time the user will be prompted to install the device drivers.
For the most current driver installation procedure refer to the README.TXT file in the installation
directory.
For a hot swap circuit to function reliably, a low inductance connection to the input supply is
recommended. Its purpose is to minimize voltage transients which occur when the load current changes or
is shut off. If not careful, wiring inductance in the supply lines will generate a voltage transient at the input
which can exceed the absolute maximum rating of the LM5064, resulting in its destruction. To protect
against such voltage transients, TVS device Z1 is provided to clamp the voltage at the input to within safe
operating limits. Likewise, Schottky diode D1 is provided on the output to clamp the output from going
excessively positive during short circuit events.
6 Device Evaluation
After configuring the hardware connections, apply an input voltage of -48V to the device. The current
hardware configuration allows the LM5064 device to work from -36V to -60V input supply voltage;
however, this guide will assume an input voltage of -48V. Launch the GUI by going to the Windows Start
menu -> All Programs -> PMBManager-x.xxxxx -> PMBusManager. A pulldown menu should come up
with a list of devices populated. Select the "LM5064" option as shown in Figure 4.
Figure 4. Device Selector

Device Information
Device Configuration
Telemetry Plotter
Device Telemetry
Display Options Design Tool
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The device should be detected on the PMBusand the initial load screen should appear as shown in
Figure 5.
Figure 5. Initial GUI Screen
If a device is not detected, an option is provided to rescan, ignore, or exit the GUI. If the hardware is
intended to be connected, check the USB connection to the PCB, FTDI connection to the evaluation
module, and verify that the power is present on the evaluation PCB by measuring the voltage between the
GND1_s (+) and VEE_s (-) testpoints. Ignoring the detection message allows use of the integrated design
tool without the hardware connected.
Figure 6. LM5064 Block Level Representation
Double click on the detected device ID (NSC-LM5064-AA) to display a block level representation of the
device as shown in Figure 6. The block level view of the device provides a display of all the telemetry data
as well as most of the faults and warnings supported by the device. The faults and warnings supported
are generally associated with an invalid input or output condition.

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The faults shown on the left side of the block representation are generally associated with the input. These
include input under-voltage (UV), input over-voltage (OV), FET Fail (FF), and input over-power (OP). The
SMBus alert status, SMBA, is also shown on the left side and will turn red during any warning or fault
event. To facilitate the evaluation of the device, SMBus alerts are automatically cleared by the GUI.
The faults shown on the right side of the block representation are associated with the output. These
include output over-voltage (OV), power good status (PGD), output over-current (OC), and over-
temperature (OT). There is also an indicator if the output is in the latched off state (LO). The device will
latch the output off after the number of user programmable retries is exceeded. To clear the latched off
condition, the output can be toggled off and on by the red power button icon located in the top right of the
LM5064 block representation.
To show a repetitive update of the device telemetry and status click on the play icon at the top of the
screen. The play button starts an active telemetry log of the gathered data. Clicking the stop icon stops
the telemetry collection and allows for the log file to be viewed and saved. The pause button pauses both
the displaying and logging of telemetry information.
To disable displaying undesired telemetry click the display icon on the block representation. This will open
the window shown in Figure 7 that will allow the user to disable the undesired telemetry, fault, and warning
information from appearing on the block level device representation.

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Figure 7. LM5064 Telemetry Display Options
Note that turning off the various warning options does not mask the faults from issuing an SMBus alert - it
just does not display them if they occur. The device is capable of masking various faults and this
functionality can be setup in the device configuration panel.
7 GUI Event Log
A GUI event log is provided to keep track of GUI configuration changes and device fault events. To
display the event log select View from the main menu bar and then View Event Log. The event log will
appear on the left side of the main GUI window. The event log can be detached and expanded if desired
by left clicking on the event log window and dragging window with the mouse to the desired location.

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8 Plotting Telemetry Data
To enable telemetry data plots click on the sine wave icon located on the LM5064 block representation.
After enabling the telemetry, a prompt will appear requesting entry of the GUI sample rate, plot rate, and
plot depth. For most cases the default rates and depths will be acceptable. The plotting tool allows the
user to select the desired data to be plotted. Up to two different parameters may be plotted at the same
time as shown in Figure 8 .
Figure 8. LM5064 GUI with Telemetry Plotting Tool Enabled
Device telemetry data is plotted as a black line that continually updates as the device is queried. In
addition to the device data, the relevant warning and fault thresholds are also plotted. Warning thresholds
are shown as orange lines while fault thresholds are shown in red and blue.
By going to the plot menu option the user can disable the plotting grid as well as the warning and fault
lines.
9 Configuring the LM5064 Device
Warning Thresholds, Temperature Fault Threshold, Protection Ranges, Fault Masking, and Averaging can
be configured in the Device Configuration panel. This panel, shown in Figure 9, is enabled by clicking the
gear icon shown on the LM5064 block representation.

www.ti.com Configuring the LM5064 Device
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Figure 9. Device Configuration Panel

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The Warning and Fault Threshold tab allows configuration of the input under-voltage, input over-voltage,
output under-voltage, input over-current, input power, and over temperature warnings. This tab also allows
adjustment of the over-temperature fault threshold. Fault threshold for the input over- and under-voltage,
current limit, power limit, and power good are set by the hardware design. Decimal values for the
thresholds are shown in the text box located to the right of the slider bar. Above the decimal values setting
is the value of the setting in hexadecimal, which can be useful when developing software for this device.
The fault behavior tab allows the user to set the device fault configuration and fault masking. The fault
configuration section allows the user to set the number of retries, as well as the circuit breaker and current
limit thresholds. The number of retries can be set by the RETRY pin to be infinite or latched off. Through
software, the number of retries can be set to 0 (latch-off), 1, 2, 4, 8, 16 or infinite. The software settings
are independent of the hardware settings; however, if the power is cycled the device will default to values
dictated by the hardware. Current limit power-up values are also set by the hardware. The values for
current limit can be set to either 26 mV (CL = VDD) or 50 mV (CL = VEE). The circuit breaker threshold
can also be set in software to either 1.9 times or 3.9 times the current limit value. Fault masking is
possible for many of the device fault conditions. Fault conditions allow masking of both the MOSFET
response and the SMBus alert signal. Note that if a fault occurs repeatedly while the MOSFET is masked,
damage to the MOSFET may result. This feature is allowed primarily for debug purposes. Faults that do
not shut off the MOSFET, and only issue a SMBus alert, will also allow masking of the alert. Note the
power-up default setting for the power good signal is to mask the SMBus alert, in order to ensure that
SMBus alert is not asserted immediately after power-up.
For convenience, the Device Configuration Panel can be undocked by holding down the left mouse button
while the cursor is at the top of the panel and dragging it to where you would like it to be placed.
10 Customizing the Design
The GUI assumes the hardware configuration is set to default evaluation board configuration. If any of the
components are changed, the device hardware configuration needs to be updated in the design tool
section. To open the design tool click the wrench icon located on the LM5064 block representation which
will open the window displayed in Figure 10.
Figure 10. LM5064 Design Tool

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Design inputs are keyed in on the left side following steps 1 though 5. General operating conditions should
be entered in step 1 of the design tool. These inputs help set bounds on the startup time and application
voltage ranges.
Step 2 allows the user to tailor the MOSFET protection features to be specific to the target application.
Current limit is pin-configurable and software configurable, and circuit breaker is software-configurable. If
CL switch is used to set the current limit, make sure the GUI selection matches the pin-configurable CL bit
setting on the board. By clicking on the MOSFET SOA Profile button the user can select SOA data from
several popular MOSFETs or enter the SOA data for the desired MOSFET. The resistor RPWR can then be
calculated to keep Q1within its SOA profile.
Step 3 allows the user to select the under- and over-voltage lockout values (UVLO/OVLO). Note that with
the correct values for R1 - R4, the device will indicate a fault condition when the input and/or output
voltages are outside of their programmed range.
Step 4 allows the user to set the fault time-out period and the fault response. The fault time-out should be
set to be below the MOSFET SOA data for a given time. For example, if a design is done to adhere to the
10 ms pulsed MOSFET SOA data, the desired fault time-out must be less than 10 ms. The fault time-out
time entered will set the value for CT. It also sets the insertion delay and fault retry delay. The initial power
up retry behavior is also selected in this design step. Make sure to change the RETRY switch to match the
design tool schematic when changing the default retry setting.
In step 5 the user enters the desired PMBus address. Note changing the PMBus address of the device in
step 5 does not change the device address, but shows how the address pins of the device need to be
configured to achieve a desired address. Once the ADR pin switches are configured for a particular
address, power to the device needs to be cycled and the GUI restarted in order for the new address to
take affect.
When invalid or incorrect inputs are given to the design tool, text associated with the faulty input will turn
red. Positioning the mouse cursor over the red text will give additional information about any design
conflict.
Component and parametric results are shown to the right as well as the LM5064 protection SOA chart.
The protection SOA chart shows the minimum, typical, and maximum SOA protection areas for a given
design. For a robust design, the SOA of the MOSFET used should be above the MAX protection SOA line
for all operating areas.
Once a design is complete, the design should be saved by selecting the File menu, and then Save. Once
the hardware is modified to match the design the GUI should be restarted and the hardware configuration
file loaded right after the device is detected and placed. If the values in the design tool are different than
the values on the board, erroneous telemetry and fault data will be reported by the GUI. To return to the
block view of the device, press the home icon located at the far left in the menu bar.
The design tool is also useful to calculate the PMBus coefficients. With the correct value for current sense
resistor (RS) the tool will calculate the correct coefficients to scale the raw telemetry data. The coefficients
can be viewed by selecting View from the main menu bar, and then selecting the PMBus Coefficient
Editor. When the PMBus Coefficient Editor is opened, press the Get All button to show the currently used
coefficients.
If desired the results presented by the design tool can be calculated by hand using the equations provided
in the datasheet. However, note the design tool calculates parameters factoring in worst case tolerances,
while the equations in the data sheet are based on typical thresholds.
11 GUI Register Page
The GUI Register Page, as shown in Figure 11, provides the user with several features to help better
understand the functionality of the LM5064. These features include the ability to read telemetry, device
identification and status registers, as well as being able to monitor the SMBus Alert and PGOOD
interrupts, and to turn the output on and off with the OPERATION button.

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Figure 11. LM5064 Register Page
Telemetry is updated by clicking the Update Telemetry button. This action will update the fields under the
Averaged heading and under the Immediate heading along with VAUX and PEAK PIN. Select which
parameters to update by clicking in the box next to each parameter. If all parameter boxes under a given
heading are checked, the "Update Telemetry" button will use the block read PMBus commands
(AVG_BLOCK_READ and BLOCK_READ) to update the fields, ensuring that the readings are time
aligned. If one or more of the boxes under the headings is not checked, the "Update Telemetry" button will
use the respective individual read PMBus commands to make the telemetry readings and the
measurements will not be time aligned. VAUX and PEAK PIN are always read with discrete PMBus
commands and, therefore, are never time aligned. The "CLEAR_PIN_PEAK" button is provided to clear
the PEAK PIN reading which is often much higher than one would expect under steady state conditions.
This is related to the large inrush current during power-on that gets sampled by the internal power
measurement circuitry and used to calculate PEAK PIN.
The output can be turned off and on using the "OPERATION" button, and the Identification Information
can be obtained by clicking the "Update ID Information" button. The rest of this page is used to monitor
and diagnose warning and fault conditions. The SMBA and PGOOD interrupts will indicate if a warning or
fault has occurred and if the output voltage is within specifications. They are always active and there is no
need to click an "Update Telemetry" button to change their state. Clicking the "Update Status" button
under the Register Operation Control heading will update the bits in all of the registers, as well as the
telemetry, under the Status section. Clicking the "CLEAR_FAULTS" button will reset all warning and fault
bits and issue an Update Status. If the warning and/or fault condition has been remedied, the bits will
reset. If the warning and/or fault condition still exists, the registers will be updated within a millisecond and
thus will appear to never have been cleared. The STATUS_WORD, STATUS_INPUT, STATUS_CML and
DIAGNOSTIC_WORD registers operate in a cumulative way. That is, these registers display any and all
warnings and errors that have occurred since the last CLEAR_FAULTS command was issued. The
telemetry and DIAGNOSTIC_WORD that are part of the BLACK_BOX_READ are also updated by clicking
the Update Status button. These telemetry parameters and bits are latched at the moment the SMBA

t1
VSYS 0t2 t3
a) Power Limit
Source Voltage-toGate -
VDS
tON
VSYS
PLIM
VGATE
VGSL
VTH
PMOSFET
0
IDS
0
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signal was asserted. They are not reset or cleared by the CLEAR_FAULTS command but rather, they are
re-armed, or readied, to be over-written with new values at the onset of the next SMBA signal assertion.
Note that these telemetry fields and this register are not cumulative. That is, they can only be updated
once after the CLEAR_FAULTS command is issued, and it will be at the first occurrence of the SMBA
assertion following the CLEAR_FAULTS. This allows the user to determine device conditions at the first
occurrence of the SMBA assertion.
12 Theory of Operation
The LM5064 provides intelligent control of the power to a load from a live power source. The three primary
functions of the device are to limit inrush current during turn-on, monitor the load current for faults during
normal operation, and to provide system telemetry for the following parameters: Input Voltage (VCC to
VEE), Input Current (IIN), Input Power (PIN), Output Voltage (VOUT), Auxilliary Voltage (VAUX), and
Temperature. Additional functions include under- and over-voltage lock-outs (UVLO/OVLO) to ensure
voltage is supplied to the load only when the system input voltage is within a specified range, power
limiting of the series pass MOSFET (Q1) during turn-on, and a Power Good logic output (PGD) to indicate
the output voltage status.
Upon applying the input voltage to the LM5064, Q1 is initially held off for the insertion delay (125 ms) to
allow ringing and transients on the input to subside. At the end of the insertion delay, if the input voltage
(VCC-VEE) is above the UVLO threshold, Q1 is turned on in a controlled manner to limit the inrush
current.
The LM5064 utilizes two methods to limit inrush currents at startup. For the input voltage range and sense
resistor on this board, the inrush current will be limited by the MOSFET power limit method. The power
limit method controls the input current such that a constant power is dissipated by Q1 during startup. At
the onset of the startup period, Vsys (VEE)= -48V and VOUT = 0V. Q1’s power dissipation is limited to a
peak value set by RPWR (80W) by monitoring its drain current (the voltage across RS) and its drain-to-
source voltage. Their product is maintained constant by controlling the drain current as the drain-to-source
voltage decreases (as the output voltage increases). This is shown in the constant power portion of where
the drain current is increasing to ILIM.
Figure 12. Power Up Using Power Limit

Load
Current
GATE
Pin
TIMER
Pin
3.9V
1.2V
1 2 3 7 8
4.1 mA
pulldown
52 PA
Gate Charge
74 PA
2.4 PA
Fault Timeout
Period
0.3V
Fault
Detection ILIMIT
tRESTART
Fault Detection & Restart www.ti.com
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If the power across Q1 does not exceed the programmed power limit, the LM5064 will also limit the drain
current to the current limit value determined by the sense resistance and the selected current limit voltage
threshold, 26 mV or 50 mV. The current limit will be maintained constant as the output voltage continues
to increase. During the current limit period, the voltage at the TIMER pin will be rising. If the TIMER
voltage reaches 3.9V before the current limit time has expired, the device will shut down and retry
according to the programmed retry configuration. If the TIMER does not expire, the output voltage will rise
and the drain current needed to charge the output capacitance will reduce. The output voltage will
continue to rise towards the the input voltage (VDS decreases to near zero), and the drain current then
reduces to a value determined by the load. Q1’s gate-to-source voltage then increases to its final value.
The circuit is now in normal operation mode.
Monitoring of the load current for faults during normal operation is accomplished using the current limit
circuit described above. If the load current increases to 8.7 Amps (26 mV across RS), Q1’s gate is
controlled to prevent the current from increasing further. When current limiting takes effect, the fault timer
limits the duration of the fault. At the end of the fault time-out period Q1 is shut off, denying current to the
load. The LM5064 then initiates a restart every 1.4 seconds. The restart consists of turning on Q1 and
monitoring the load current to determine if the fault is still present. After the fault is removed, the circuit
powers up to normal operation at the next restart. If the retry setting is changed to a limited number of
retrys, the LM5064 will stop retrying after the programmed number of retrys occur, and keep Q1 shut off
until UVLO/EN is toggled or the output is turned off and then on via PMBus.
In a sudden overload condition (e.g. when the output is shorted to VEE), it is possible that the current
could increase faster than the response time of the current limit circuit. In this case, the circuit breaker
sensor shuts off Q1’s gate rapidly when the voltage across RS reaches 49 mV. When the current reduces
to the current limit threshold, the current limit circuitry then takes over.
The PGD logic level output is low during turn-on and switches high when the VDS of the MOSFET is
below 1.25V. PGD switches low when the VDS of the MOSFET is above 2.5V. The high level voltage at
PGD can be any appropriate voltage up to +80V above VEE and can be higher or lower than the voltages
at VCC and OUT.
The UVLO thresholds are set by resistors R1 and R2, the OVLO thresholds are set by R3 and R4.
Optional resistor R2a can be added to set the UVLO and OVLO thresholds with only three resistors as
outlined in the LM5064 datasheet. Internal current sources at UVLO/EN and OVLO are used to set the
hysteresis levels.
13 Fault Detection & Restart
If the load current increases to the fault level (the typical current limit threshold of 8.7A), an internal current
source charges the timing capacitor at the TIMER pin. When the voltage at the TIMER pin reaches 3.9V,
the fault time-out period is complete and the LM5064 shuts off Q1. The restart sequence then begins,
consisting of seven cycles at the TIMER pin between 3.9V and 1.2V, as shown in Figure 13. When the
voltage at the TIMER pin reaches 0.3V during the eighth high-to-low ramp, Q1 is turned on. If the fault is
still present, the fault time-out period and the restart sequence repeat.
Figure 13. Fault Time-out and Restart Sequence

VCC
UVLO/
EN
OVLO
VEE
R1
R2
R3
2.48V
20 PA
2.47V
21 PA
TIMER AND GATE
LOGIC CONTROL
LM5064
R4/3a
R2a
GND
VSYS
www.ti.com UVLO and OVLO Input Voltage Threshold
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The waveform at the TIMER pin can be monitored at the TIMER test point. On this evaluation board, the
initial fault time-out period is 8 ms and the restart time is 1.4 seconds.
14 UVLO and OVLO Input Voltage Threshold
Programming the UVLO threshold sets the minimum system voltage to enable Q1. If VCC-VEE is below
the UVLO thresholds, Q1 is switched off, denying power to the load. Programmable hysteresis is
adjustable by changing the value of R1.
The UVLO threshold is set with two resistors (R1, R2) as shown in Figure 14 and an internal 20 µA
current source allows a hysteresis voltage to be set.
The OVLO threshold sets the maximum voltage that can be present on the input before the device turns
off the series pass device. The OVLO threshold is set with the two resistors (R3, R4). The hysterisis
voltage is set by the internal 21 uA current source and the value of R3.
Figure 14. Programming the UVLO and OVLO Thresholds
15 Shutdown
With the circuit in normal operation, the LM5064 can be shutdown by pulling the UVLO/EN pin to VEE or
by clicking the ON/OFF button on the LM5064 block representation in the GUI.
16 Board Layout and Probing Cautions
Refer to the product datasheet for detailed layout guidelines. For most applications the layout of this
evaluation module as detailed in the PC Board Layout section of this document should be sufficient to
provide a working solution with accurate telemetry. The following should be kept in mind when the board is
powered:
1. Use CAUTION when probing the circuit to prevent injury as well as possible damage to the circuit.
2. At maximum load current ( typically 16.7A), the wire size and length used to connect the power source
and the load become very important. The wires connecting this evaluation board to the power source
should be a heavy gauge and twisted together to minimize input inductance. The same applies for the
wires connecting this board to the load. This recommendation is made in order to minimize high
voltage transients from occurring when the load current is shut off.
3. A 60V TVS diode located close to the LM5064EVK GND1 and VEE pins provides the critical function
of clamping inevitable input voltage overshoot when Q1turns off at high currents. If operation above
60V is required, the TVS will need to be replaced with a TVS rated at a higher standoff voltage. Always
verify the TVS by performing a worst-case current limit at the maximum input voltage and monitoring
the resulting input voltage surge. The TVS should be able to clamp the input below 100V in all cases.
4. The VEE points for the UVLO/EN and OVLO resistor networks are tied directly to a via where the

VTIMER (2V/Div)
VOUT (20V/Div)
VSYS (20V/Div) (-48V)
VGATE (20V/Div)
VGATE (20V/Div)
VOUT (25V/Div)
VSYS (25V/Div)
VTIMER (2V/Div)
VOUT (20V/Div)
VGATE (5V/Div)
IIN (5A/Div)
VTIMER (2V/Div)
VOUT (20V/Div)
VGATE (5V/Div)
IIN (5A/Div)
CL = 8.7A CB = 1.8 x CL
VTIMER (2V/Div)
VOUT (20V/Div)
VSYS (5V/Div)
IIN (5A/Div)
VTIMER (2V/Div)
VOUT (20V/Div)
VSYS (20V/Div)
IIN (5A/Div)
Performance Characteristics www.ti.com
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LM5064 is conneced to the VEE plane.
5. All testpoint signals are referenced to the VEE voltage.
17 Performance Characteristics
Figure 15. Insertion Time Delay (40 ms/div) Figure 16. Turn-On Sequence into a 40ΩLoad (40 ms/div)
Figure 17. Circuit Breaker Event (CL = VDD) 4 ms/div Figure 18. Current Limit Event (CL = VDD) 4 ms/div
Figure 19. Startup (UVLO/EN, OVLO) (400 ms/div) Figure 20. Short Circuit VOUT 1 s/div

-50 -25 0 25 50 75 100 125
-1.6
-1.2
-0.8
-0.4
0.0
0.4
0.8
1.2
1.6
IIN ERROR (%)
TEMPERATURE (°C)
CL=VEE
-50 -25 0 25 50 75 100 125
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
PIN ERROR (%)
TEMPERATURE (°C)
CL=VEE
www.ti.com Performance Characteristics
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Figure 21. IIN Error vs Temperature Figure 22. PIN Error vs Temperature

Bill of Materials www.ti.com
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18 Bill of Materials
Designator Value Description Manufacturer Part Number Qty.
U1 NEGATIVE HOT SWAP CONTROLLER Texas
Instruments LM5064 1
U2 BiDirectional I2C Isolator Silicon Labs Si8400 1
U3, U4 HIGH ISOLATION VOLTAGE SINGLE
TRANSISTOR TYPE NEC PS2501L-1-A 2
C1, C2,
CREF, CVDD 1 µF CAP, CERM, 1uF, 10V, +/-10%, X7R, 0603 MuRata GRM188R71A105KA61D 4
CAXH N/A OPEN N/A N/A N/A
CD, CS 1000
pF CAP, CERM, 1000pF, 50V, +/-10%, X7R, 0603 MuRata GRM188R71H102KA01D 2
CIN 10 nF CAP, CERM, 0.01uF, 100V, +/-10%, X7R,
0805 MuRata GRM21BR72A103KA01L 1
CO1, CO2 100 µF CAP, AL, 100uF, 100V, +/-20%, SMD Nippon Chemi-
Con EMVE101ARA101MKE0S 1
CT .15 µF CAP, CERM, 0.15uF, 25V, +/-10%, X7R,
0603 MuRata GRM188R71E154KA01D 1
D1 Diode, Schottky, 100V, 3A, SMC Diodes Inc. B3100-13-F 1
DTEMP Transistor, NPN, 40V, 0.2A, SOT-23 NXP
Semiconductor PMS3904 1
Q1 MOSFET, N-CH, 100V, 120A, DDPAK Fairchild FDB047N10 1
R1 200 kΩRES, 200 kΩ, 1%, 0.1W, 0603 Vishay-Dale CRCW0603200KFKEA 1
R3 191 kΩRES, 191 kΩ, 1%, 0.1W, 0603 Vishay-Dale CRCW0603191KFKEA 1
R2 16.9
kΩRES, 16.9 kΩ, 1%, 0.1W, 0603 Vishay-Dale CRCW060316K9FKEA 1
R2a N/A OPEN N/A N/A N/A
R4/3a 8.25
kΩRES, 8.25 kΩ, 1%, 0.1W, 0603 Vishay-Dale CRCW06038K25FKEA 1
R5 280 kΩRES, 280 kΩ, 1%, 0.1W, 0603 Vishay-Dale CRCW0603280KFKEA 1
R6, RP1, RP2 10 kΩRES, 10.0 kΩ, 1%, 0.1W, 0603 Vishay-Dale CRCW060310K0FKEA 3
R7, R8,
RAXH, RS1,
RS2
0ΩRES, 0Ω, 5%, 0.1W, 0603 Vishay-Dale CRCW06030000Z0EA 1
RIN 0ΩRES, 0Ω, 5%, 0.25W, 1206 Vishay-Dale CRCW12060000Z0EA 1
RP3 4.99
kΩRES, 4.99 kΩ, 1%, 0.1W, 0603 Vishay-Dale CRCW06034K99FKEA 1
RP4, RP5 39 kΩRES, 39 kΩ, 5%, 0.1W, 0603 Vishay-Dale CRCW060339K0JNEA 1
RP6 10 kΩRES, 10 kΩ, 5%, 0.1W, 0603 Vishay-Dale CRCW060310K0JNEA 1
RPWR 30.1
kΩRES, 30.1 kΩ, 1%, 0.1W, 0603 Vishay-Dale CRCW060330K1FKEA 1
RS 3 mΩRES, 0.003Ω, 1%, 1W, 2512 SMD Vishay-Dale WSL25123L000FEA 1
RPWR 30.1
kΩRES, 30.1 kΩ, 1%, 0.1W, 0603 Vishay-Dale CRCW060330K1FKEA 1
Z1 Transient Voltage Supression Diode,
5000W, 60V Littlefuse 5.0SMDJ60A 1

www.ti.com Bill of Materials
19
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AN-2143 LM5064 Evaluation Kit
Designator Value Description Manufacturer Part Number Qty.
AD0, AD1,
AD2, CL,
DRAIN,
GATE,
GND1_S,
GND2_S,
OVLO,
PGOOD,
RS+, RS-,
RTRY,
TIMER,
UVLO, VAUX,
VAUXH, VDD,
VEE_OUT_S,
VEE_S
Test Point, TH, Miniature Keystone
Electronics 5015 20
ADR0, ADR1,
ADR2,
CLIMIT,
RETRY
SWITCH SLIDE SPDT SMD J-LEAD 50 V,
100 mA Copal CJS-1201TA 5
GND1, GND2,
VEE,
VEE_OUT
Standard Banana Jack, Uninsulated Keystone
Electronics 575-8 1
H1, H2, H5,
H6 Standoff, Hex, 0.5"L #4-40 Nylon Keystone Electronics 1902C 4
H3, H4, H7,
H8 'Machine Screw, Round, #4-40 x 1/4, Nylon, Philips panhead B Fastener Supply NY PMS 440 0025 PH 1
J1 Female Header, 5-Pin, Dual row, Right
Angle Sullins PPPC052LJBN-RC 1
J2 Male Header, 5-Pin, Dual row, Right Angle Samtec Inc TSW-105-08-L-D-RA 1

PC Board Layout www.ti.com
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19 PC Board Layout
Figure 23. Board Top Layer
Figure 24. Board Mid Layer 1
Figure 25. Board Mid Layer 2