Texas Instruments TPS543B22EVM User manual

User's Guide
TPS543B22EVM SWIFT Step-Down Converter Evaluation
Module
ABSTRACT
This user’s guide contains information for the TPS543B22 evaluation module (BSR178) and the 20 A
DC/DC converter. Also included are the performance characteristics, schematic, and bill of materials for the
TPS543B22EVM.
Table of Contents
1 Introduction.............................................................................................................................................................................3
1.1 Background........................................................................................................................................................................ 3
1.2 Before You Begin............................................................................................................................................................... 3
1.3 Performance Characteristics Summary............................................................................................................................. 4
2 Configurations and Modifications.........................................................................................................................................5
2.1 Output Voltage................................................................................................................................................................... 5
2.2 Switching Frequency (FSEL Pin)....................................................................................................................................... 6
2.3 Current Limit, Soft-Start Time, and Internal Compensation (MODE Pin)........................................................................... 6
2.4 Adjustable UVLO................................................................................................................................................................6
3 Test Setup and Results.......................................................................................................................................................... 7
3.1 Input/Output Connections.................................................................................................................................................. 7
3.2 Efficiency..........................................................................................................................................................................10
3.3 Output Voltage Regulation................................................................................................................................................11
3.4 Load Transient and Loop Response................................................................................................................................ 12
3.5 Output Voltage Ripple...................................................................................................................................................... 13
3.6 Input Voltage Ripple......................................................................................................................................................... 14
3.7 Synchronizing to a Clock..................................................................................................................................................15
3.8 Start-up and Shutdown with EN....................................................................................................................................... 16
3.9 Start-up and Shutdown with VIN...................................................................................................................................... 17
3.10 Start-up Into Pre-Bias.....................................................................................................................................................18
3.11 Hiccup Current Limit....................................................................................................................................................... 19
3.12 Thermal Performance.................................................................................................................................................... 20
4 Board Layout.........................................................................................................................................................................21
4.1 Layout.............................................................................................................................................................................. 21
5 Schematic and Bill of Materials...........................................................................................................................................25
5.1 Schematic........................................................................................................................................................................ 25
5.2 Bill of Materials.................................................................................................................................................................27
6 Revision History................................................................................................................................................................... 28
List of Figures
Figure 3-1. P1 Efficiency............................................................................................................................................................10
Figure 3-2. P2 Efficiency – Default Configuration......................................................................................................................10
Figure 3-3. U1 Load Regulation ................................................................................................................................................11
Figure 3-4. U1 Line Regulation ................................................................................................................................................. 11
Figure 3-5. U2 Load Regulation ................................................................................................................................................11
Figure 3-6. U2 Line Regulation ................................................................................................................................................. 11
Figure 3-7. U1 Transient Response...........................................................................................................................................12
Figure 3-8. U2 Transient Response...........................................................................................................................................12
Figure 3-9. U1 Bode Plot........................................................................................................................................................... 12
Figure 3-10. U2 Bode Plot......................................................................................................................................................... 12
Figure 3-11. U1 Output Ripple – No Load..................................................................................................................................13
Figure 3-12. U1 Output Ripple – 20 A Load.............................................................................................................................. 13
www.ti.com Table of Contents
SLUUCH6B – SEPTEMBER 2022 – REVISED SEPTEMBER 2023
Submit Document Feedback
TPS543B22EVM SWIFT Step-Down Converter Evaluation Module 1
Copyright © 2023 Texas Instruments Incorporated

Figure 3-13. U2 Output Ripple – No Load................................................................................................................................. 13
Figure 3-14. U2 Output Ripple – 20 A Load.............................................................................................................................. 13
Figure 3-15. U1 Input Ripple – No Load.................................................................................................................................... 14
Figure 3-16. U1 Input Ripple – 20 A Load................................................................................................................................. 14
Figure 3-17. U2 Input Ripple – No Load.................................................................................................................................... 14
Figure 3-18. U2 Input Ripple – 20 A Load................................................................................................................................. 14
Figure 3-19. U1 and U2 Synchronized to a Clock..................................................................................................................... 15
Figure 3-20. U2 Clock Synchronization Transitions...................................................................................................................15
Figure 3-21. U2 Start-up with EN – No Load............................................................................................................................. 16
Figure 3-22. U2 Shutdown with EN – No Load..........................................................................................................................16
Figure 3-23. U2 Startup with EN – No Load and Measuring VDRV...........................................................................................16
Figure 3-24. U2 Start-up with VIN .............................................................................................................................................17
Figure 3-25. U2 Shutdown with VIN ......................................................................................................................................... 17
Figure 3-26. U2 Start-up Into 0.5-V Pre-Bias.............................................................................................................................18
Figure 3-27. U1 Output Overcurrent Protection – Overload...................................................................................................... 19
Figure 3-28. U2 Output Overcurrent Protection – Overload...................................................................................................... 19
Figure 3-29. U1 Thermal Performance – 20-A Load and U2 Off .............................................................................................. 20
Figure 3-30. U2 Thermal Performance – 20-A Load and U1 Off............................................................................................... 20
Figure 3-31. U1 Thermal Performance – Both 20-A Load ........................................................................................................ 20
Figure 3-32. U2 Thermal Performance – Both 20-A Load ........................................................................................................ 20
Figure 4-1. Top Overlay............................................................................................................................................................. 22
Figure 4-2. Top Solder............................................................................................................................................................... 22
Figure 4-3. Top Layer.................................................................................................................................................................22
Figure 4-4. Signal 1................................................................................................................................................................... 22
Figure 4-5. Signal 2................................................................................................................................................................... 23
Figure 4-6. Signal 3................................................................................................................................................................... 23
Figure 4-7. Signal 4................................................................................................................................................................... 23
Figure 4-8. Bottom Solder..........................................................................................................................................................23
Figure 4-9. Bottom Overlay........................................................................................................................................................24
Figure 4-10. Bottom Layer......................................................................................................................................................... 24
Figure 4-11. Drill Drawing.......................................................................................................................................................... 24
Figure 4-12. Board Dimensions................................................................................................................................................. 24
Figure 5-1. U1 schematic...........................................................................................................................................................25
Figure 5-2. U2 schematic...........................................................................................................................................................26
List of Tables
Table 1-1. Input Voltage and Output Current Summary...............................................................................................................3
Table 1-2. TPS543B22EVM Small Size (U1) Performance Characteristics Summary................................................................ 4
Table 1-3. TPS543B22EVM High Efficiency (U2) Performance Characteristics Summary......................................................... 4
Table 2-1. VOUT Selection.......................................................................................................................................................... 5
Table 2-2. FSEL Selection........................................................................................................................................................... 6
Table 2-3. MODE Selection......................................................................................................................................................... 6
Table 3-1. Connectors and Jumpers............................................................................................................................................8
Table 3-2. Test Points.................................................................................................................................................................. 9
Table 3-3. Efficiency Measurement Test Points......................................................................................................................... 10
Table 5-1. TPS543B22EVM Bill of Materials............................................................................................................................. 27
Trademarks
All trademarks are the property of their respective owners.
Trademarks www.ti.com
2TPS543B22EVM SWIFT Step-Down Converter Evaluation Module SLUUCH6B – SEPTEMBER 2022 – REVISED SEPTEMBER 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

1 Introduction
1.1 Background
The TPS543B22 DC/DC converter is a synchronous buck converter designed to provide up to a 20-A output.
The input (VIN) is rated for 4 V to 18 V. Table 1-1 provides the rated input voltage and output current range for
the evaluation module.
The high-side and low-side MOSFETs are incorporated inside the TPS543B22 package along with the gate-
drive circuitry. The low drain-to-source on-resistance of the MOSFET allows the TPS543B22 to achieve high
efficiencies and helps keep the junction temperature low at the rated output current. Fixed frequency advanced
current mode control allows you to synchronize the regulators to an external clock source. An external divider
allows for an adjustable output voltage. The TPS543B22 FSEL and MODE pins provide selectable switching
frequency, soft-start time, current limit, and internal compensation. Lastly, the TPS543B22 includes an enable
pin and a power-good output, which can be used for sequencing multiple regulators.
This evaluation module includes two designs with the TPS543B22. The first design is designed to demonstrate
the small printed-circuit-board areas that can be achieved when designing with the TPS543B22 regulator. The
small area design fits within 275 mm2. The second design is designed to demonstrate the high efficiency that
can be achieved when designing with the TPS543B22 regulator. The second design also includes jumpers that
can be used to easily evaluate the features of the TPS543B22.
Table 1-1. Input Voltage and Output Current Summary
EVM INPUT VOLTAGE RANGE OUTPUT CURRENT RANGE
TPS543B22EVM VIN = 4 V to 18 V 0 A to 20 A
1.2 Before You Begin
The following warnings and cautions are noted for the safety of anyone using or working close to the
TPS543B22EVM. Observe all safety precautions.
CAUTION
The TPS543B22EVM can become hot during operation due to dissipation of power in some operating conditions.
Avoid contact with the board. Follow all applicable safety procedures applicable to your laboratory.
Caution: Hot surface.
Contact can cause burns.
Do not touch!
WARNING
The circuit module has signal traces, components, and component leads on the bottom of the board.
This can result in exposed voltages, hot surfaces or sharp edges. Do not reach under the board
during operation.
CAUTION
Some power supplies can be damaged by application of external voltages. If using more than
1 power supply, then check equipment requirements and use blocking diodes or other isolation
techniques, as needed, to prevent damage to equipment.
www.ti.com Introduction
SLUUCH6B – SEPTEMBER 2022 – REVISED SEPTEMBER 2023
Submit Document Feedback
TPS543B22EVM SWIFT Step-Down Converter Evaluation Module 3
Copyright © 2023 Texas Instruments Incorporated

1.3 Performance Characteristics Summary
A summary of the TPS543B22EVM performance characteristics is provided in Table 1-2 and Table 1-3. The
TPS543B22EVM is designed and tested for VIN = 4 V to 18 V. Characteristics are given for an input voltage
of VIN = 12 V and an output voltage of 1.2 V, unless otherwise specified. The ambient temperature is room
temperature (25°C) for all measurements, unless otherwise noted.
Table 1-2. TPS543B22EVM Small Size (U1) Performance Characteristics Summary
SPECIFICATION TEST CONDITIONS MIN TYP MAX UNIT
VIN voltage range 11.7 12 12.3 V
Output voltage setpoint 1.2 V
Output current range VIN = 11.7 V to 12.3 V 0 20 A
Output rise time Set by MODE pin resistor 2 ms
Current limit Set by MODE pin resistor High
Switching frequency (fSW) Set by FSEL pin resistor 2200 kHz
Table 1-3. TPS543B22EVM High Efficiency (U2) Performance Characteristics Summary
SPECIFICATION TEST CONDITIONS MIN TYP MAX UNIT
VIN voltage range 4 12 18 V
Output voltage setpoint J3 short pins 1 and 2 1 V
Output current range VIN = 4 V to 18 V 0 20 A
Output rise time Set by MODE pin resistor, All default J13 options 2 ms
Current limit Set by MODE pin resistor, J9 short pins 1 and 2,
3 and 4, or 5 and 6 High
Switching frequency (fSW) Set by FSEL pin resistor, J7 short pins 3 and 4 1000 kHz
Introduction www.ti.com
4TPS543B22EVM SWIFT Step-Down Converter Evaluation Module SLUUCH6B – SEPTEMBER 2022 – REVISED SEPTEMBER 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

2 Configurations and Modifications
These evaluation modules are designed to provide access to the features of the TPS543B22. The U2 design
provides jumpers for testing different configurations. Jumper selections must be made prior to enabling the
TPS543B22.
If a desired configuration is not available, then some modifications can be made to this module. When
modifications are made to the components on the EVM, the internal compensation option selected with the
MODE pin resistor needs to be changed. Changes to the fSW, output voltage, output inductor, and output
capacitors require a change in the compensation. TPS543B22 data sheet equations or WEBENCH can be used
to calculate the output capacitor value, compensation, fSW, and inductance. Verify all components have sufficient
voltage and current ratings.
2.1 Output Voltage
In the U1 design, the output voltage is set by the resistor divider network of R63 (RFBT) and R60 (RFBB). R60 is
fixed at 10.0 kΩ to set the FB divider current at approximately 50 µA. To change the output voltage of the EVM,
the value of resistor R63 must change. Changing the value of R63 can change the output voltage above the
0.5-V reference voltage (VREF). The value of R63 for a specific output voltage can be calculated using Equation
1. After changing R63, the feedfoward capacitor (C45) can also need to be changed.
RFBT = RFBB ×VOUT
VREF  −1 (1)
In the U2 design, there are a few ways to set the output voltage. First, jumper J6 can be used to select between
the options shown in Table 2-1. If the desired output voltage is not available, a resistor must be changed. For
output voltages less than 1.0 V, TI recommends leaving J3 open and increasing R20. R20 becomes RFBB and
the required value for can be calculated with Equation 2, where RFBT is R7 which is 10 kΩ. For output voltages
greater than 1.0 V, the jumper output voltage options can be changed by changing one of the resistors R16-R19.
The RFBJ resistor value to get a desired equivalent RFBB resistance can be calculated with Equation 3. To use J6
for output voltages 3.3 V or larger, R13 must be reduced from 825 Ω to 0 Ω.
RFBB = RFBT ×VREF
VOUT−VREF (2)
RFBJ =RFBB ×  R13 + R20  −R13 × R20
R20 −RFBB (3)
Table 2-1. VOUT Selection
JUMPER SETTING EQUIVALENT BOTTOM FB RESISTOR (RFBB) NOMINAL OUTPUT VOLTAGE
Open R20 = 10.0 kΩ 1.00 V
1 to 2 pin shorted(1) (R16 + R13)||R20 = 7.15 kΩ 1.20 V
3 to 4 pin shorted (R17 + R13)||R20 = 4.98 kΩ 1.50 V
5 to 6 pin shorted (R18 + R13)||R20 = 3.87 kΩ 1.80 V
7 to 8 pin shorted (R19 + R13)||R20 = 1.8 kΩ 3.3 V
(1) Default Setting
www.ti.com Configurations and Modifications
SLUUCH6B – SEPTEMBER 2022 – REVISED SEPTEMBER 2023
Submit Document Feedback
TPS543B22EVM SWIFT Step-Down Converter Evaluation Module 5
Copyright © 2023 Texas Instruments Incorporated

2.2 Switching Frequency (FSEL Pin)
In the U2 design, jumper J7 can be used to select between the switching frequency options shown in Table 2-2.
If the desired option is not available, change one of the resistors to the value which sets the desired option.
In the U1 design, change the FSEL resistor to the value which sets the desired option.
Table 2-2. FSEL Selection
JUMPER SETTING FSEL RESISTOR SWITCHING FREQUENCY
1 to 2 pin shorted 17.4 kΩ 750 kHz
3 to 4 pin shorted(1) 11.8 kΩ 1000 kHz
5 to 6 pin shorted 8.06 kΩ 1500 kHz
7 to 8 pin shorted 4.99 kΩ 2200 kHz
(1) Default Setting
2.3 Current Limit, Soft-Start Time, and Internal Compensation (MODE Pin)
In the U2 design, jumper J9 can be used to select between the current limit, soft-start time, and internal
compensation options shown in Table 2-3. If the desired option is not available, change one of the resistors to
the value which sets the desired option.
In the U1 design, change the MODE resistor to the value which sets the desired option.
Table 2-3. MODE Selection
JUMPER SETTING MODE RESISTOR CURRENT LIMIT SOFT-START TIME RAMP
1 to 2 pin shorted 2.21 kΩ High 2 ms 1 pF
3 to 4 pin shorted(1) 4.87 kΩ High 2 ms 2 pF
5 to 6 pin shorted 11.3 kΩ High 2 ms 4 pF
7 to 8 pin shorted 60.4 kΩ Low 2 ms 2 pF
(1) Default Setting
2.4 Adjustable UVLO
The undervoltage lockout (UVLO) for U2 can be adjusted externally using R12 (RENT) and R15 (RENB). See the
TPS543B22 4-V to 18-V Input, 20-A Synchronous SWIFT™ Step-Down Converter with Internally Compensated
Advanced Current Mode Control data sheet for detailed instructions for setting the external UVLO.
The undervoltage lockout (UVLO) for U1 is adjusted externally using R55 (RENT) and R57 (RENB).
Configurations and Modifications www.ti.com
6TPS543B22EVM SWIFT Step-Down Converter Evaluation Module SLUUCH6B – SEPTEMBER 2022 – REVISED SEPTEMBER 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

3 Test Setup and Results
This section describes how to properly connect, set up, and use the TPS543B22EVM evaluation module.
The section also includes test results typical for the evaluation module and covers efficiency, output voltage
regulation, load transients, loop response, output ripple, input ripple, start-up, and current limit modes.
Measurements are taken with the following conditions unless otherwise noted.
• 12-V input
• Room temperature (20°C to 25°C)
• U1 with the default setting output voltage of 1.2 V, switching frequency of 2200 kHz, and maximum current
limit setting
• With the other converter disabled
3.1 Input/Output Connections
The TPS543B22EVM is provided with input connectors, output connectors, and test points as shown in Table 3-1
and Table 3-2.
To support the minimum input voltage with the full rated load on both outputs with the default EVM, a power
supply capable of supplying greater than 20 A must be connected to J1 through a pair of 18-AWG wires or
better.
For U2, the load must be connected to J2 and for U1, the load must be connected to J14. Two pair of 18-AWG
wires or better must be used for each connection. With the maximum current limit setting, the maximum load
current capability is near 20 A before the TPS543B22 goes into current limit. Wire lengths must be minimized to
reduce losses in the wires.
Test point TP30 provides a place to monitor the VIN input voltage with TP33 providing a convenient ground
reference for U1. Test point TP2 provides a place to monitor the VIN input voltage with TP9 providing a
convenient ground reference for U2. TP31 is used to monitor the output voltage of U1 with TP36 as the ground
reference. TP1 is used to monitor the output voltage of U2 with TP16 as the ground reference.
If modifications are made to the TPS543B22EVM, then the input current can change. The input power supply
and wires connecting the EVM to the power supply must be rated for the input current.
Note
For the FSEL pin of the TPS543B22 to correctly detect the resistor value connected to ground, the
buffers on the EVM need to be provided a VCC voltage of 2 V to 5.5 V to go high impedance.
www.ti.com Test Setup and Results
SLUUCH6B – SEPTEMBER 2022 – REVISED SEPTEMBER 2023
Submit Document Feedback
TPS543B22EVM SWIFT Step-Down Converter Evaluation Module 7
Copyright © 2023 Texas Instruments Incorporated

Table 3-1. Connectors and Jumpers
REFERENCE
DESIGNATOR NAME RELATED IC FUNCTION
J1 VIN Both VIN screw terminal to connect input voltage (see Table 1-1 for VIN range).
J2 VOUT_P2 U2 VOUT screw terminal to connect load to output.
J3 VOUT Select U2 VOUT selection header. Use shunt to set output voltage. See Table 2-1.
J4 ENSYNC_P2 U2 2-pin header to connect U2 buffer output enable to ground. Populate shunt to enable
output of buffer. Remove shunt to make buffer output high impedance.
J6 VO_2NDSTG U2 Output Second Filter.
J7 FSEL Select U2 FSEL selection header. Use shunt to select FSEL resistor. See Table 2-2.
J8 FSEL Test U2 Test mode 1-2 use pin strap resistors. 2-3 I2C test mode.
J9 MODE Select U2 MODE selection header. Use shunt to select MODE resistor. See Table 2-3.
J10 MODE Test U2 Test mode 1-2 use pin strap resistors. 2-3 I2C test mode.
J14 VOUT_P1 U1 VOUT screw terminal to connect load to output.
J15 EN_OFF_P1 U1 2-pin header for enable. Add shunt to connect EN to ground and disable device.
J16 ENSYNC_P1 U1 2-pin header to connect U4 buffer output enable to ground. Populate shunt to enable
output of buffer. Remove shunt to make buffer output high impedance.
Test Setup and Results www.ti.com
8TPS543B22EVM SWIFT Step-Down Converter Evaluation Module SLUUCH6B – SEPTEMBER 2022 – REVISED SEPTEMBER 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

Table 3-2. Test Points
REFERENCE
DESIGNATOR NAME RELATED IC FUNCTION
TP1 VOUT_P2 U2 VOUT test point. Use this for efficiency, output regulation, and bode plot measurements.
TP2 VIN_P2 U2 VIN test point. Use this for efficiency measurements.
TP3 SW_P2 U2 SW node solder mask opening.
TP4 VDRV_P2 U2 VDRV node test point.
TP5 SW_P2 U2 SW node test point.
TP6 PGOOD_P2 U2 PGOOD test point.
TP7 MSEL_P2 U2 MODE test point.
TP8 AGND_P2 U2 AGND test point.
TP9 PGND_P2 U2 PGND test point.
TP10 VCC_BUF_P2 U2 VDRV Voltage Supply to Buffer.
TP11 GOSNS U2 Remote Sense for U2.
TP12 FSEL_P2 U2 FSEL test point.
TP13 PGND U2 Ground near P2 SYNC input.
TP14 BODE-_P2 U2 Test point between voltage divider network and output voltage. Used for Bode plot
measurements.
TP15 BODE+__P2 U2 Used for Bode plot measurements.
TP16 PGND_VO2_P2 U2 PGND test point. Use this for efficiency measurements.
TP17 EN__P2 U2 EN test point. If user is applying an external voltage, then the external voltage must be
kept below the absolute maximum voltage of the EN pin of 6 V.
TP18 SYNC_P2 U2 SYNC test point. Supply an external clock to this test point to synchronize U1 regulators.
TP19 VO_2NDSTG U2
SMB connector to measure output voltage after second stage filter if added to EVM.
When using this test point, the scope must be set for 1-MΩ termination. When using 50-Ω
termination, a 2:1 divider is created.
TP20 VO2_PGND U2 Ground for second stage filter output.
TP21 ISNS Both Test point to measure current in load transient circuit. Gain is 20 A/V.
TP22 FGEN Both Test point to connect function generator to load transient circuit. Slowly increase amplitude
and vary slew rate of function generator for desired load step.
TP23 ISNS Both Test point to measure current in load transient circuit. Gain is 20 A/V.
TP24 SW_P2 U2
SMB connector to measure SW node. When using this test point, the scope must be set
for 50-Ω termination. The combination of 50-Ω termination and 450-Ω series resistance
creates a 10:1 attenuation.
TP25 VOUT_P2 U2 SMB connector to measure output voltage. When using this test point, the scope must be
set for 1-MΩ termination. When using 50-Ω termination, a 2:1 divider is created.
TP26 VO_2NDSTG U2 Test point to measure output voltage after second stage filter if added to EVM.
TP27 PGND Both PGND test point for load transient circuit.
TP29 VOUT_P1 U1 SMB connector to measure output voltage. When using this test point, the scope must be
set for 1-MΩ termination. When using 50-Ω termination, a 2:1 divider is created.
TP30 VIN_P1 U1 VIN test point. Use this for efficiency measurements.
TP31 VOUT_P1 U1 VOUT test point. Use this for efficiency, output regulation, and bode plot measurements.
TP32 EN_P1 U1 EN test point. If applying an external voltage, then the external voltage must be kept below
the absolute maximum voltage of the EN pin of 6 V.
TP33 PGND_P1 U1 PGND test point.
TP34 PGOOD_P1 U1 PGOOD test point.
TP35 AGND_P1 U1 AGND test point.
TP36 PGND_P1 U1 PGND test point. Use this for efficiency measurements.
TP37 VO_SNS U1 Used for Bode plot measurements.
TP38 BODE-_P1 U1 Test point between voltage divider network and output voltage. Used for Bode plot
measurements.
TP39 VCC_BUF_P1 U1 VDRV Voltage Supply to Buffer.
TP40 PGND_P1 U1 PGND test point.
TP41 SYNC_P1 U1 SYNC test point. Supply an external clock to this test point to synchronize U4 regulators.
www.ti.com Test Setup and Results
SLUUCH6B – SEPTEMBER 2022 – REVISED SEPTEMBER 2023
Submit Document Feedback
TPS543B22EVM SWIFT Step-Down Converter Evaluation Module 9
Copyright © 2023 Texas Instruments Incorporated

3.2 Efficiency
Figure 3-1 and Figure 3-2 show the efficiency for both designs on the TPS543B22EVM. The test points listed
in Table 3-3 are used for the efficiency measurement. Use these test points to minimize the contribution of PCB
parasitic power loss to the measured power loss.
Some additional test setup considerations to minimize external sources of power dissipation are listed below.
• Disable the other regulator to avoid including the switching quiescent current of the other regulator in the
efficiency measurement.
• Do not measure the SW pin of P2 with TP24 while measuring the efficiency of P2. Measuring the SW pin
with this test point loads this node with 500 Ω and the efficiency measurement includes the power lost in this
external resistance.
• Remove the shunt from J8 to use default start voltage for P2.
Table 3-3. Efficiency Measurement Test Points
RELATED IC TEST POINT NAME REFERENCE
DESIGNATOR FUNCTION
U1
VIN_P1 TP30 Input voltage test point connected near pins of P1
VOUT_P1 TP31 Output voltage test point near output inductor of P1
PGND_EFF_P1 TP36, TP33 PGND reference test point for both input and output
voltages Kelvin connected near P1
U2
VIN_P2 TP2 Input voltage test point connected near pins of P2
VOUT_P2 TP1 Output voltage test point near output inductor of P2
PGND_EFF_P2 TP9,TP16 PGND reference test point for both input and output
voltages Kelvin connected near P2
Output Current (A)
Efficiency (%)
0 5 10 15 20
60
65
70
75
80
85
90
95
100
Vout = 1.2V
VIN = 5.0 V, 2.2 MHz
VIN = 8.0 V, 2.2 MHz
VIN = 12.0 V, 2.2 MHz
VIN = 14.0 V, 2.2 MHz
VOUT = 1.2V fSW = 2200 kHz
Figure 3-1. P1 Efficiency
Output Current (A)
Efficiency (%)
0 5 10 15 20 25
70
75
80
85
90
95
100
Vin = 12VVout = 1V
VIN = 5.0 V, 1 MHz
VIN = 8.0 V, 1 MHz
VIN = 12.0 V, 1 MHz
VIN = 14.0 V, 1 MHz
VOUT = 1 V fSW = 1000 kHz
Figure 3-2. P2 Efficiency – Default Configuration
Test Setup and Results www.ti.com
10 TPS543B22EVM SWIFT Step-Down Converter Evaluation Module SLUUCH6B – SEPTEMBER 2022 – REVISED SEPTEMBER 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

3.3 Output Voltage Regulation
Figure 3-3 and Figure 3-4 show the load and line regulation for U1. Figure 3-5 and Figure 3-6 show the load and
line regulation for U2.
Output Current (A)
Output Voltage (V)
0 5 10 15 20
1.19
1.192
1.194
1.196
1.198
1.2
1.202
1.204
1.206
1.208
1.21
VIN = 5 V, 2.2 MHz
VIN = 8.0 V, 2.2 MHz
VIN = 12.0 V, 2.2 MHz
VIN = 14.0 V, 2.2 MHz
Figure 3-3. U1 Load Regulation
Input Voltage (V)
Output Voltage (V)
4.5 6.5 8.5 10.5 12.5 14.5 16.5 18
1.2
1.201
1.202
1.203
1.204
1.205
1.206
1.207
1.208
1.209
1.21
IOUT = 0 A, 2.2 MHz
IOUT = 10 A, 2.2 MHz
IOUT = 20 A, 2.2 MHz
Figure 3-4. U1 Line Regulation
Output Current (A)
Output Voltage (V)
0 5 10 15 20
0.99
0.992
0.994
0.996
0.998
1
1.002
1.004
1.006
1.008
1.01
VIN = 5 V, 1 MHz
VIN = 8.0 V, 1 MHz
VIN = 12.0 V, 1 MHz
VIN = 14.0 V, 1 MHz
Figure 3-5. U2 Load Regulation
Input Voltage (V)
Output Voltage (V)
4 6 8 10 12 14 16 18
0.995
0.996
0.997
0.998
0.999
1
1.001
1.002
1.003
1.004
1.005
IOUT = 0 A, 1 MHz
IOUT = 10 A, 1 MHz
IOUT = 20 A, 1 MHz
Figure 3-6. U2 Line Regulation
www.ti.com Test Setup and Results
SLUUCH6B – SEPTEMBER 2022 – REVISED SEPTEMBER 2023
Submit Document Feedback
TPS543B22EVM SWIFT Step-Down Converter Evaluation Module 11
Copyright © 2023 Texas Instruments Incorporated

3.4 Load Transient and Loop Response
Figure 3-7 and Figure 3-8 show the response to load transients for both designs. The current step is from 0-A to
10-A and the current step slew rate is 1 A/µs. An electronic load is used to provide a DC 0-A load and the load
transient circuit on the EVM is used to provide a 10-A step. The VOUT voltage is measured using TP10 for U1
and TP29 for U2.
When using the load transient circuit included on the TPS543B22EVM, slowly increase amplitude of function
generator for desired load step amplitude then vary the rise and fall times for the desired slew rate. The current
for the load step can be sensed with the ISNS test point. The default resistors on the EVM provide a gain of
66.66 A/V. With this gain, a 10-A step results in 150-mV at the ISNS test point.
Note
To use the load transient circuit with U1, move R27 to R28.
Figure 3-9 and Figure 3-10 show the loop characteristics for both designs. Gain and phase plots are shown for
VIN voltage of 12 V and a 20-A load.
ILOAD (13.3A/div)
VOUT (50mV/div) AC coupled
VIN=12V IOUT = 0A to 20A 200 s/div
SW (10V/div)
Figure 3-7. U1 Transient Response
ILOAD (20A/div)
VOUT (20mV/div) 1V dc o  set
VIN=12V IOUT = 0A to 20A 200 s/div
SW (10V/div)
Figure 3-8. U2 Transient Response
Frequency (Hz)
Gain (dB)
Phase (Degrees)
1000 2000 5000 10000 100000 1000000
-40 -200
-30 -150
-20 -100
-10 -50
0 0
10 50
20 100
30 150
40 200
50 250
60 300
70 350
80 400
Vin = 12 V, Vout = 1.2 V
Iout = 20 A 2200 kHz 2pF
Gain
Phase
Figure 3-9. U1 Bode Plot
Frequency (Hz)
Gain (dB)
Phase (Degrees)
1000 2000 5000 10000 100000 1000000
-40 -200
-30 -150
-20 -100
-10 -50
0 0
10 50
20 100
30 150
40 200
50 250
60 300
70 350
80 400
Vin = 12 V, Vout = 1.0 V
Iout = 20 A 1000 kHz 2pF
Gain
Phase
Figure 3-10. U2 Bode Plot
Test Setup and Results www.ti.com
12 TPS543B22EVM SWIFT Step-Down Converter Evaluation Module SLUUCH6B – SEPTEMBER 2022 – REVISED SEPTEMBER 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

3.5 Output Voltage Ripple
Figure 3-11 through U2 Output Ripple - 20A show the TPS543B22EVM output voltage ripple. The load currents
are no load and 20 A. VIN = 12 V. The VOUT voltage is measured using TP29 for U1 and TP25 for U2.
VIN=12V IOUT = 0A 400ns/div
VOUT (20m/div) AC coupled
ILOAD (20A/div)
SW (10V/div)
Figure 3-11. U1 Output Ripple – No Load
VIN=12V IOUT = 20A 400ns/div
VOUT (20m/div) AC coupled
ILOAD (20A/div)
SW (10V/div)
Figure 3-12. U1 Output Ripple – 20 A Load
ILOAD (10A/div)
VOUT (10mV/div) 1V dc o

set
VIN=12V IOUT = 0A 2 s/div
SW (10V/div)
Figure 3-13. U2 Output Ripple – No Load
ILOAD (10A/div)
VOUT (10mV/div) 1V dc o

set
VIN=12V IOUT = 20A 2 s/div
SW (10V/div)
Figure 3-14. U2 Output Ripple – 20 A Load
www.ti.com Test Setup and Results
SLUUCH6B – SEPTEMBER 2022 – REVISED SEPTEMBER 2023
Submit Document Feedback
TPS543B22EVM SWIFT Step-Down Converter Evaluation Module 13
Copyright © 2023 Texas Instruments Incorporated

3.6 Input Voltage Ripple
Figure 3-15 through U2 Input Ripple - 20 A Load show the TPS543B22EVM input voltage ripple. The load
currents are no load and 20 A. VIN = 12 V. The ripple voltage is measured across C40 for U1 and measured
across C13 for U2.
VIN=12V IOUT = 0A 400ns/div
VIN ac coupled (20mV/div)
ILOAD (10A/div)
SW (10V/div)
Figure 3-15. U1 Input Ripple – No Load
VIN=12V IOUT = 20A 400ns/div
VIN ac coupled (100mV/div)
ILOAD (10A/div)
SW (10V/div)
Figure 3-16. U1 Input Ripple – 20 A Load
ILOAD (10A/div)
VOUT (20mV/div) ac coupled
VIN=12V IOUT = 0A 1 s/div
SW (10V/div)
Figure 3-17. U2 Input Ripple – No Load
ILOAD (10A/div)
VIN (200mV/div) ac coupled
VIN=12V IOUT = 20A 1 s/div
SW (10V/div)
Figure 3-18. U2 Input Ripple – 20 A Load
Test Setup and Results www.ti.com
14 TPS543B22EVM SWIFT Step-Down Converter Evaluation Module SLUUCH6B – SEPTEMBER 2022 – REVISED SEPTEMBER 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

3.7 Synchronizing to a Clock
Figure 3-19 shows U1 and U2 synchronized to an external clock of 1.25 MHz at the SYNC test point. To
synchronize to the clock at the SYNC test point, place a shunt on the ENSYNC_U1 or ENSYNC_U2 jumper or
jumpers to enable the output of the buffers.
Figure 3-20 shows the transitions to and from synchronizing to an external clock with 20-A load. 16 pulses with
a frequency of 1-MHz were sent to the SYNC testpoint on the EVM. In this waveform, after four pulses, the
TPS543B22 begins synchronizing to the clock. After the clock goes away, the TPS543B22 switches at 70% of
the internal clock frequency for four pulses then transitions back to the normal internal clock frequency. There is
only a small variation in the output voltage during these transitions.
Figure 3-19. U1 and U2 Synchronized to a Clock
Figure 3-20. U2 Clock Synchronization Transitions
www.ti.com Test Setup and Results
SLUUCH6B – SEPTEMBER 2022 – REVISED SEPTEMBER 2023
Submit Document Feedback
TPS543B22EVM SWIFT Step-Down Converter Evaluation Module 15
Copyright © 2023 Texas Instruments Incorporated

3.8 Start-up and Shutdown with EN
Figure 3-21 and Figure 3-22 show the start-up and shutdown waveforms for U2 with EN. In Figure 3-21, the
input voltage is initially applied and the output is inhibited by pulling EN to GND using an external function
generator. When the EN voltage is increased above the enable-threshold voltage, the start-up sequence begins
and the output voltage ramps up to the externally set value. In Figure 3-22, the external function generator pulls
EN to ground and the TPS543B22 shuts down.
Figure 3-23 shows the VDRV internal LDO start-up relative to the EN pin.
A shunt on the ENOFF_U1 jumper or RDIV_VIN can be used to test the EN start-up of U1 and U2, respectively.
When the shunt is removed from ENOFF_U1, EN is released and the start-up sequence begins for U1. When
the shunt is placed on RDIV_VIN, EN is pulled to the input voltage through the resistor divider and the start-up
sequence begins for U2.
SW (5V/div)
VOUT (500mV/div)
PGOOD (5V/div)
EN (2V/div)
VIN=12V IOUT = 0A 1 ms/div
Figure 3-21. U2 Start-up with EN – No Load
VOUT (500mV/div)
PGOOD (5V/div)
EN (2V/div)
VIN=12V IOUT = 0A 10 ms/div
SW (5V/div)
Figure 3-22. U2 Shutdown with EN – No Load
EN (2V/div)
VOUT (500mV/div)
VDRV (5V/div)
VIN (10V/div)
VIN=12V IOUT = 0A 400s/div
Figure 3-23. U2 Startup with EN – No Load and Measuring VDRV
Test Setup and Results www.ti.com
16 TPS543B22EVM SWIFT Step-Down Converter Evaluation Module SLUUCH6B – SEPTEMBER 2022 – REVISED SEPTEMBER 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

3.9 Start-up and Shutdown with VIN
U2 Start-Up with VIN and U2 Shutdown with VIN show the start-up and shutdown waveforms for U2 with VIN.
In U2 Start-Up with VIN, the VIN voltage ramps up and output voltage ramps up after the input and EN pin
voltages reach their respective UVLO threshold. In U2 Shutdown with VIN, the VIN voltage ramps down and the
TPS543B22 shuts down when the input or EN pin voltage reach their respective UVLO threshold. The rate at
which VIN ramps down changes as soon as the TPS543B22 is disabled because the device is no longer loading
the input supply.
VOUT (500mV/div)
PGOOD (5V/div)
VIN (5V/div)
VIN=12V IOUT = 0A 2 ms/div
EN (5V/div)
Figure 3-24. U2 Start-up with VIN
VOUT (500mV/div)
PGOOD (5V/div)
VIN (5V/div)
VIN=12V IOUT = 10A 2 ms/div
EN (5V/div)
Figure 3-25. U2 Shutdown with VIN
www.ti.com Test Setup and Results
SLUUCH6B – SEPTEMBER 2022 – REVISED SEPTEMBER 2023
Submit Document Feedback
TPS543B22EVM SWIFT Step-Down Converter Evaluation Module 17
Copyright © 2023 Texas Instruments Incorporated

3.10 Start-up Into Pre-Bias
Figure 3-26 shows the EN start-up of U2 into a pre-biased output. The output voltage is pre-biased by toggling
the EN pin low then high at a rate such that the output voltage does not fully discharge before EN goes high
again.
SW (5V/div)
VOUT (500mV/div)
PGOOD (5V/div)
EN (2V/div)
VIN=12V IOUT = 0A 400s/div
Figure 3-26. U2 Start-up Into 0.5-V Pre-Bias
Test Setup and Results www.ti.com
18 TPS543B22EVM SWIFT Step-Down Converter Evaluation Module SLUUCH6B – SEPTEMBER 2022 – REVISED SEPTEMBER 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

3.11 Hiccup Current Limit
These waveforms show the TPS543B22 entering hiccup with an overload. The TPS543B22 tries to restart after
the Hiccup wait time period but the overload was still present on the output.
VIN=12V 4ms/div
VOUT (2V/div)
ILOAD (10A/div)
SW (10V/div)
Figure 3-27. U1 Output Overcurrent Protection –
Overload
ILOAD (10A/div)
VOUT (1V/div)
VIN=12V 4 ms/div
SW (10V/div)
Figure 3-28. U2 Output Overcurrent Protection –
Overload
www.ti.com Test Setup and Results
SLUUCH6B – SEPTEMBER 2022 – REVISED SEPTEMBER 2023
Submit Document Feedback
TPS543B22EVM SWIFT Step-Down Converter Evaluation Module 19
Copyright © 2023 Texas Instruments Incorporated

3.12 Thermal Performance
Figure 3-29 through Figure 3-32 show the temperature rise of the TPS543B22 ICs at full 20-A load. Figure 3-29
and Figure 3-30 have only one TPS543B22 on and loaded. Figure 3-31 and Figure 3-32 have both TPS543B22s
loaded. A minimum of a 10 minute soak time was used before taking each measurement.
Figure 3-29. U1 Thermal Performance – 20-A Load
and U2 Off
Figure 3-30. U2 Thermal Performance – 20-A Load
and U1 Off
Figure 3-31. U1 Thermal Performance – Both 20-A
Load
Figure 3-32. U2 Thermal Performance – Both 20-A
Load
Test Setup and Results www.ti.com
20 TPS543B22EVM SWIFT Step-Down Converter Evaluation Module SLUUCH6B – SEPTEMBER 2022 – REVISED SEPTEMBER 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated