Texas Instruments TPS6594-Q1 Series User manual

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TPS6594x-Q1 Evaluation Module
User's Guide
SLVUBT0–December 2019
TPS6594x-Q1 Evaluation Module
The TPS6594x-Q1 Evaluation Module (EVM) highlights the performance and flexibility of the TPS6594x-
Q1 power management integrated circuit (PMIC). The modular design allows the EVMs to be stacked to
provide a multi-PMIC solution with a single PMIC acting as the master and up to five PMIC slaves. This
document should be used in conjunction with the Programmable Processor PMIC's GUI User's Guide
SLVUBT8 and the TPS6594x-Q1 Power Management IC (PMIC) with 4-phase 14-A Buck for Processors
SLVSEA7.
Contents
1 Introduction ................................................................................................................... 3
2 Getting Started............................................................................................................... 3
2.1 Getting Started: Single EVM ...................................................................................... 3
2.2 Getting Started: Multiple EVM Evaluation ....................................................................... 4
2.3 The GUI Tool........................................................................................................ 4
3 EVM Details .................................................................................................................. 5
3.1 Terminal Blocks..................................................................................................... 5
3.2 Test Point Descriptions ............................................................................................ 5
3.3 Configuration Headers ............................................................................................. 6
3.4 Signal Headers...................................................................................................... 8
3.5 Stack-up Headers................................................................................................... 9
3.6 Connectors......................................................................................................... 12
3.7 EVM Control, GPIO, and additional regulators................................................................ 12
4 Customization............................................................................................................... 12
4.1 Changing the Communication Interface........................................................................ 12
4.2 Changing the Phase Configuration ............................................................................. 14
5 Additional Resources ...................................................................................................... 15
6 Schematic, Layout, and Bill of Materials ................................................................................ 16
7 Typical Data................................................................................................................. 27
8 EMI Data .................................................................................................................... 27
9 Thermal Data ............................................................................................................... 27
List of Figures
1 EVM Top View ............................................................................................................... 4
2 EVM Header J7.............................................................................................................. 6
3 LDO Headers................................................................................................................. 8
4 EVM Masters Slave Configuration......................................................................................... 9
5 EVM Bottom View.......................................................................................................... 10
6 Header J37, Recommended Power Sequence (Enable) for Master and One or More Slaves .................. 11
7 Interface Settings for I2C Communication............................................................................... 13
8 Interface Settings for SPI Communication.............................................................................. 14
9 Phase Configuration Components ....................................................................................... 15
10 Schematic Page 1.......................................................................................................... 16
11 Schematic Page 2.......................................................................................................... 17
12 Layout Top, Layer 1........................................................................................................ 18
13 Layout Ground, Layer 2 .................................................................................................. 19
14 Layout Signal, Layer 3..................................................................................................... 20

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15 Layout Signal, Layer 4..................................................................................................... 21
16 Layout Ground, Layer 5 ................................................................................................... 22
17 Layout Bottom .............................................................................................................. 23
List of Tables
1 EVM Descriptions............................................................................................................ 3
2 Terminal Blocks.............................................................................................................. 5
3 Test Point Descriptions ..................................................................................................... 5
4 Header J7 Description ...................................................................................................... 6
5 Header J26, VBACKUP..................................................................................................... 7
6 Header J30 VIO_IN Voltage Select ....................................................................................... 7
7 Header J15, USB_3V3/VSYS/VBUS, GPIO1/I2C/SPI.................................................................. 7
8 Header J8 Pullup Voltages................................................................................................. 9
9 Header J37 Master/Slave Select......................................................................................... 11
10 EVM LED Indicators ....................................................................................................... 12
11 Bill of Materials of Balance of Components............................................................................. 24

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1 Introduction
The TPS65941x-Q1 power management integrated circuit (PMIC) family is extremely flexible and scalable,
providing configurability at the device and system level. At the device level, a single PMIC can provide up
to five separate step down converters (BUCK regulators) and four LDOs. Four of these BUCK regulators
can be used in multi-phase mode to provide a single 14A source. At the system level, several PMICs can
be configured to work in a master-slave topology with one master and up to five slave PMICs. The
TPS65941x-Q1 evaluation module (EVM) is both an evaluation and development tool. With the EVM both
device level and system level configurability are available through an easy to use graphical user interface
(GUI) tool.
Table 1 shows the available master and slave EVMs, the silicon associated with those EVMs, the initial
non-volatile memory (NVM) configuration, and the hardware components associated with the
configurations. Because of the configurable nature of both the part and the EVM, any EVM can be
configured as a master or slave device. Master and slave configurations are provided to facilitate getting
started and to accelerate development.
Table 1. EVM Descriptions
EVM Part Number PMIC Device Part
Number Mode NVM Phase Configuration Components on the Back Side of EVM
R1-R7 J23,J24,J25
TPS659413EVM PTPS659413F0RW
ERQ1 Master BUCK1+BUCK2, BUCK3, BUCK4, and BUCK5 R1,R2,R5, and R7 J23
TPS659411EVM PTPS659411F0RW
ERQ1 Slave BUCK1+BUCK2+BUCK3 +BUCK4, and BUCK5 R1,R2,R4,and R6 J23,J24, and J25
2 Getting Started
Only a power supply and the EVM are required to evaluate and test the TPS6594x-Q1 default
configuration under load conditions. This section contains the master and master+slave configurations and
how to run these two default configurations.
2.1 Getting Started: Single EVM
1. Connect Power to the EVM.
2. Connect the EVM to the Host PC through the USB. In the event that the power is provided by the USB
cable, apply the appropriate jumper connection to connect VBUS and VSYS see Table 7.
3. Launch the GUI and evaluate.
Terminal J6, labeled VSYS_IN in Figure 1, can accept wire gauges up to 14 AWG. The voltage supplied
must be within the input range of the device, 2.7 V to 5.5 V. The power supply providing the input to
VSYS_IN is required to supply 120% of the output power. Once power has been supplied to VSYS_IN, the
pullup on nPWRON/ENABLE pin will enable the device and the power output rails will activate. The
default ON Request for the master device is the ENABLE pin which is a level sensitive input. Please refer
to SLVSEA7 for more details.
Figure 1 shows the TPS659413EVM (master).

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Figure 1. EVM Top View
2.2 Getting Started: Multiple EVM Evaluation
1. Connect Power to one EVM and remove the jumpers on all EVMs shorting VBUS and VSYS. All VCCA
and GND power pins are shared between the stacked EVMs.
2. Connect one EVM to the Host PC through the USB. In the event that the power is provided by the USB
cable, apply the appropriate jumper connection to connect VBUS and VSYS seeTable 7.
3. Stack Master EVM and Slave EVM(s). For convenience it is recommended to place the Master on the
top of the stack.
4. Launch the GUI and evaluate.
The EVM can be powered solely from the 5 V USB connection (either 5V VUSB or 3.3V USB_3V3),
provided that the total load is less than 3 W. This removes the requirement for a separate supply when
evaluating a number of the digital features of the PMIC with the EVM.
The three distinguishing characteristics of the slave EVM are the PMIC, the backside components
described in Figure 9, and the jumper position on J37. With the jumper on J37 placed in the slave position,
the ENABLE pin of the slave PMIC is connected to the VOUT_LDOINT output pin of the master PMIC
through the J29 Stack-up header. Once the master and slave devices are stacked, supplying power on J6
is the only requirement for getting started. VSYS_IN is connected to VCCA and distributed across all
stacked boards through J28. The power supply can be applied to any of the available J6 terminals.
2.3 The GUI Tool
Texas Instruments provides a GUI tool to enable, configure, and evaluate the various features of the
TPS6594x-Q1 with the EVM. Please refer to the GUI User's Guide SLVUBT8 for a more detailed
description of this tool.

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(1) See Section 3.4 for applying input voltages other than VSYS_IN to the LDO regulators through J21
The GUI will run on most PC platforms and requires an available USB port. The EVM USB connector is
type-C and a type-A to type-C cable is provided with the EVM to connect to the host computer. The EVM
will enumerate as two COM ports and one additional port for the devices firmware updates. The port the
GUI should use is the ACCtrl COM port (and not the ACCtrl Console).
3 EVM Details
The following sections describe the various interfaces for measuring and controlling the configuration.
Note: the configurations are in coordination with the settings of the PMIC. It is important to understand that
both the EVM configuration and the settings of the PMIC must match. For example, if the GUI is used to
change the PMIC interface to SPI from I2C, then the appropriate SPI related jumpers should be in place
on J7 and J15. Please refer to the GUI User's Guide SLVUBT8 on how to update the PMIC
communication protocol.
3.1 Terminal Blocks
The terminal blocks are simple push and release terminals which can accommodate wire sizes up to 14
AWG. Table 2 lists the terminal blocks found around the perimeter of the EVM. J6, VSYS_IN, is the input
voltage for all regulators (BUCK and LDO). (1) The remaining 5 terminal blocks are the BUCK outputs.
Table 2. Terminal Blocks
Terminal Designator Description
VSYS_IN J6 All Regulator Input (PVIN_LDOx, PVIN_Bx), 2.7 V to 5.5 V Range
BUCK1 J1 Buck 1 Output, 3.5 A Capable
BUCK2 J2 Buck 2 Output, 3.5 A Capable
BUCK3 J3 Buck 3 Output, 3.5 A Capable
BUCK4 J4 Buck 4 Output, 4 A (single phase) or 3.5 A Capable
BUCK5 J5 Buck 5 Output, 2 A Capable
3.2 Test Point Descriptions
Numerous test points are provided to access voltages and signals. All test points are designed for sensing
voltages only and are not designed to carry large DC currents.
Table 3. Test Point Descriptions
Test Point Device Pin Description
TP1 VCCA This point can be used to measure IDDQ,
when resistor R58 is removed.
TP2 VIO_IN This point can be used to measure IDDQ
when resistor R65 is removed.
TP3, TP4, TP5 GND NA
TP6 FB_B3 External voltage monitor connection.
TP7 FB_B4
TP8 GPIO10 (SYNCCLKIN) Sync Clock input, up to 4.4 Mhz
TP9 SW_B1 Test Point for the switch mode.Not
populated to reduce EMI.
TP10 SW_B2
TP11 SW_B3
TP12 SW_B4
TP13 SW_B5
TP14 GND NA

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3.3 Configuration Headers
There are five headers available to configure the EVM function. Headers J26 and J37 configure the
backup power supply and master and slave mode of operation, respectively. Header J7, as shown in the
silk screen picture in Figure 2, is used to configure the EVM to match the feature setting written to the
TPS6594x-Q1 configuration registers. J30 is used to select the PMIC IO voltage, either 1.8 V or 3.3 V.
The fifth header is a portion of J15 which allows VSYS to be powered from the USB connection and the
configuration of GPIO1.
Figure 2. EVM Header J7
Table 4. Header J7 Description
Option Pins Configuration Description
SPI_EN Open (Default) I2C Mode. The signal path for I2C communication between the
MCU and the PMIC is enabled.
Closed SPI mode. The signal path for SPI communication between the
MCU and the PMIC is enabled.
TRIG_WDG, GPIO2,
SDA2/SDO Open GPIO mode. GPIO2 from PMIC is connected to PM7 of the MCU through a level translator.
TRIG_WDG, GPIO2: Closed Trigger Watchdog mode. GPIO2 of the PMIC should be in the
Alternative function to support the watchdog trigger input signal.
GPIO2 from the PMIC is connected to the MCU output and
TRIG_WDG.
GPIO2,SDA2/SDO: Closed
(Default) I2C Mode (J7 VIO_IN, I2C/SPI: Open) Q&A Watchdog mode. GPIO2 of the PMIC should be in the
Alternative function to support
the Q&A Watchdog and the I2C
mode is selected. This setting
is done in conjunction with J15,
GPIO1,SCL2/CS: Closed.
SPI mode (J7 VIO_IN, I2C/SPI:
Closed) SPI mode, Chip Select. GPIO2 of the PMIC should be in the
Alternative function to support
SPI communication. This
setting is done in conjunction
with J15, GPIO1, SCL2/CS:
Closed.
ERR_SoC, GPIO3 Open (Default) GPIO mode. GPIO3 of the PMIC is connected to PP5 of the
through a level translator.
Closed SoC Error Count Down mode. GPIO3 of the PMIC should be in
the Alternative function to support the system error count down
from the SoC. GPIO is connected to alternative MCU output,
nERR_SoC.

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Table 4. Header J7 Description (continued)
Option Pins Configuration Description
ERR_MCU, GPIO7 Open (Default) GPIO mode. GPIO7 of the PMIC is connected to POH of the
through a level translator.
Closed MCU Error Count Down mode. GPIO7 of the PMIC should be in
the Alternative function to support the system error count down
from the MCU. GPIO7 is connected to MCU output PK5,
nERR_MCU.
TRIG_WDG, GPIO11 Open (Default) GPIO mode. GPIO11 from PMIC is connected to PP4 of the
MCU through a level translator.
Closed Trigger Watchdog mode. GPIO11 of the PMIC should be in the
Alternative function to support the watchdog trigger input signal.
GPIO11 from the PMIC is connected to the MCU output PK4,
TRIG_WDG.
Table 5. Header J26, VBACKUP
Configuration
Open VBACKUP is not connected.
Pin1, Pin2: Closed (Default) VCCA is connected to the PMIC Battery Backup and VBACKUP.
Pin2, Pin3: Closed Cell C3 is connected to the PMIC Battery Backup and
VBACKUP.
NOTE: C3 is not populated on the EVM, but left to the end user to populate with either a coin cell or
super cap, depending upon the desired use case.
Table 6. Header J30 VIO_IN Voltage Select
Configuration Description
Open Not Allowed, 1.8 V or 3.3 V must be selected.
VIO Select, 3.3 V: Closed (Default) VIO_IN is 3.3 V.
VIO Select, 1.8 V: Closed VIO_IN is 1.8 V.
In addition to J7 and J26, the lower portion of J15 is also used for the selection of VSYS and GPIO1.
Table 7. Header J15, USB_3V3/VSYS/VBUS, GPIO1/I2C/SPI
Configuration Description
USB_3V3, VSYS: Closed (Default) 3.3 V fromTLV710-Q1 (U6) is connected to VSYS (VCCA). The input for U6 is the 5 V
from the USB connection (VBUS). VBUS is not intended to support heavy load
conditions of greater than 3 W. This is the default state of the EVM.
VSYS, VBUS, and USB_3V3: Open VSYS, VBUS, and USB_3V3 are isolated. VSYS should be powered from J6.
VSYS, VBUS: Closed +5 V from USB Port is connected to VSYS (VCCA). This supply is not intended to
support heavy load conditions of greater than 3 W.
SCL2/CS, GPIO1: Open GPIO mode. GPIO1 of the PMIC is connected to IO1 of the MCU.
SCL2/CS, GPIO1: Closed (Default) I2C mode (J7 VIO_IN, I2C/SPI: Open) Q&A Watchdog mode. GPIO1 of the PMIC
should be in the Alternative function to
support the Q&A Watchdog and the I2C
mode selected. This setting is done in
conjunction with J7, GPIO2, SDA2/SDO:
Closed
SPI mode (J7 VIO_IN, I2C/SPI: Closed) SPI mode, Chip Select. GPIO1 of the
PMIC should be in the Alternative function
to support SPI communication. This
setting is done in conjunction with J7,
GPIO2, SDA2/SDO: Closed

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NOTE: The PMIC device can be configured for a power good level of 3.3 V or 5.0 V for the VCCA
pin. Align the USB_3V3/VSYS/VBUS jumper with the PMIC configuration. The default PMIC
configuration is 3.3 V.
3.4 Signal Headers
Signal headers are provided for the LDOs, BUCK regulators, and GPIO signals. Headers J13 (LDOs), J12
(BUCKs), and J11 (GPIOs) are placed on the perimeter of the board to enable probing of these signals
even when in a stacked configuration.
There are 6 signal headers associated with the LDO; five are shown in the EVM silk screen capture,
Figure 3. These include J20 and J21, the power inputs to the LDOs, J14 and J13 , the LDO outputs, and
J18 and J19 which can be used to measure Power Supply Rejection Ratio (PSRR) on LDO3 and LDO4.
All pins of J20 are connected to the VCCA, and J20 is placed next to J21 to easily connect all the LDO
power inputs to the VCCA; this is the default jumper configuration. An external power supply for the LDOs
can also be applied directly to J21.
Figure 3. LDO Headers
NOTE: J13 and J14 provide the same LDO outputs; however, J13 should only be used for probing.
J14 provides a shorter and wider trace, lowering the impedance and supporting maximum
loads of 500 mA. Also, pin 7 is a different signal for J13 and J14; GND_S and AMUXOUT,
respectively.
Signal Header J12 provides access to all of the buck regulator outputs, GND_S and VCCA_S.
NOTE: Header J12 should only be used for voltage probing and not for power delivery.
GPIO signals are provided on both J9 and J11. J8 (PU) is located directly above J9 enabling each GPIO
to be pulled to the voltage defined in table x through a 10 kΩresistor pullup. J10 (PD) is located directly
below J9 to enable shorting each GPIO directly to GND.

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Table 8. Header J8 Pullup Voltages
J8, Pin(s) Pullup Voltage Description
1,2,7-11 VIO_IN GPIO1,GPIO2, GPIO7-11: Output Type
Selection; Power Domain is VIO
3,4 VOUT_LDOVRTC GPIO3 and GPIO4: Input Type Selection;
Power Domain is VRTC
5,6 VOUT_LDOVINT GPIO5 and GPIO6: Output Type
Selection; Power Domain is VINT
3.5 Stack-up Headers
As shown in , multiple boards can be configured into a master-slave relationship (1 master and up to 5
slaves) and physically stacked upon each other. VCCA and GND are shared between boards on headers
J27 and J28. Communication between the boards is shared on header J29. This header, J29, is marked
on the bottom silkscreen, as shown in Figure 5.
Figure 4. EVM Masters Slave Configuration

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Figure 5. EVM Bottom View
The J29 signal, nPWRON_S, and the nPWRON/ENABLE or VOTU_LDOVINT signals of the PMIC are
connected through J37. When multiple PMICs are stacked, as shown in Figure 6, the expectation is that
the master is placed in master mode, connecting the stackable signal nPWRON_S, and the
VOUT_LDOVINT. By using this stackup configuration, one or more of the slaves power up sequence will
always follow the master. When in master mode or when the header J37 is left open the
nPWRON/ENABLE pin can be controlled with the EVM push button and S1.

Master
VOUT_LDOVINT
nPWRON_S
nPWRON/ENABLE
J37
J29
Slave
VOUT_LDOVINT
nPWRON/ENABLE
J37
J29
Slave
VOUT_LDOVINT
nPWRON/ENABLE
J37
J29
nPWRON_S
nPWRON_S
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Figure 6. Header J37, Recommended Power Sequence (Enable) for Master and One or More Slaves
Table 9. Header J37 Master/Slave Select
Configuration Description
Open When used as a single PMIC (no stacking). ENABLE is
connected to a pullup and therefore automatically enabled. S1
can be used to generate edges or change the level.
Slave, M/S Select: Closed Slave Mode. The PMIC signal ENABLE is connected to the
nPWRON_S signal which is from the master's VOUT_LDOVINT.
M/S Select, Master: Closed Master Mode. The PMIC signal, VOUT_LDOVINT, is connected
to the nPWRON_S which will be the ENABLE signal on the
PMICs connected as slaves.

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3.6 Connectors
In addition to J12 and the terminal connections, J32-J36 are SMA connectors for testing the buck
regulator outputs. These connectors are not populated.
Two load module connector footprints are provided, J16 and J17. The connector components are not
populated.
3.7 EVM Control, GPIO, and additional regulators
The EVM has a built-in USB interface based upon the MSP432E401Y (U3) to allow the GUI, from the host
computer, to communicate with the PMIC. The supply voltage required by the MSP432E401Y is generated
automatically by the TLV7103318 (U6) device which provides 3.3 V and 1.8 V from USB power, VBUS.
These voltages are available for supplying VIO_IN for the PMIC (selectable from J30). Two
SN74GTL2003 level shifters (U8, U9) are used in order to support the use case of the PMIC VIO_IN of 1.8
V (the MCU IO will always be 3.3 V). In addition to the level translators, the TS3A5018RSVR switch is
used to apply the pullup voltages to the I2C lines only when the EVM is a master (J37). The application of
the pullup resistors is for I2C mode only and is only intended for one board in a stack-up application. Note:
in the stack-up configuration only one board can have a valid VBUS voltage on the board. This means that
the master board can have a connected USB cable supplying VBUS or that VSYS can be connected to
VBUS through J15, see Table 7. The EVM has 4 LEDs to indicate board power, on or off, and some
select PMIC GPOs status. The signals are listed in Table 10.
Table 10. EVM LED Indicators
LED Designator Indication
D3 LED is on when EN_DRV is high.
D4 LED is on when nINT is low.
D5 LED is on when nRSTOUT is low.
D6 EVM power indicator. LED is on when VCCA is higher than 2.8
V.
4 Customization
The EVM, in conjunction with GUI tool, provides various degrees of customization. A couple of examples
are provided here which can be generalized to a number of functions.
4.1 Changing the Communication Interface
The default settings for communication with the PMIC is I2C. This default configuration for GPIO1 and
GPIO2 are the function settings SCL_I2C2 and SDA_I2C2, respectively.

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Figure 7. Interface Settings for I2C Communication
Changing to SPI requires a minor change to the jumper settings and those settings will change in the case
of multiple EVMs in a stackup configuration. These jumper settings are highlighted in yellow in Figure 8.
The first jumper to place is on the SPI_EN option on connector J7. Placing this jumper will connect the
micro controller to the SPI bus which is connected to all available PMICs through the EVM stack
connection through J29. In a multiple EVM stackup, this jumper should only be placed on the EVM with
the USB connection to the host computer. The SPI does not have a device ID and therefor the chip select
is used to determine which PMIC will receive and respond to commands on the SPI bus. The signals
SCL2/CS and GPIO1 on J15 should only be jumpered on the EVM which is intended to communicate with
the GUI (through the micro controller). All other EVMs which are stacked should pull GPIO1 high, so that
the PMIC does not respond or interfere with the SPI communication.

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Figure 8. Interface Settings for SPI Communication
4.2 Changing the Phase Configuration
As shown in Figure 9, there are five possible phase configurations. It is important that the phase
configuration of the EVM matches the phase configuration of the PMIC. Specific consideration should be
given to BUCK3 and BUCK4 in phase configurations 1 and 2, since these regulators have independent
feedback circuits which can be configured to measure external supplies. FB_B3 and FB_B4 are made
available on test points TP6 and TP7 respectively. If the voltage monitors associated with BUCK3 and
BUCK4 are disabled, then it is recommended to connect the FB_Bn pins to reference ground, using R4
and R6.

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Figure 9. Phase Configuration Components
5 Additional Resources
•Programmable Processor PMIC's GUI User’s Guide
• TPS65921-Q1 Power Management IC (PMIC) With 4-Phase 14-A Buck for ProcessorsTPS65921-Q1
Power Management IC (PMIC) With 4-Phase 14-A Buck for Processors

VCCA
SW_B1
OSC32KIN
OSC32KCAP
OSC32KOUT
OVPGDRV
FB_B1
VCCA
Q1
47µF
C24
L1 470nH
10V
D1
J6
C3
J1VOUT_B1
J2
J3
J4
J5
L2 470nH
L3 470nH
L4 470nH
L5 470nH
VOUT_LDOVINT
VOUT_LDOVRTC
VOUT_LDO1
VOUT_LDO2
VOUT_LDO3
VOUT_LDO4
VSYS
680µF
C79
AMUXOUT
PVIN_LDO4
PVIN_LDO3
PVIN_LDO12
C55
10uF
TP1 TP2
Note: The capacitors in the schematic are populated
for max load use case; actual capacitor placement
should be reconfigured according to actual use cases.
nPWRON_S
10k
R27
12
S1
Note: Jumper on J37-2-3 for Master to provide power
on signal (LDOVINT) for slaves; all slaves jumper on
J37-1-2 to get power on signal (ENABLE) from master.
No jumper on J37 when single PMIC is used.
VOUT_LDOVINT
2.2uF
C8
2.2uF
C10
2.2uF
C11
2.2uF
C12
2.2uF
C13
2.2uF
C15
VIO_IN
SW_B2
SW_B3
SW_B4
SW_B5
FB_B2
FB_B3
FB_B4
FB_B5
FB_B1
FB_B3
FB_B4
FB_B5
FB_B2
Phase Config R2/R3 R4/R5 R6/R7 J23 J24 J25
1 (4) R2 - - Y Y Y
2 (3+1) R2 - R7 Y Y N
3 (2+1+1) R2 R5 R7 Y N N
4 (1+1+1+1) R3 R5 R7 N N N
5 (2+2) R2 R5 R6 Y N Y
12
34
56
J16
12
34
56
J17
VOUT_B1
VOUT_B2 VOUT_B2
VOUT_B3
VOUT_B1
VOUT_B3
VOUT_B4 VOUT_B4
240
R20
240
R21
10kR8
VIO_IN
VCCA
PVIN_LDO4 VOUT_LDO4
D3
D4
D5
TP4
TP5 TP14
TP3
150uF
C2
0.002
R25
10k
R28
10k
R33
VOUT_LDO3
PVIN_LDO3
VOUT_LDO3PVIN_LDO3
PVIN_LDO4
2.2uF
C4
VCCA
SDA_I2C1/SDI_SPI
SCL_I2C1/SCK_SPI
0.47uFC9
0.47uFC14
10uF
C36
0.1µF
C35
0.1µF
C39
47µF
C29
1µF
C68
22uF
C18
47µF
C25
VOUT_B2
47µF
C30
22uF
C19
47µF
C26
47µF
C31
22uF
C20
47µF
C27
47µF
C32
22uF
C21
47µF
C28
47µF
C33
22uF
C22
VOUT_B3
VOUT_B4
VOUT_B5
C63
10uF 1µF
C74
C60
10uF
0.1µF
C40
0.1µF
C43
1µF
C71
C65
10uF 1µF
C76
C61
10uF
0.1µF
C41
0.1µF
C44
1µF
C72
C66
10uF 1µF
C77
C59
10uF
0.1µF
C37 0.1µF
C42 1µF
C70
C64
10uF 1µF
C75
C54
10uF
0.1µF
C34 0.1µF
C38 1µF
C67
47µF
C45 47µF C49 C62
10uF 1µF
C73
0.1µF
C23
TPS65941-Q1
VOUT_LDO2
11
OSC32KIN 38
GPIO2
33
SW_B2 15
SW_B5 34
REFGND2 6
PVIN_B2 17
GPIO4
47
VSYS_SENSE
51
VOUT_LDO3
9
INT
14
OVPGDRV
52
VOUT_LDOVRTC
3
PVIN_LDO12
12
REFGND1 5
FB_B3 49
VOUT_LDO4
7
RSTOUT
25
PVIN_B4 54
GND 57
EN_DRV
29
GPIO8
41
SDA_I2C1/SDI_SPI
30
FB_B1 22
VOUT_LDO1
13
OSC32KCAP 40
SCL_I2C1/SCK_SPI
31
PVIN_B1 26
GPIO5
23
GPIO6
24
GPIO7
18
GPIO9
19
SW_B3 43
VIO_IN
48
SW_B3 44
SW_B1 27
VOUT_LDOVINT
2
VCCA
4
PVIN_B3 45
PWRON/ENABLE
20
GPIO10
42
VBACKUP
36
SW_B4 56
PVIN_LDO3
10
SW_B2 16
PVIN_B5 35
FB_B5 37
SW_B4 55
FB_B2 21
AMUXOUT
1
OSC32KOUT 39
GPIO1
32
FB_B4 50
GPIO11
53
SW_B1 28
PVIN_LDO4
8
GPIO3
46
U1
2.2uF
C5
2.2uF
C6
VOUT_LDO4
1
2 3 4 5
J32
1
2 3 4 5
J33
1
2 3 4 5
J35
1
2 3 4 5
J34
GPIO3
GPIO4
GPIO7
GPIO8
GPIO9
GPIO11
GPIO7
nINT
EN_DRV
0R1
0
R2
0
R3
0
R4
0
R5
0
R6
0
R7
0R67
nPWRON
nRSTOUT
1
2 3 4 5
J36
10uF
C47
0
R26
47µF
C46
47µF
C50
47µF
C51 47µF
C56
47µF
C52
47µF
C57
47µF
C48 47µF C53
_S
_S
_S
_S
_S
_S
_S
_S
VBACKUP
For LDOs PSRR, line and load
regulation measurements
12
32.768kHz
Y1
1
2
3
J18
1
2
3
J19
1
2
3
J20
1
2
3
J21
1
2
3
J26
1
2
3
J37
10uF
C58
10uF
C69
10uF
C78
J23 J25 J24
VOUT_B2 VOUT_B3VOUT_B1 VOUT_B4
VOUT_LDOVINT
VOUT_LDOVRTC
VIO_IN
1.2k
R22
1.2k
R23
1.2k
R24
GPIO11
nPWRON
TP9
TP10
TP11
TP12
TP13
SCLK_SPMI
SDATA_SPMI
nERR_SoC
nERR_MCU
GPIO2
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
VOUT_LDOVINT
VOUT_LDOVRTC
VOUT_LDO1
VOUT_LDO2
VOUT_LDO3
VOUT_LDO4
VOUT_B1
VOUT_B2
VOUT_B3
VOUT_B4
VOUT_B5
TP6
TP7
0R35
0
R36
22uF
C1
22uF
C94
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
10kR9
10kR10
10kR11
10kR12
10kR13
10kR14
10kR15
10kR16
10kR17
10kR18
GPIO1
VCCA_S
GPIO3
TP8
GPIO1
GPIO10
0.1µF
C93
3300pF
C102
0.1µF
C99
3300pF
C104
0.1µF
C100
3300pF
C103
3300pF
C101
3300pF
C105
VSYS VCCA VIO_IN
VCCA_S
0
R40
VCCA
0.1µF
C106
D2
5
4
1
2
3
6
7
J13
5
4
1
2
3
6
7
J12
0
R58
0
R65
6pFC16
6pFC17
22uF
C7
SCL_I2C2/CS_SPI
SDA_I2C2/SDO_SPI
5
4
1
2
3
6
7
J14
AMUXOUT
TRIG_WDG
TRIG_WDG
SYNCCLKIN
5
4
1
2
3
6
7
8
9
10
11
J7
5
4
1
2
3
6
7
8
9
10
11
J8
5
4
1
2
3
6
7
8
9
10
11
J9
5
4
1
2
3
6
7
8
9
10
11
J10
5
4
1
2
3
6
7
8
9
10
11
J11
GPIO1
100R32
GPIO1
GPIO2
VIO_IN
nINT
EN_DRV
nPWRON
nRSTOUT
VSYS
SPI_EN
OVPGDRV
VSYS_SENSE
VSYS_SENSE
0
R19
100R51
100R54
0R39
0R83
5
4
1
2
3
6
7
8
9
10
11
J15
6
7
1
U2A
V+
3V- 12
U2E
4
5
2U2B
8
9
14 U2C
10k
R37
10k
R38
VCCA
240
R30
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
GNDSGNDS
GNDS
GNDS
D7 MCUVCC
+VBUS
NT1
USB_3V3
Force Sense
MCUVCC
NT2
NT3
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TPS6594x-Q1 Evaluation Module
6 Schematic, Layout, and Bill of Materials
Figure 10. Schematic Page 1

D+
1D-
2
ID
3
GND
4NC 5
VBUS
6
U5
3300pF
C80
USBD_N
+VBUS
+VBUS
USBD_P
USBD_P
USBD_N
USB_ID
USBD_N
USBD_P
+VBUS
0.1uF
C83
0.1uF
C89
0.1uFC87
0.1uF
C82
0.1uF
C90
1
3 4
2
G
G
25MHz
Y2
12pF
C92
12pF
C95
10k
R47
1.0M
R48
4.87k
R52
1 2
3 4
5 6
7 8
9 10
J31
nRST_MCU
TMS
TCK
TDO
TDI IO1 1
IO2 2
IO3 3
GND
4
IO4
5
IO5
6
IO6
7
VCC 8
TPD6E004RSER
U4
TMS
TCK
TDO
TDI
USB Connector JTAGMCU Reset / OSC
PB0
PB0
GND
A1
SSTXP1
A2 SSTXN1
A3
VBUS
A4
CC1
A5
DP1
A6 DN1
A7
RFU1
A8
VBUS
A9
SSRXN2
A10
SSRXP2
A11
GND
A12 GND B1
SSTXP2 B2
SSTXN2 B3
VBUS B4
CC2 B5
DP2 B6
DN2 B7
RFU2 B8
VBUS B9
SSRXN1 B10
SSRXP1 B11
GND B12
Shield
S1
Shield
S2 Shield S3
Shield S4
J22 12401610E4#2A
USBD_N
USBD_P
SDA1
SCL1
+VBUS
Level shifter
MCUVCC & I/O Power Options
EVMs Stack-up Connection
MCU GPIOs
VCCA
SCLK_SPMI
SDATA_SPMI
1
2
3
4
5
6
7
8
J27
1
2
3
4
5
6
7
8
J28
1
2
3
4
5
6
7
8
J29
MCU Power
SCL1/SCK
MCUVCC
MCUVCC
MCUVCC
VIO_IN
PD0
1
PD1
2
PD2
3
PD3
4
PE3 12
PE2 13
PE1 14
PE0 15
PK0 18
PK1 19
PK2 20
PK3 21
PC7
22 PC6
23 PC5
24 PC4
25
PH0 29
PH1 30
PH2 31
PH3 32
PA0
33
PA1
34
PA2
35
PA3
36
PA4
37
PA5
38
PA6
40
PA7
41
PF0 42
PF1 43
PF2 44
PF3 45
PF4 46
PG0 49
PG1 50
PK7 60
PK6 61
PK5 62
PK4 63
PB2
91
PB3
92
PB0
95
PB1
96
PC3/TDO/SWO
97 PC2/TDI
98 PC1/TMS/SWDIO
99 PC0/TCK/SWCLK
100
PJ0 116
PJ1 117
PB5
120 PB4
121
PE4 123
PE5 124
PD4
125
PD5
126
PD6
127
PD7
128
MSP432E401YTPDTR
U3A
EN0RXIN
53
EN0RXIP
54
EN0TXON
56
EN0TXOP
57
RBIAS 59
WAKE
64 HIB 65
XOSC0 66
XOSC1 67
RST
70
OSC0 88
OSC1 89
MSP432E401YTPDTR
U3C
PQ0 5
PQ1 6
PQ2 11
PQ3 27
PM7
71 PM6
72 PM5
73 PM4
74 PM3
75 PM2
76 PM1
77 PM0
78
PL0
81
PL1
82
PL2
83
PL3
84
PL4
85
PL5
86
PL7
93 PL6
94
PQ4 102
PP2 103
PP3 104
PP4 105
PP5 106
PN0
107
PN1
108
PN2
109
PN3
110
PN4
111
PN5
112
PP0 118
PP1 119
MSP432E401YTPDTR
U3B
VDD
7
VDDA
8
VREFA+
9
GNDA 10
VDD
16
GND 17 VDD
26
VDD
28
VDD
39
VDD
47
GND 48
VDD
51
VDD
52
GND 55
GND 58
VBAT
68
VDD
69
VDD
79
GND 80
VDDC
87
VDD
90
VDD
101
VDD
113
GND 114
VDDC
115
VDD
122
MSP432E401YTPDTR
U3D
4.87k
R43
4.87k
R41
SDA_I2C2/SDO_SPI
SCL_I2C1/SCK_SPI
SDA2
SCL2
SDA1/SDI
SDA2/SDO
SDA_I2C1/SDI_SPI
nPWRON_S
IO1
IO11
nINT3P3
100
R45
1.0M
R68
1.0M
R69
1.0M
R60
2.2uF
C85
2.2uF
C86
2.2uF
C88
1.0kR61
1.2kR50
SCL_I2C1/SCK_SPI
2.2uF
C91
VCC3P3
2.2uF
C97
2.2uF
C96
2.2uF
C81
VIO_IN
MCUVCC
IO1
200k
R53
1.0MR55
374k
R38
0.1uF
C98
GND 1
SREF
2
S1
3
S2
4
S3
5
S4
6
S5
7
S6
8
S7
9
S8
10 D8 11
D7 12
D6 13
D5 14
D4 15
D3 16
D2 17
D1 18
DREF 19
GREF 20
SN74GTL2003PWR
U9
GND 1
SREF
2
S1
3
S2
4
S3
5
S4
6
S5
7
S6
8
S7
9
S8
10 D8 11
D7 12
D6 13
D5 14
D4 15
D3 16
D2 17
D1 18
DREF 19
GREF 20
SN74GTL2003PWR
U8
SPI_MISO
SPI_MOSI
SPI_CLK
IO2
IO3
IO4
IO5
IO6
IO7
IO8
IO9
IO10
IO11
IO2
IO3
IO4
IO5
IO6
IO7
IO8
IO9
IO10
SPI_MOSI
SPI_CLK
SCL1/SCK
SDA1/SDISDA1
SCL1
SDA2
SCL2
SCL2/CSSCL_I2C2/CS_SPI
SDA_I2C2/SDO_SPI
SCL_I2C2/CS_SPI
SCL2/CS
SPI_MISO
SDA2/SDO
TRIG_WDG
nERR_MCU
nERR_SoC
VDDC1P2
I2C PU / SPI Selection
MCUVCC
SDA_I2C2/SDO_SPI
SCL_I2C1/SCK_SPI
SDA_I2C1/SDI_SPI
SCL_I2C2/CS_SPI
SDA_I2C1/SDI_SPI
0
R37
SEL
15
1B1
16
1B2
11A 2
4B2
11 4A 10
2B1
3
2B2
4
3B2
83B1
9
2A 5
GND 6
VCC
14
OE
13
3A 7
4B1
12
SN74CBTLV3257RSVRU12
MCUVCC
10k
R46
MCUVCC
1µF
C84
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
nINT3P3nINT
1A 1
1B 2
2B 3
2A 4
2C
5
3C
6
GND 7
3A 8
3B 9
4B 10
4A 11
4C
12
1C
13
VCC
14
SN74HC4066PW
U11
1.0kR62
1.0kR63
1.0kR64
+VBUS
10k
R57
PUEN
PUEN
SPI_CS
MCUVCC
10k
R70
MCUVCC
MCUVCC
10k
R71
10k
R72
10k
R73
10k
R74
10k
R75
10k
R76
10k
R77
10k
R78
10k
R79
10k
R80
10k
R81
10k
R82
10k
R49
10k
R42
10k
R44
SPI_CS
I2C_SPI_SEL
0.1uF
C107
0.47uF
C108
EN1
1
IN
2
EN2
3GND 4
OUT2 5
OUT1 6
TLV7103318QDSERQ1
U6
VCCA
1
2
3
J38
VCC3P3
1.0M
R83 VIO1P8
I2C_SPI_SEL
2.2uF
C109
1.0M
R84
1.0M
R85
1.0M
R87
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TPS6594x-Q1 Evaluation Module
Figure 11. Schematic Page 2

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TPS6594x-Q1 Evaluation Module
Figure 12. Layout Top, Layer 1

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TPS6594x-Q1 Evaluation Module
Figure 13. Layout Ground, Layer 2

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TPS6594x-Q1 Evaluation Module
Figure 14. Layout Signal, Layer 3