Texas Instruments TSW3000 User manual

TSW3000 Demo Kit
User's Guide
September 2005
SLWU013A

TSW3000 Demo Kit
User's Guide
Literature Number: SLWU013AMarch 2004 – Revised September 2005

Contents
1 Demo Kit Configuration Options ................................................................................... 71.1 DAC Component .................................................................................................... 71.2 VComm Configuration .............................................................................................. 71.3 VCXO ................................................................................................................. 71.4 VCO .................................................................................................................. 72 Block Diagrams .......................................................................................................... 82.1 System Block Diagram ............................................................................................. 82.2 Demo Kit Block Diagram ........................................................................................... 83 Key Texas Instruments Components ............................................................................. 93.1 CDCM7005 .......................................................................................................... 93.2 DAC5687 ............................................................................................................. 93.3 TRF370x ............................................................................................................. 93.4 TRF3750 ............................................................................................................. 94 Software Installation .................................................................................................... 95 Software Operation ..................................................................................................... 95.1 CDCM7005 Software ............................................................................................. 105.2 TRF3750 Software ................................................................................................ 125.3 DAC5687 Software ................................................................................................ 135.4 DAC5687 GUI Register Descriptions ........................................................................... 146 Board Setup .............................................................................................................. 166.1 Jumper Settings ................................................................................................... 166.2 Input/Output Connectors ......................................................................................... 176.3 Parallel Port ........................................................................................................ 176.4 DC Power Requirements ......................................................................................... 177 Demo Kit Test Configuration ....................................................................................... 177.1 Test Setup Block Diagram ....................................................................................... 187.2 Test Equipment .................................................................................................... 187.3 Calibration .......................................................................................................... 187.4 Test Specifications ................................................................................................ 188 Basic Test Procedure ................................................................................................. 198.1 Initial Inspection ................................................................................................... 198.2 Engage Power Supplies .......................................................................................... 198.3 Program the CDCM7005 ......................................................................................... 198.4 Program the TRF3750 ............................................................................................ 198.5 DAC5687 Program ................................................................................................ 208.6 Carrier Suppression ............................................................................................... 218.7 Sideband Rejection ............................................................................................... 229 Optional Configurations ............................................................................................. 249.1 External LO ........................................................................................................ 249.2 External Reference ................................................................................................ 249.3 Monitor DAC Output .............................................................................................. 24
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10 Filter Specifications ................................................................................................... 2510.1 Baseband Filter .................................................................................................... 2511 Layers and Schematics .............................................................................................. 2511.1 Layers ............................................................................................................... 2611.2 Schematics ......................................................................................................... 35
Contents 4 SLWU013A – March 2004 – Revised September 2005

List of Figures
1 System Block Diagram ...................................................................................................... 82 Demo Kit Block Diagram .................................................................................................... 83 TSW3000 Startup Screen ................................................................................................. 104 Default CDCM7005 SPI GUI .............................................................................................. 115 TRF3750 GUI - Main Menu ............................................................................................... 126 TRF3750 GUI - Advanced Menu ......................................................................................... 137 DAC5687 GUI .............................................................................................................. 148 Test System Block Diagram .............................................................................................. 189 Default DAC GUI With f
DAC
/8 Tone From NCO ........................................................................ 2110 Single Sideband Spectrum Output Before DAC Offset and QMC Adjustments ................................... 2211 DAC GUI With Typical Settings To Minimize LO and Sideband ..................................................... 2312 Sideband and LO ........................................................................................................... 2413 Top Layer .................................................................................................................... 2614 Top Layer (NH) ............................................................................................................. 2715 Layer 2 ....................................................................................................................... 2816 Layer 3 ....................................................................................................................... 2917 Layer 4 ....................................................................................................................... 3018 Layer 4 (NH) ................................................................................................................ 3119 Layer 5 ....................................................................................................................... 3220 Bottom Layer ................................................................................................................ 3321 Bottom Silkscreen .......................................................................................................... 3422 Drill Drawing ................................................................................................................ 35
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List of Tables
1 Frequency Bands ............................................................................................................ 72 CDCM7005 Register Values .............................................................................................. 113 Jumper List .................................................................................................................. 164 Input/Output Connections ................................................................................................. 175 Demo Kit Specifications ................................................................................................... 186 Frequency Designations ................................................................................................... 19
List of Tables6 SLWU013A – March 2004 – Revised September 2005

1 Demo Kit Configuration Options
1.1 DAC Component
1.2 VComm Configuration
1.3 VCXO
1.4 VCO
User's GuideSLWU013A – March 2004 – Revised September 2005
The TSW3000 Demo Kit can be configured in different ways to evaluate different components in differentfrequency bands. This section outlines the various component configurations. Based on the configuration,testing and board setup must be altered to accommodate the given components and features.
The TSW3000 Demo Kit is built for the DAC5687, although this Demo Kit can also support the DAC5686since the two devices are pin compatible. The procedures outlined in this document are primarily suited forthe DAC5687, but can be modified easily for the DAC5686 if desired.
The analog quadrature modulator requires a common-mode dc voltage of approximately 3.7 V. In order toutilize the dc-offset adjustment capabilities of the DAC568x for carrier suppression, it is imperative tomaintain a dc path from the DAC output to the modulator input. The common-mode voltage for themodulator is maitained with a passive resistor network that is designed to provide the proper operationpoint for the DAC568x and the TRF370x modulator. By design, in order to preserve the proper dc levels,the DAC gain should be kept at maximum (15), though deviation by a few steps is generally acceptablewith no degradation in performance.
The CDCM7005 requires a VCXO source to derive its output clock signals. The VCXO is at referencedesignator U10 on the back side of the board. The frequency of the VCXO can be changed to operate theDemo Kit with different clocking schemes for different modulation standards or for specific customerrequirements. Denote which VCXO frequency is on the board so that the CDCM7005 part can be set upproperly. The following conventions are typically used:•WCDMA: Derivatives of 61.44 MHz (i.e., 122.88 MHz, 245.76 MHz, 491.52 MHz)•GSM: Derivatives of 52 MHz (i.e., 104 MHz, 208 MHz)•CDMA2K: Derivativies of 78.6432 (i.e., 157.2864 MHz, 314.5728 MHz)
The VCO outputs the RF signal used for the LO drive on the analog quadrature modulator. The RF outputfrequency is contingent on the LO frequency value.
The RF frequency band of the VCO must be noted in order to know how to program the TRF3750 andwhere to measure the output RF signal from the modulator. The typical bands of operation are shown inTable 1 .
Table 1. Frequency Bands
UMTS PCS GSM900 DCS1800
FREQUENCY 2110-2170 MHz 1930-1990 MHz 935-960 MHz 1805-1880 MHz
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2 Block Diagrams
2.1 System Block Diagram
DAC
I/Q
Modulator
90°
0°
LPA TX
Diplexer
ANT
RX
LNA
A/D I/Q
Demod
2.2 Demo Kit Block Diagram
16
DAC5687
16
CLK1
I
Q
TRF370x
I/Q
Modulator RF
LO
VCO
TRF3750
VCXO
PLL
Ref Osc
CDCM7005
CLK2
Block Diagrams
The basic radio system block diagram in Figure 1 demonstrates where the TSW3000 Demo Kit fits in theoverall transceiver. The dash-line box illustrates the components found on the TSW3000 Demo Kit board.
Figure 1. System Block Diagram
The basic Demo Kit block diagram is shown in Figure 2 . The shaded boxes illustrate the key TexasInstruments components found on the TSW3000 Demo Kit board.
Figure 2. Demo Kit Block Diagram
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3 Key Texas Instruments Components
3.1 CDCM7005
3.2 DAC5687
3.3 TRF370x
3.4 TRF3750
4 Software Installation
5 Software Operation
Key Texas Instruments Components
The CDCM7005 clock distribution chip is used to generate and synchronize the clock outputs to thesystem. The device has five outputs which can be either LVPECL or LVCMOS and can be divided downby 1, 2, 3, 4, 6, 8, and 16. The divide by 16 can be replaced with a divide by 4 or 8 with a 90 degreephase shift.
The DAC5687 is a 16-bit interpolating dual digital-to-analog converter (DAC). The device incorporates adigital modulator, independent differential offset control, and I/Q amplitude control. The device is typicallyused in baseband mode or in low IF mode in conjunction with an analog quadrature modulator.
The TRF370x is a direct upconvert I/Q modulator. The device accepts differential input voltage atbaseband or low IF frequencies and outputs an RF signal based on the LO drive frequency.
The TRF3750 is a PLL chip used in the synthesizer section to generate the LO frequency required for theI/Q modulator.
This section summarizes the installation procedures for the software required to operate the Demo Kit.Once all of the software is loaded, it is recommended to reboot the computer.•Extract TSW3000-Installv2p0.zip
•Execute setup.exe
The following describes the use of the software required to set the TSW3000 Demo Kit in the baselineconfiguration for the CDCM7005, TRF3750, and DAC5687. The software should be configured in theorder presented below. The first step requires starting the TSW3000 software. This opens a window asshown in Figure 3 . The tabs on the left side of the window allow selection of different GUI controllers forthe DAC5687, TRF3750, and CDCM7005. The lower left portion of the screen contains links to this user'sguide as well as the data sheets for the DAC5687, TRF3750, and the CDCM7005.
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5.1 CDCM7005 Software
Software Operation
Figure 3. TSW3000 Startup Screen
By using the provided CDCM7005 serial peripheral interface (SPI) software, the user can load settings tothe CDCM7005 internal registers. This must be performed every time the TSW3000 Demo Kit is poweredup, since the CDCM7005 has default settings that are loaded at power up and the settings may be slightlydifferent than the ones required to operate the Demo Kit. Executing the program brings up the interfaceseen in Figure 4 . The default settings are correct for a VCXO of 491.52 MHz and a 10 MHz reference ason the TSW3000. The CDCM7005 GUI allows register settings to be saved and can be loaded back inafterwards. This can be accomplished with the Save and Load Settings buttons near the right side of theGUI.
It is recommended that any unused output clocks be tri-stated. In this case the TSW3000 only usesOUT_MUX_1 to drive the DAC5687. OUT_MUX_0, OUT_MUX_2, OUT_MUX_3, OUT_MUX_4 should betri-stated unless there is a need to use the other output clocks.
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Software Operation
Figure 4. Default CDCM7005 SPI GUI
The divider parameters, M and N, are determined according to the following equation based on theinternal reference frequency and internal VCXO frequency.
F
REF
= (F
VCXO
×M)/(N ×P)
The p parameter is the VCXO input divider and set through the FB_MUX value. The M and N countervalues need to be adjusted depending on the board configuration. The M and N counter registers aredetermined by the reference frequency and the VCXO frequency. The OUT_MUX sets the divide ratios forthe individual output clocks. The OUTSEL determines whether the output clocks will be used assingle-ended CMOS or differential LVPECL. With a 10-MHz reference oscillator the CDCM7005 settingsare shown in Table 2 for a variety of common VCXO frequencies. For other frequencies, see to theCDCM7005 data sheet for more details.
Table 2. CDCM7005 Register Values
VCXO Freq. (MHz) 491.52 245.76 122.88 61.44
Divider M 125 125 125 125Divider N 768 768 768 768FB_MUX 8 4 2 1
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5.2 TRF3750 Software
Software Operation
The TRF3750 software is used to program the PLL chip to lock the VCO oto a desired frequency output.The main menu of the program is shown in Figure 5 .
Figure 5. TRF3750 GUI - Main Menu
The options in the front panel allow the user to program the desired frequency of the VCO, the desiredfrequency of the PFD, the reference frequency, and the prescaler selection. The software then displaysthe actual VCO frequency, PFD frequency and the R, N, A, and B counter values to be programmed intothe TRF3750. Hitting the Send button writes these values to the TRF3750. In default mode on a defaultboard, only the desired VCO frequency (2100 MHz to 2200 MHz) needs to be changed. For other VCOranges, other parameters may need to be changed.
The Advanced Operation button will bring up another user interface as shown in Figure 6 .
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5.3 DAC5687 Software
Software Operation
Figure 6. TRF3750 GUI - Advanced Menu
This menu allows control of more register settings. For details on these settings, see the TRF3750 datasheet (SLWS146 ). The register of interest in this menu is the MUXOUT CONTROL which can be used todetermine the function of LED D4. This mode defaults to Digital PLL Lock Detect and causes the LED D4to light up when the PLL successfully locks. Normally, these menu settings do not need to be changed.
By using the provided software, the user can write and read control register information to the DAC5687.At first startup of this software, it is imperative to select the Pll Port Config button to bring up the parallelport configuration settings. From the menu, select the TSW3000 setting. This configures the port to becompatible with the TSW3000. Once the Demo Kit is powered on with the parallel port configured andconnected properly, then the GUI shown in Figure 7 is displayed with the default settings read from thedevice. If there is a problem with the communication, such as the Demo Kit is not powered on or theparallel port cable is not connected, an error message will be displayed instructing the user to correct theproblem. Once corrected, hit the Read All button to read the default settings of the device.
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5.4 DAC5687 GUI Register Descriptions
Software Operation
Figure 7. DAC5687 GUI
For normal operation, the user needs only to select values and switches as desired. The values areautomatically sent to the device and read back to verify their configuration.
5.4.1 Register Controls•Load Regs– Loads register values from a saved file to the DAC5687 and updates the GUI.•Save Regs– Saves current GUI registers settings to a text file for future use.•Read All– Reads the current registers of the DAC5687. This is used to verify settings on the frontpanel.
•Send All– Sends the current front panel registers to the device. This is generally only used when theDemo Kit power has recycled or the device has been reset and the user wants to load the displayedsettings to the device.
5.4.2 Configuration Controls•Full Bypass– When set, all filtering, QMC, and NCO functions are bypassed.•FIR Bypass– Bypass all interpolation filters. QMC INCO functional. Limited to FDAC = 250 MHz•FIFO Bypass– When set to bypass, the internal four sample FIFO is disabled. When cleared, the FIFOis enabled.
•FIR A– A side first FIR filter in high-pass mode when set, low-pass mode when cleared.
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Software Operation
•FIR B– B side first FIR filter in high-pass mode when set, low-pass mode when cleared.•Dual Clk– Only used when the PLL is disabled. When set, two differential clocks are used to input thedata to the chip; CLK1/CLK1C is used to latch the input data into the chip, and CLK2/CLK2C is usedas the DAC sample clock.•Interleave– When set, interleaved input data mode is enabled; both A and B data streams are input atthe DA(15:0) input pins.•Inverse Sinc– Enables inverse sinc filter.•Half Rate Input– Enables half rate input mode. Input data for the DAC A data path is input to the chipat half speed using both the DA(15:0) and DB(15:0) input pins.•Sif– Sets sif_4-pin bit. A 4-pin serial interface mode is enabled when on, 3-pin mode when off. TheDAC5687 Demo Kit is configured for a 3-pin serial interface, so setting to a 4-bit serial interface makesreading registers impossible with the GUI.•Inv. PLL Lock– Only used when PLL is disabled and dual clock mode is disabled. When cleared, inputdata is latched into the chip on rising edges of the PLLLOCK output pin. When set, input data islatched into the chip on falling edges of the PLLLOCK output pin.•PLL Freq– Sets PLL VCO center frequency to low or high center frequency.•PLL Kv– Sets PLL VCO gain to either high or low gain.•Qflag– Sets qflag bit. When set, the QFLAG input pin operates as a B sample indicator wheninterleaved data is enabled. When cleared, the TXENABLE rising determines the A/B timingrelationship.
•2's Comp– When set, input data is interpreted as 2's complement. When cleared, input data isinterpreted as offset binary.•Rev A Bus– When cleared, DA input data MSB to LSB order is DA(15) = MSB and DA(0) = LSB.When set, DA input data MSB to LSB order is reversed, DA(15) = LSB and DA(0) = MSB.•Rev B Bus– When cleared, DB input data MSB to LSB order is DB(15) = MSB and DB(0) = LSB.When set, DB input data MSB to LSB order is reversed, DB(15) = LSB and DB(0) = MSB.•USB– When set, the data to DACB is inverted to generate upper side band output.•Inv. Clk I(Q)– Inverts the DAC core sample clock when set, normal when cleared.•Sync_Phstr– When set, the internal clock divider logic is initialized with a PHSTR pin low to hightransition.
•Sync_cm– When set, the coarse mixer is synchronized with a PHSTR low-to-high transition.•Sync_NCO– When set, the NCO phase accumulator is cleared with a phstr low-to-high transition.•Phstr Clk Div Select– Selects the clock used to latch the PHSTR input when restarting the internalclock dividers. When set, the full rate CLK2 signal latches PHSTR and when cleared, the divided downinput clock signal latches PHSTR.•DAC Serial Data– When set, both DAC A and DAC B input data is replaced with fixed data loaded intothe 16-bit serial interface DAC Static Data.–Counter Mode– Controls the internal counter that can be used as the DAC data source: {off; all16b; 7b LSBs; 5b MIDs; 5b MSBs}.–DAC Static Data– When DAC Serial Data is set, both DAC A and DAC B input data is replacedwith fixed data loaded with this value. Range = 0 - 65535.•Alt. PLLLOCK Output– Can be used to determine alternate outputs on the PLLLOCK pin when usingthe internal PLL mode. The EXTLO pin must be open when using this mode.•NCO– When set, enables NCO.–NCO Gain– Sets NCO gain resulting in a 2x increase in NCO output amplitude. Except for F
s
/2 andF
s
/4 mixing NCO frequencies, this selection can result in saturation for full-scale inputs. Considerusing QMC gain for lower gains.•QMC– When set, enables the QMC.–QMCA Gain– Sets QMC gain A to a range = 0 to 2047. See the data sheet for more information.–QMC B Gain– Sets QMC gain B to a range = 0 to 2047. See the data sheet for more information.–QMC Phase– Sets QMC phase to a range = -512 to 511. See the data sheet for more information.Used to adjust for I/Q phase imbalance.•Mode– Used to select the coarse mixer mode. See the DAC5687 data sheet for more information.
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6 Board Setup
6.1 Jumper Settings
Board Setup
•PLL Divider– Sets VCO divider to div by 1, 2, 4, or 8.•Interpolation – Sets FIR Interpolation factor: {X2, X4, X4L, X8}. X4 uses lower power than 4xL, butF
dac
= 320 MHz max when NCO or QMC are used.•Phstr Init. Phase – Adjusts the initial phase of the fs/2 and fs/4 cmix block at PHSTR.•Sync FIFO– Sync source selection mode for the FIFO. When a low to high transition is detected onthe selected sync source, the FIFO input and output pointers are initialized. See the DAC5687 datasheet for source description.
5.4.3 DAC A(B) Gain•DAC Coarse Gain– Sets coarse gain of DAC A(B) full-scale current. Range is 0 to 15. See theDAC5687 data sheet for full-scale gain equation.•DAC Fine Gain– Sets fine gain of DAC A(B) full scale current. Range is -128 to127. See the DAC5687data sheet for full-scale gain equation. Used to adjust for I/Q amplitude imbalance.•DAC DCOffset– Sets DAC A(B) dc-offset register. Range is -4096 to 4095. Used to adjust for carriersuppression.
•Sleep– DAC A(B) sleeps when set, operational when cleared.
5.4.4 NCO
•NCO DDS– Sets NCO DDS registers. See the DAC5687 data sheet for formula.•NCO Phase– Sets initial NCO phase registers. See the DAC5687 data sheet for more information.•F
DAC
(MHz), NCO IF (MHz)– Used to calculate the required NCO DDS value.
5.4.5 Additional Control/Monitor Registers•Version– Displays the version of the silicon. If a version of 0 is read then the communication is notfunctioning and an error message will be displayed.
The TSW3000 Demo Kit has on-board jumpers that allow the user to selectively disengage devices asdesired. The unit is shipped with jumpers in place that activate all of the devices on board. Table 3explains the functionality of the jumpers on the board.
Table 3. Jumper List
JUMPER LABEL FUNCTION CONDITION DEFAULT
W1 PLL Lock 2-pin access port for monitoring PLL lock of the Open InstalledDAC5687W2 PWD Power down for the TRF370x Powered Pin 1, 2W6 LO Buffer Disengages power to LO buffer amp Powered InstalledW5 IOVDD Toggles 3.3 V or 1.8 V to IOVDD on the DAC5687 3.3 V Engaged Pin 1, 2J15 pin 2 PLLVDD Toggles power to the DAC PLL Not Powered Pin 1, 2J15 pin 5 SLEEP Power down for the DAC5687 Open RemovedJ15 pin 8 EXTLO Toggles internal reference ground Grounded Pin 7, 8J15 pin 11 TXENABLE Selects interleaved data Powered Pin 11, 12J15 pin 14 TESTMODE DO NOT POPULATE! Open RemovedJ15 pin 17 QFLAG Used to flag the DAC5687 channel B data in Open Removedinterleave modeJ15 pin 20 CDC_PD Power down of the CDCM7005 Open RemovedJ15 pin 23 REF_SEL Selecets reference for CDCM7005 Open Removed
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6.2 Input/Output Connectors
6.3 Parallel Port
6.4 DC Power Requirements
7 Demo Kit Test Configuration
Demo Kit Test Configuration
Table 3. Jumper List (continued)
JUMPER LABEL FUNCTION CONDITION DEFAULT
J15 pin 27 PLL_PWD Power down the TRF3750 Powered Pin 26, 27J15 pin 29 RESET Resets the DAC5687 when low Open Removed
The input and output connections are shown in Table 4 .
Table 4. Input/Output Connections
REFERENCE DESIGNATOR CONNECTOR TYPE DESCRIPTION
J13 34-pin header I channel data inputJ14 34-pin header Q channel data inputJ9 SMA RF outputJ10 SMA Optional LO inputJ8 SMA Optional external referenceJ2 SMA Output clock 1 from CDCM7005J3 SMA Output clock 2 from CDCM7005J5 SMA Optional I out A from DAC5687J19 SMA Optional Q out B from DAC5687J6 SMA Input for external VCXO for CDCM7005J7 SMA PLL lock status on DAC5687J4 SMA Phase synchronization on DAC5687
RF shield covers should be in place over the synthesizer section and the RF modulator section. Theseshields provide isolation of the RF sections on the board.
The TSW3000 Demo Kit contains a 25-pin parallel port connector (J1) to interface to a standard computerparallel port. Programming of the CDCM7005, DAC5687, and TRF3750 are accomplished through thisport.
The Demo Kit requires a single dc-voltage supply that is nominally 6 V. From that supply, the 5 V, 3.3 V,and 1.8 V required for the devices on the board are generated internally through linear voltage regulators.It is possible to use a higher input voltage; however, care should be taken not to over dissipate theon-board voltage regulators.
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7.1 Test Setup Block Diagram
TSW3000
EVM DUT
J7
Clock
Power
Supply GND
+6 V
16
25
J9
Pattern
Generator 16
J17 J11
PC Controller
J14
J13
J1
Spectrum
Analyzer
7.2 Test Equipment
7.3 Calibration
7.4 Test Specifications
Demo Kit Test Configuration
The test set up for general testing of the TSW3000 Demo Kit is shown in Figure 8 .
Figure 8. Test System Block Diagram
The following is a list of the test equipment required for testing the TSW3000 Demo Kit. Equivalent modelsmay be used for certain applications, but may produce different results due to limitations within theinstrument.
•Dual Power Supply: Any with current readout capability•Spectrum Analyzer: Rhode & Schwartz FSU, Agilent PSA, or equivalentThis particular piece can measure >70-dBc ACPR with the noise cancellation option active. Thisamount of dynamic range is required to accurately measure the ACPR of the Demo Kit. Anotherspectrum analyzer can be substituted if it achieves as good or better dynamic range.•Pattern Generator: Agilent 16702B•Oscilloscope: Tektronix 650 or equivalentUsed to probe clock output signals and for debugging.•Digital Voltmeter: Agilent 34401A or equivalent
In order to record proper output power the insertion loss of the output cable must calibrated. Measure theinsertion loss of the cable from J9 to the spectrum analyzer; set the analyzer's reference level offset tothat value.
The test specifications are outlined in Table 5 .
Table 5. Demo Kit Specifications
MIN MAX UNITS
CURRENT
+6 V 1.5 A
CW TESTS
Carrier suppression 30 dBc
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8 Basic Test Procedure
8.1 Initial Inspection
8.2 Engage Power Supplies
8.3 Program the CDCM7005
8.4 Program the TRF3750
Basic Test Procedure
Table 5. Demo Kit Specifications (continued)
MIN MAX UNITS
Sideband rejection 25 dBc
Spurious Output
2nd harmonic 45 dBcAliased LSB (pos) 40 dBcOutput clock 40 dBcAliased USB 15 dBcAliased USB (neg) 8 dBc
WCDMA ACPR
Channel power -14 dBmACPR -Low 70 dBcACPR -High 70 dBc
This section outlines the basic test procedure to get the Demo Kit operational. Disconnect the cables atJ13 and J14 that connect to the pattern generator. Connect the power supply cable and the RF output tothe spectrum analyzer.
Inspect the board to determine which devices were used.•Note the VCXO frequency (U10) that is on the board•Note the VCO frequency band (Y3) that is on the board
Engage 6-V power supply•Verify the current reading is between 0.8 A to 1.3 A when configured with the DAC5687
Use the Default Settings on the CDCM7005 GUI (See Section 5.1 ). This generates a 491.52-MHz clock.•Set the OUT_MUX_0, 2, 3, 4 to tristate. Only OUT_MUX_1 is used for clocking the DAC5687•Hit the GUI Send button•Verify that LEDs D1, D2, and D3 are illuminated
Use the Default Settings in the TRF3750 GUI (See Section 5.2 ). This places a carrier at 2.14 GHz•Hit the GUI send button.•Verify the LED D4 is illuminated. This indicates lock of the VCXO and TCXO reference.•Monitor RF output from the spectrum analyzer•Verify a single frequency tone at the default 2.14 GHz.
Table 6. Frequency Designations
VCO BAND UMTS GSM900 PCS DCS1800
Midband (MHz) 2140 950 1960 1850Low (MHz) 2110 935 1930 1805
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8.5 DAC5687 Program
Basic Test Procedure
Table 6. Frequency Designations (continued)
VCO BAND UMTS GSM900 PCS DCS1800
High (MHz) 2170 960 1990 1880
•Disable the PLL by removing the jumper at J15, pins 2 and 3, if not already removed.•Verify DACA and DACB Coarse Gain is set to 15•Set Mode to 0000 (No Coarse Mixing)•Ensure DAC Offsets and DAC fine gain for both A and B are set to 0•Set the spectrum analyzer as follows:– Center Freq: 2.14 GHz– RBW: 30 kHz, VBW: 300 kHz– Span: 491.52 MHz– Attn: 5 dB– Ref Level: 10 dBm
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