Texas Instruments TMS320C6722 User manual

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1 TMS320C6727, TMS320C6726, TMS320C6722 DSPs
1.1 Features
TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
•C672x: 32-/64-Bit 300-MHz Floating-Point DSPs •Three Multichannel Audio Serial Ports– Transmit/Receive Clocks up to 50 MHz•Upgrades to C67x+ CPU From C67x™ DSP
– Six Clock Zones and 16 Serial Data PinsGeneration:
– Supports TDM, I2S, and Similar Formats– 2X CPU Registers [64 General-Purpose]
– DIT-Capable (McASP2)– New Audio-Specific Instructions– Compatible With the C67x CPU
•Universal Host-Port Interface (UHPI)– 32-Bit-Wide Data Bus for High Bandwidth•Enhanced Memory System
– Muxed and Non-Muxed Address and Data– 256K-Byte Unified Program/Data RAM– 384K-Byte Unified Program/Data ROM
•Two 10-MHz SPI Ports With 3-, 4-, and 5-Pin– Single-Cycle Data Access From CPU Options– Large Program Cache (32K Byte) Supports
•Two Inter-Integrated Circuit (I2C) PortsRAM, ROM, and External Memory
•Real-Time Interrupt Counter/Watchdog•External Memory Interface (EMIF) Supports
•Oscillator- and Software-Controlled PLL– 100-MHz SDRAM (16- or 32-Bit)
•Applications:– Asynchronous NOR Flash, SRAM (8-,16-, or
– Professional Audio32-Bit)
•Mixers– NAND Flash (8- or 16-Bit)
•Effects Boxes•Enhanced I/O System
•Audio Synthesis– High-Performance Crossbar Switch
•Instrument/Amp Modeling– Dedicated McASP DMA Bus
•Audio Conferencing– Deterministic I/O Performance
•Audio Broadcast•dMAX (Dual Data Movement Accelerator)
•Audio EncoderSupports:
– Emerging Audio Applications– 16 Independent Channels
– Biometrics– Concurrent Processing of Two Transfer
– MedicalRequests
– Industrial– 1-, 2-, and 3-Dimensional
•Commercial or Extended TemperatureMemory-to-Memory andMemory-to-Peripheral Data Transfers
•144-Pin, 0.5-mm, PowerPAD™ Thin Quad– Circular Addressing Where the Size of a Flatpack (TQFP) [RFP Suffix]Circular Buffer (FIFO) is not Limited to 2
n
•256-Terminal, 1.0-mm, 16x16 Array Plastic Ball– Table-Based Multi-Tap Delay Read and
Grid Array (PBGA) [GDH and ZDH Suffixes]Write Transfers From/To a Circular Buffer
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this document.C67x, PowerPAD, TMS320C6000, C6000, DSP/BIOS, XDS, TMS320 are trademarks of Texas Instruments.Philips is a registered trademark of Koninklijki Philips Electronics N.V.All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

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1.2 Description
TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
The TMS320C672x is the next generation of Texas Instruments' C67x generation of high-performance32-/64-bit floating-point digital signal processors. The TMS320C672x includes the TMS320C6727,TMS320C6726, and TMS320C6722 devices.
(1)
Enhanced C67x+ CPU. The C67x+ CPU is an enhanced version of the C67x CPU used on the C671xDSPs. It is compatible with the C67x CPU but offers significant improvements in speed, code density, andfloating-point performance per clock cycle. At 300 MHz, the CPU is capable of a maximum performance of2400 MIPS/1800 MFLOPS by executing up to eight instructions (six of which are floating-pointinstructions) in parallel each cycle. The CPU natively supports 32-bit fixed-point, 32-bit single-precisionfloating-point, and 64-bit double-precision floating-point arithmetic.
Efficient Memory System. The memory controller maps the large on-chip 256K-byte RAM and 384K-byteROM as unified program/data memory. Development is simplified since there is no fixed division betweenprogram and data memory size as on some other devices.
The memory controller supports single-cycle data accesses from the C67x+ CPU to the RAM and ROM.Up to three parallel accesses to the internal RAM and ROM from three of the following four sources aresupported:
•Two 64-bit data accesses from the C67x+ CPU•One 256-bit program fetch from the core and program cache•One 32-bit data access from the peripheral system (either dMAX or UHPI)
The large (32K-byte) program cache translates to a high hit rate for most applications. This prevents mostprogram/data access conflicts to the on-chip memory. It also enables effective program execution from anoff-chip memory such as an SDRAM.
High-Performance Crossbar Switch. A high-performance crossbar switch acts as a central hub betweenthe different bus masters (CPU, dMAX, UHPI) and different targets (peripherals and memory). Thecrossbar is partially connected; some connections are not supported (for example, UHPI-to-peripheralconnections).
Multiple transfers occur in parallel through the crossbar as long as there is no conflict between busmasters for a particular target. When a conflict does occur, the arbitration is a simple and deterministicfixed-priority scheme.
The dMAX is given highest-priority since it is responsible for the most time-critical I/O transfers, followednext by the UHPI, and finally by the CPU.
dMAX Dual Data Movement Accelerator. The dMAX is a module designed to perform Data MovementAcceleration. The Data Movement Accelerator (dMAX) controller handles user-programmed data transfersbetween the internal data memory controller and the device peripherals on the C672x DSPs. The dMAXallows movement of data to/from any addressable memory space including internal memory, peripherals,and external memory.
The dMAX controller includes features such as the capability to perform three-dimensional data transfersfor advanced data sorting, and the capability to manage a section of the memory as a circular buffer/FIFOwith delay-tap based reading and writing of data. The dMAX controller is capable of concurrentlyprocessing two transfer requests (provided that they are to/from different source/destinations).
External Memory Interface (EMIF) for Flexibility and Expansion. The external memory interface on theC672x supports a single bank of SDRAM and a single bank of asynchronous memory. The EMIF datawidth is 16 bits wide on the C6726 and C6722, and 32 bits wide on the C6727.
SDRAM support includes x16 and x32 SDRAM devices with 1, 2, or 4 banks.
The C6726 and C6722 support SDRAM devices up to 128M bits.
(1) Throughout the remainder of the document, TMS320C6727 (or C6727), TMS320C6726 (or C6726), and/or TMS320C6722 (or C6722)will be referred to as TMS320C672x (or C672x).
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TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
The C6727 extends SDRAM support to 256M-bit and 512M-bit devices.
Asynchronous memory support is typically used to boot from a parallel non-multiplexed NOR flash devicethat can be 8, 16, or 32 bits wide. Booting from larger flash devices than are natively supported by thededicated EMIF address lines is accomplished by using general-purpose I/O pins for upper address lines.
The asynchronous memory interface can also be configured to support 8- or 16-bit-wide NAND flash. Itincludes a hardware ECC calculation (for single-bit errors) that can operate on blocks of data up to512 bytes.
Universal Host-Port Interface (UHPI) for High-Speed Parallel I/O. The Universal Host-Port Interface(UHPI) is a parallel interface through which an external host CPU can access memories on the DSP.Three modes are supported by the C672x UHPI:•Multiplexed Address/Data - Half-Word (16-bit-wide) Mode (similar to C6713)•Multiplexed Address/Data - Full Word (32-bit-wide) Mode•Non-Multiplexed Mode - 16-bit Address and 32-bit Data Bus
The UHPI can also be restricted to accessing a single page (64K bytes) of memory anywhere in theaddress space of the C672x; this page can be changed, but only by the C672x CPU. This feature allowsthe UHPI to be used for high-speed data transfers even in systems where security is an importantrequirement.
The UHPI is only available on the C6727.
Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2) - Up to 16 Stereo Channels I2S.The multichannel audio serial port (McASP) seamlessly interfaces to CODECs, DACs, ADCs, and otherdevices. It supports the ubiquitous IIS format as well as many variations of this format, including timedivision multiplex (TDM) formats with up to 32 time slots.
Each McASP includes a transmit and receive section which may operate independently or synchronously;furthermore, each section includes its own flexible clock generator and extensive error-checking logic.
As data passes through the McASP, it can be realigned so that the fixed-point representation used by theapplication code can be independent of the representation used by the external devices without requiringany CPU overhead to make the conversion.
The McASP is a configurable module and supports between 2 and 16 serial data pins. It also has theoption of supporting a Digital Interface Transmitter (DIT) mode with a full 384 bits of channel status anduser data memory.
McASP2 is not available on the C6722.
Inter-Integrated Circuit Serial Ports (I2C0, I2C1). The C672x includes two inter-integrated circuit (I2C)serial ports. A typical application is to configure one I2C serial port as a slave to an external user-interfacemicrocontroller. The other I2C serial port may then be used by the C672x DSP to control externalperipheral devices, such as a CODEC or network controller, which are functionally peripherals of the DSPdevice.
The two I2C serial ports are pin-multiplexed with the SPI0 serial port.
Serial Peripheral Interface Ports (SPI0, SPI1). As in the case of the I2C serial ports, the C672x DSPalso includes two serial peripheral interface (SPI) serial ports. This allows one SPI port to be configured asa slave to control the DSP while the other SPI serial port is used by the DSP to control externalperipherals.
The SPI ports support a basic 3-pin mode as well as optional 4- and 5-pin modes. The optional pinsinclude a slave chip-select pin and an enable pin which implements handshaking automatically inhardware for maximum SPI throughput.
The SPI0 port is pin-multiplexed with the two I2C serial ports (I2C0 and I2C1). The SPI1 serial port ispin-multiplexed with five of the serial data pins from McASP0 and McASP1.
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1.2.1 Device Compatibility
TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
Real-Time Interrupt Timer (RTI). The real-time interrupt timer module includes:•Two 32-bit counter/prescaler pairs•Two input captures (tied to McASP direct memory access [DMA] events for sample rate measurement)•Four compares with automatic update capability•Digital Watchdog (optional) for enhanced system robustness
Clock Generation (PLL and OSC). The C672x DSP includes an on-chip oscillator that supports crystalsin the range of 12 MHz to 25 MHz. Alternatively, the clock can be provided externally through the CLKINpin.
The DSP includes a flexible, software-programmable phase-locked loop (PLL) clock generator. Threedifferent clock domains (SYSCLK1, SYSCLK2, and SYSCLK3) are generated by dividing down the PLLoutput. SYSCLK1 is the clock used by the CPU, memory controller, and memories. SYSCLK2 is used bythe peripheral subsystem and dMAX. SYSCLK3 is used exclusively for the EMIF.
The TMS320C672x floating-point digital signal processors are based on the new C67x+ CPU. This core iscode-compatible with the C67x CPU core used on the TMS320C671x DSPs, but with significantenhancements including additional floating-point instructions. See Section 2.2
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1.3 Functional Block Diagram
Program/Data
RAM
256K Bytes
256
256 Program/Data ROM Page0
256K Bytes
256 Program/Data ROM Page1
128K Bytes
3232
DMPPMP
CSP 32
256
32K Bytes
Program
Cache
64
D1
Data
R/W
R/W
Data
D2 64
256
Program
FetchINTI/O
C67x+ CPU
Memory
Controller
32
High-Performance
Crossbar Switch 32
McASP DMA Bus
JTAG EMU
32
32
32
32
32
32
32
32
Peripheral Configuration Bus
EMIF
32
Events
In
32
MAX1MAX0
32
CONTROL
32
Interrupts
Out
I/O
dMAX
McASP0
16 Serializers
McASP1
6 Serializers
McASP2
2 Serializers
+ DIT
SPI1
SPI0
I2C1
I2C0
RTI32
UHPI
PLL
Peripheral Interrupt and DMA Events
32
32
32
32
32
TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
Figure 1-1 shows the functional block diagram of the C672x device.
A. UHPI is available only on the C6727. McASP2 is not available on the C6722.
Figure 1-1. C672x DSP Block Diagram
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Contents
TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
1 TMS320C6727, TMS320C6726, TMS320C6722 4.3 Recommended Operating Conditions ............... 33DSPs ........................................................ 1
4.4 Electrical Characteristics ............................ 341.1 Features .............................................. 1
4.5 Parameter Information .............................. 351.2 Description ............................................ 2
4.6 Timing Parameter Symbology ....................... 361.2.1 Device Compatibility ................................. 4
4.7 Power Supplies ...................................... 371.3 Functional Block Diagram ............................ 5
4.8 Reset ................................................ 382 Device Overview ......................................... 7
4.9 Dual Data Movement Accelerator (dMAX) .......... 392.1 Device Characteristics ................................ 7
4.10 External Interrupts ................................... 442.2 Enhanced C67x+ CPU ............................... 8
4.11 External Memory Interface (EMIF) .................. 452.3 CPU Interrupt Assignments ........................... 9
4.12 Universal Host-Port Interface (UHPI) [C6727 Only] .552.4 Internal Program/Data ROM and RAM .............. 10
4.13 Multichannel Audio Serial Ports (McASP0, McASP1,and McASP2) ........................................ 682.5 Program Cache ...................................... 11
4.14 Serial Peripheral Interface Ports (SPI0, SPI1) ...... 802.6 High-Performance Crossbar Switch ................. 12
4.15 Inter-Integrated Circuit Serial Ports (I2C0, I2C1) ... 932.7 Memory Map Summary ............................. 15
4.16 Real-Time Interrupt (RTI) Timer With Digital2.8 Boot Modes .......................................... 16
Watchdog ............................................ 972.9 Pin Assignments .................................... 19
4.17 External Clock Input From Oscillator or CLKIN Pin 1002.10 Development ........................................ 26
4.18 Phase-Locked Loop (PLL) ......................... 1023 Device Configurations ................................. 30
5 Application Example ................................. 1053.1 Device Configuration Registers ..................... 30
6 Revision History ...................................... 1063.2 Peripheral Pin Multiplexing Options ................. 30
7 Mechanical Data ....................................... 1073.3 Peripheral Pin Multiplexing Control ................. 31
7.1 Package Thermal Resistance Characteristics ..... 1074 Peripheral and Electrical Specifications ........... 33
7.2 Supplementary Information About the 144-Pin RFP4.1 Electrical Specifications ............................. 33
PowerPAD™ Package ............................. 1084.2 Absolute Maximum Ratings ......................... 33
7.3 Packaging Information ............................. 109
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2 Device Overview
2.1 Device Characteristics
TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
Table 2-1 provides an overview of the C672x DSPs. The table shows significant features of each device,including the capacity of on-chip memory, the peripherals, the execution time, and the package type withpin count.
Table 2-1. Characteristics of the C672x Processors
HARDWARE FEATURES C6727 C6726 C6722
dMAX 1EMIF 1 (32-bit) 1 (16-bit) 1 (16-bit)Peripherals
UHPI 1 0 0Not all peripheral pins are
McASP 3 3 (McASP2 DIT only) 2available at the same time.(For more details, see the
SPI 2Device Configurations section.)
I2C 2RTI 132KB Program Cache 32KB Program Cache 32KB Program CacheOn-Chip Memory Size (KB) 256KB RAM 256KB RAM 128KB RAM384KB ROM 384KB ROM 384KB ROMControl Status RegisterCPU ID + CPU Rev ID 0x0300(CSR.[31:16])Frequency MHz 300, 250 250, 225 250, 225, 2003.3 ns (C6727-300) 4 ns (C6722-250)4 ns (C6726-250)Cycle Time ns 4 ns (C6727A-250 and 4.4 ns (C6722A-225)4.4 ns (C6726A-225)C6727-250) 5 ns (C6722-200)Core (V) 1.2 VVoltage
I/O (V) 3.3 VPrescaler /1, /2, /3, ..., /32Clock Generator Options Multiplier x4, x5, x6, ..., x25Postscaler /1, /2, /3, ..., /32256-Terminal PBGA(GDH)17 x 17 mm – –256-Terminal GreenPackages (see Section 7 )
PBGA (ZDH)
144-Pin PowerPAD 144-Pin PowerPAD20 x 20 mm –
Green TQFP (RFP) Green TQFP (RFP)Process Technology µm 0.13 µmProduct Preview (PP),Product Status
(1)
Advance Information (AI), or PDProduction Data (PD)
(1) Advance Information concerns new products in the sampling or preproduction phase of development. Characteristic data and otherspecifications are subject to change without notice.
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2.2 Enhanced C67x+ CPU
.D1 .M1 .S1 .L1
Register File A
Data Path A
Cross
Paths
.D2 .M2 .S2 .L2
Register File B
Data Path B
TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
The TMS320C672x floating-point digital signal processors are based on the new C67x+ CPU. This core iscode-compatible with the C67x CPU core used on the TMS320C671x DSPs, but with significantenhancements including an increase in core operating frequency from 225 MHz to 300 MHz
(2)
whileoperating at 1.2 V.
The CPU fetches 256-bit-wide advanced very-long instruction word (VLIW) fetch packets that arecomposed of variable-length execute packets. The execute packets can supply from one to eight 32-bitinstructions to the eight functional units during every clock cycle. The variable-length execute packets area key memory-saving feature, distinguishing the C67x CPU from other VLIW architectures. Additionally,execute packets can now span fetch packets, providing a code size improvement over the C67x CPUcore.
The CPU features two data paths, shown in Figure 2-1 , each composed of four functional units (.D, .M, .S,and .L) and a register file. The .D unit in each data path is a data-addressing unit that is responsible for alldata transfers between the register files and the memory. The .M functional units are dedicated formultiplies, and the .S and .L functional units perform a general set of arithmetic, logical, and branchfunctions. All instructions operate on registers as opposed to data in memory, but results stored in the32-bit registers can be subsequently moved to memory as bytes, half-words, or words.
Figure 2-1. CPU Data Paths
The register file in each data path contains 32 32-bit registers for a total of 64 general-purpose registers.This doubles the number of registers found on the C67x CPU core, allowing the optimizing C compiler topipeline more complex loops by decreasing register pressure significantly.
The four functional units in each data path of the CPU can freely share the 32 registers belonging to thatdata path. Each data path also features a single cross path connected to the register file on the opposingdata path. This allows each data path to source one cross-path operand per cycle from the opposingregister file. On the C67x+ CPU, this single cross-path operand can be used by two functional units percycle, an improvement over the C67x CPU in which only one functional unit could use the cross-pathoperand. In addition, the cross-path register read(s) are not counted as part of the limit of four reads of thesame register in a single cycle.
The C67x+ CPU executes all C67x instructions plus new floating-point instructions to improveperformance specifically during audio processing. These new instructions are listed in Table 2-2 .(2) CPU speed is device-dependent. See Table 2-1 .
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2.3 CPU Interrupt Assignments
TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
Table 2-2. New Floating-Point Instructions for C67x+ CPU
FLOATING-POINTINSTRUCTION IMPROVESOPERATION
(1)
MPYSPDP SP x DP →DP Faster than MPYDP.Improves high Q biquads (bass management) and FFT.MPYSP2DP SP x SP →DP Faster than MPYDP.Improves Long FIRs (EQ).ADDSP (new to CPU “S” Unit) SP + SP →SPADDDP (new to CPU “S” Unit) DP + DP →DP
Now up to four floating-point add and subtract operations in parallel.Improves FFT performance and symmetric FIR.SUBSP (new to CPU “S” Unit) SP – SP →SPSUBDP (new to CPU “S” Unit) DP – DP →DP
(1) SP means IEEE Single-Precision (32-bit) operations and DP means IEEE Double-Precision (64-bit) operations.
Finally, two new registers, which are dedicated to communication with the dMAX unit, have been added tothe C67x+ CPU. These registers are the dMAX Event Trigger Register (DETR) and the dMAX EventStatus Register (DESR). They allow the CPU and dMAX to communicate without requiring any accessesto the memory system.
Table 2-3 lists the interrupt channel assignments on the C672x device. If more than one source is listed,the interrupt channel is shared and an interrupt on this channel could have come from any of the enabledperipherals on that channel.
The dMAX peripheral has two CPU interrupts dedicated to reporting FIFO status (INT7) and transfercompletion (INT8). In addition, the dMAX can generate interrupts to the CPU on lines INT9–13 and INT15in response to peripheral events. To enable this functionality, the associated Event Entry within the dMAXcan be programmed so that a CPU interrupt is generated when the peripheral event is received.
Table 2-3. CPU Interrupt Assignments
CPU INTERRUPT INTERRUPT SOURCE
INT0 RESETINT1 NMI (From dMAX or EMIF Interrupt)INT2 ReservedINT3 ReservedINT4 RTI Interrupt 0INT5 RTI Interrupts 1, 2, 3, and RTI Overflow Interrupts 0 and 1.INT6 UHPI CPU Interrupt (from External Host MCU)INT7 FIFO status notification from dMAXINT8 Transfer completion notification from dMAXINT9 dMAX event (0x2 specified in the dMAX interrupt event entry)INT10 dMAX event (0x3 specified in the dMAX interrupt event entry)INT11 dMAX event (0x4 specified in the dMAX interrupt event entry)INT12 dMAX event (0x5 specified in the dMAX interrupt event entry)INT13 dMAX event (0x6 specified in the dMAX interrupt event entry)INT14 I2C0, I2C1, SPI0, SPI1 InterruptsINT15 dMAX event (0x7 specified in the dMAX interrupt event entry)
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2.4 Internal Program/Data ROM and RAM
00 20
2707
2F
2808
0F
3F
38 37 30
1F 18 10 17
3F
38 37 30
1F
18 17 10
2F
28 27 20
0F
08 00 07
Byte
ROM Page 1
Base Address
0x0004 0000
ROM Page 0
Base Address
0x0000 0000
Bank
0Bank 1Bank 2Bank 3
13 33 10 30 17 37 14 34
1B 3B
18 38
1F 3F
1C 3C
RAM Page 0
Base Address
0x1000 0000
00 20 03 23 07 04
27 24
0B
08
2B
28
0F
0C
2F
2C
Byte
Bank
0Bank 1Bank 2Bank 3Bank 4Bank 5Bank 6Bank 7
TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
The organization of program/data ROM and RAM on C672x is simple and efficient. ROM is organized astwo 256-bit-wide pages with four 64-bit-wide banks. RAM is organized as a single 256-bit-wide page witheight 32-bit-wide banks.
The internal memory organization is illustrated in Figure 2-2 (ROM) and Figure 2-3 (RAM).
Figure 2-2. Program/Data ROM Organization
Figure 2-3. Program/Data RAM Organization
The C672x memory controller supports up to three parallel accesses to the internal RAM and ROM fromthree of the following four sources as long as there are no bank conflicts:•Two 64-bit data accesses from the C67x+ CPU•One 256-bit-wide program fetch from the program cache•One 32-bit data access from the peripheral system (either dMAX or UHPI)
A program cache miss is 256 bits wide and conflicts only with data accesses to the same page. Multipledata accesses to different pages, or to the same page but different banks will occur without conflict.
The organization of the C672x internal memory system into multiple pages (3 total) and a large number ofbanks (16 total) means that it is straightforward to optimize DSP code to avoid data conflicts. Severalfactors, including the large program cache and the partitioning of the memory system into multiple pages,minimize the number of program versus data conflicts.
The result is an efficient memory system which allows easy tuning towards the maximum possible CPUperformance.
The C672x ROM consists of a software bootloader plus additional software. Please refer to theC9230C100 TMS320C672x Floating-Point Digital Signal Processors ROM Data Manual (literature numberSPRS277) for more details on the ROM contents.
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