Texas Instruments TMS320C6745 DSP User manual

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMS320C6745, TMS320C6747
SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor
1 TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor
1
1.1 Features
1
• Software Support
– TI DSP/BIOS™
– Chip Support Library and DSP Library
• 375- and 456-MHz TMS320C674x VLIW DSP
• C674x Instruction Set Features
– Superset of the C67x+ and C64x+ ISAs
– Up to 3648 MIPS and 2736 MFLOPS C674x
– Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– Compact 16-Bit Instructions
• C674x Two-Level Cache Memory Architecture
– 32KB of L1P Program RAM/Cache
– 32KB of L1D Data RAM/Cache
– 256KB of L2 Unified Mapped RAM/Cache
– Flexible RAM/Cache Partition (L1 and L2)
• Enhanced Direct Memory Access Controller 3
(EDMA3):
– 2 Transfer Controllers
– 32 Independent DMA Channels
– 8 Quick DMA Channels
– Programmable Transfer Burst Size
• TMS320C674x Fixed- and Floating-Point VLIW
DSP Core
– Load-Store Architecture with Nonaligned
Support
– 64 General-Purpose Registers (32-Bit)
– Six ALU (32- and 40-Bit) Functional Units
– Supports 32-Bit Integer, SP (IEEE Single
Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point
– Supports up to Four SP Additions Per Clock,
Four DP Additions Every 2 Clocks
– Supports up to Two Floating-Point (SP or DP)
Reciprocal Approximation (RCPxP) and
Square-Root Reciprocal Approximation
(RSQRxP) Operations Per Cycle
– Two Multiply Functional Units
– Mixed-Precision IEEE Floating Point Multiply
Supported up to:
– 2 SP x SP -> SP Per Clock
– 2 SP x SP -> DP Every Two Clocks
– 2 SP x DP -> DP Every Three Clocks
– 2 DP x DP -> DP Every Four Clocks
– Fixed-Point Multiply Supports Two 32 x 32-Bit
Multiplies, Four 16 x 16-Bit Multiplies, or
Eight 8 x 8-Bit Multiplies per Clock Cycle, and
Complex Multiples
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Hardware Support for Modulo Loop
Operation
– Protected Mode Operation
– Exceptions Support for Error Detection and
Program Redirection
• 128KB of RAM Shared Memory (TMS320C6747
Only)
• 3.3-V LVCMOS I/Os (Except for USB Interfaces)
• Two External Memory Interfaces:
– EMIFA
– NOR (8- or 16-Bit-Wide Data)
– NAND (8- or 16-Bit-Wide Data)
– 16-Bit SDRAM with 128-MB Address Space
(TMS320C6747 Only)
– EMIFB
– 32-Bit or 16-Bit SDRAM with 256-MB
Address Space (TMS320C6747)
– 16-Bit SDRAM with 128-MB Address Space
(TMS320C6745)
• Three Configurable 16550-Type UART Modules:
– UART0 with Modem Control Signals
– Autoflow Control Signals (CTS, RTS) on UART0
Only
– 16-Byte FIFO
– 16x or 13x Oversampling Option
• LCD Controller (TMS320C6747 Only)
• Two Serial Peripheral Interfaces (SPIs) Each with
One Chip Select
• Multimedia Card (MMC)/Secure Digital (SD) Card
Interface with Secure Data I/O (SDIO)
• Two Master and Slave Inter-Integrated Circuit (I2C
Bus™)
• One Host-Port Interface (HPI) with 16-Bit-Wide
Muxed Address/Data Bus for High Bandwidth
(TMS320C6747 Only)
• Programmable Real-Time Unit Subsystem
(PRUSS)
– Two Independent Programmable Realtime Unit
(PRU) Cores
– 32-Bit Load and Store RISC Architecture
– 4KB of Instruction RAM per Core
– 512 Bytes of Data RAM per Core

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– PRUSS can be Disabled via Software to
Save Power
– Standard Power-Management Mechanism
– Clock Gating
– Entire Subsystem Under a Single PSC Clock
Gating Domain
– Dedicated Interrupt Controller
– Dedicated Switched Central Resource
• USB 1.1 OHCI (Host) with Integrated PHY (USB1)
(TMS320C6747 Only)
• USB 2.0 OTG Port with Integrated PHY (USB0)
– USB 2.0 High- and Full-Speed Client
(TMS320C6747)
– USB 2.0 Full-Speed Client (TMS320C6745)
– USB 2.0 High-, Full-, and Low-Speed Host
(TMS320C6747)
– USB 2.0 Full- and Low-Speed Host
(TMS320C6745)
– High-Speed Functionality Available on
TMS320C6747 Device Only
– End Point 0 (Control)
– End Points 1,2,3,4 (Control, Bulk, Interrupt or
ISOC) RX and TX
• Three Multichannel Audio Serial Ports (McASPs):
– TMS320C6747 Supports 3 McASPs
– TMS320C6745 Supports 2 McASPs
– Six Clock Zones and 28 Serial Data Pins
– Supports TDM, I2S, and Similar Formats
– DIT-Capable (McASP2)
– FIFO Buffers for Transmit and Receive
• 10/100 Mbps Ethernet MAC (EMAC):
– IEEE 802.3 Compliant (3.3-V I/O Only)
– RMII Media-Independent Interface
– Management Data I/O (MDIO) Module
• Real-Time Clock with 32-kHz Oscillator and
Separate Power Rail (TMS320C6747 Only)
• One 64-Bit General-Purpose Timer (Configurable
as Two 32-Bit Timers)
• One 64-Bit General-Purpose Watchdog Timer
(Configurable as Two 32-Bit General-Purpose
Timers)
• Three Enhanced Pulse Width Modulators
(eHRPWMs):
– Dedicated 16-Bit Time-Base Counter with
Period and Frequency Control
– 6 Single Edge, 6 Dual Edge Symmetric, or 3
Dual Edge Asymmetric Outputs
– Dead-Band Generation
– PWM Chopping by High-Frequency Carrier
– Trip Zone Input
• Three 32-Bit Enhanced Capture (eCAP) Modules:
– Configurable as 3 Capture Inputs or 3 Auxiliary
Pulse Width Modulator (APWM) Outputs
– Single-Shot Capture of up to Four Event Time-
Stamps
• Two 32-Bit Enhanced Quadrature Encoder Pulse
(eQEP) Modules
• TMS320C6747 Device:
– 256-Ball Pb-Free Plastic Ball Grid Array (PBGA)
[ZKB Suffix], 1.0-mm Ball Pitch
• TMS320C6745 Device:
– 176-pin PowerPAD™ Plastic Quad Flat Pack
[PTP suffix], 0.5-mm Pin Pitch
• Commercial, Industrial, Extended, or Automotive
Temperature
1.2 Applications
• A/V Receivers
• Automotive Amplifiers
• Soundbars
• Home Theatre Systems
• Professional Audio
• Network Streaming Audio
1.3 Description
The TMS320C6745/6747 device is a low-power digital signal processor based on a TMS320C674x DSP
core. It consumes significantly lower power than other members of the TMS320C6000™ platform of
DSPs.
The TMS320C6745/6747 device enables original-equipment manufacturers (OEMs) and original-design
manufacturers (ODMs) to quickly bring to market devices featuring high processing performance .
The TMS320C6745/6747 DSP core uses a two-level cache-based architecture. The Level 1 program
cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-
associative cache. The Level 2 program cache (L2P) consists of a 256-KB memory space that is shared
between program and data space. L2 memory can be configured as mapped memory, cache, or
combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional
128KB of RAM shared memory (TMS320C6747 only) is available for use by other hosts without affecting
DSP performance.

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The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output
(MDIO) module; two I2C Bus interfaces; 3 multichannel audio serial ports (McASPs) with 16/9 serializers
and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a
configurable 16-bit host-port interface (HPI) [TMS320C6747 only]; up to 8 banks of 16 pins of general-
purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other
peripherals; 3 UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width
modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can
be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit
enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an
asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a
higher speed memory interface (EMIFB) for SDRAM.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the
TMS320C6745/6747 device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10
Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for
PHY configuration.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections later in this document
and the associated peripheral reference guides.
(1) For more information on these devices, see Section 8, Mechanical Packaging and Orderable
Information.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE
TMS320C6745 HLQFP (176) 24.00 mm x 24.00 mm
TMS320C6747 BGA (256) 17.00 mm x 17.00 mm

Switched Central Resource (SCR)
BOOT ROM
256KB L2 RAM
32KB
L1 RAM
32KB
L1 Pgm
AET
C674x
DSP CPU
DSP Subsystem
JTAG Interface
Serial Interfaces
I C
(2)
2SPI
(2)
UART
(3)
Audio Ports
McASP
w/FIFO
(2)
DMA
Peripherals
External Memory Interfaces
Connectivity
EDMA3
Control Timers
eHRPWM
(3)
eCAP
(3)
eQEP
(2)
(10/100)
EMAC
(RMII)
MDIO
USB2.0
OTG Ctlr
PHY
MMC/SD
(8b)
EMIFA(8b)
NAND/Flash
EMIFB
SDRAM Only
(16b)
GPIO PRU
Subsystem
System Control
Input
Clock(s)
Power/Sleep
Controller
Memory
Protection
Pin
Multiplexing
PLL/Clock
Generator
w/OSC
General-
Purpose
Timer
General-
Purpose
Timer
(Watchdog)
Switched Central Resource (SCR)
BOOT ROM
256KB L2 RAM
32KB
L1 RAM
32KB
L1 Pgm
AET
C674x
DSP CPU
DSP Subsystem
JTAG Interface
Serial Interfaces
I C
(2)
2SPI
(2)
UART
(3)
Audio Ports
McASP
w/FIFO
(3)
DMA
Peripherals
Display Internal Memory
LCD
Ctlr 128KB
RAM
External Memory Interfaces
Connectivity
EDMA3
Control Timers
eHRPWM
(3)
eCAP
(3)
eQEP
(2)
(10/100)
EMAC
(RMII)
MDIO
USB1.1
OHCI Ctlr
PHY
USB2.0
OTG Ctlr
PHY
HPI MMC/SD
(8b)
EMIFA(8b/16B)
NAND/Flash
16b SDRAM
EMIFB
SDRAM Only
(16b/32b)
GPIO PRU
Subsystem
System Control
Input
Clock(s)
Power/Sleep
Controller
Memory
Protection
Pin
Multiplexing
RTC/
32-kHz
OSC
PLL/Clock
Generator
w/OSC
General-
Purpose
Timer
General-
Purpose
Timer
(Watchdog)
4
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Processor Copyright © 2008–2014, Texas Instruments Incorporated
1.4 Functional Block Diagram
Note: Not all peripherals are available at the same time due to multiplexing. See Table 3-1 for details on which device
components are available on each device.
Figure 1-1. TMS320C6747 Functional Block Diagram
Note: Not all peripherals are available at the same time due to multiplexing. See Table 3-1 for details on which device
components are available on each device.
Figure 1-2. TMS320C6745 Functional Block Diagram

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Table of ContentsCopyright © 2008–2014, Texas Instruments Incorporated
Table of Contents
1 TMS320C6745, TMS320C6747 Fixed- and
Floating-Point Digital Signal Processor............. 1
1.1 Features .............................................. 1
1.2 Applications........................................... 2
1.3 Description............................................ 2
1.4 Functional Block Diagram ............................ 4
2 Revision History ......................................... 6
3 Device Overview ......................................... 8
3.1 Device Characteristics................................ 8
3.2 Device Compatibility.................................. 9
3.3 DSP Subsystem..................................... 10
3.4 Memory Map Summary ............................. 21
3.5 Pin Assignments .................................... 26
3.6 Terminal Functions.................................. 28
4 Device Configuration.................................. 56
4.1 Boot Modes ......................................... 56
4.2 SYSCFG Module.................................... 57
4.3 Pullup/Pulldown Resistors .......................... 59
5 Device Operating Conditions ........................ 60
5.1 Absolute Maximum Ratings Over Operating Case
Temperature Range
(Unless Otherwise Noted) ................................. 60
5.2 Handling Ratings.................................... 60
5.3 Recommended Operating Conditions............... 61
5.4 Notes on Recommended Power-On Hours (POH) .62
5.5 Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating Case
Temperature (Unless Otherwise Noted) ............ 63
6 Peripheral Information and Electrical
Specifications........................................... 64
6.1 Parameter Information .............................. 64
6.2 Recommended Clock and Control Signal Transition
Behavior............................................. 65
6.3 Power Supplies...................................... 65
6.4 Reset ................................................ 66
6.5 Crystal Oscillator or External Clock Input........... 69
6.6 Clock PLLs .......................................... 71
6.7 Interrupts ............................................ 75
6.8 General-Purpose Input/Output (GPIO).............. 79
6.9 EDMA ............................................... 82
6.10 External Memory Interface A (EMIFA) .............. 87
6.11 External Memory Interface B (EMIFB) .............. 98
6.12 Memory Protection Units .......................... 106
6.13 MMC / SD / SDIO (MMCSD)....................... 109
6.14 Ethernet Media Access Controller (EMAC)........ 112
6.15 Management Data Input/Output (MDIO)........... 117
6.16 Multichannel Audio Serial Ports (McASP0, McASP1,
and McASP2) ...................................... 119
6.17 Serial Peripheral Interface Ports (SPI0, SPI1)..... 132
6.18 Enhanced Capture (eCAP) Peripheral............. 151
6.19 Enhanced Quadrature Encoder (eQEP)
Peripheral .......................................... 154
6.20 Enhanced High-Resolution Pulse-Width Modulator
(eHRPWM)......................................... 156
6.21 LCD Controller ..................................... 160
6.22 Timers.............................................. 175
6.23 Inter-Integrated Circuit Serial Ports (I2C0, I2C1) .. 177
6.24 Universal Asynchronous Receiver/Transmitter
(UART)............................................. 182
6.25 USB1 Host Controller Registers (USB1.1 OHCI).. 184
6.26 USB0 OTG (USB2.0 OTG) ........................ 185
6.27 Host-Port Interface (UHPI)......................... 193
6.28 Power and Sleep Controller (PSC) ................ 200
6.29 Programmable Real-Time Unit Subsystem
(PRUSS) ........................................... 203
6.30 Emulation Logic.................................... 206
6.31 IEEE 1149.1 JTAG ................................ 209
6.32 Real Time Clock (RTC) ............................ 211
7 Device and Documentation Support.............. 214
7.1 Device Support..................................... 214
7.2 Documentation Support............................ 215
7.3 Support Resources ................................ 216
7.4 Related Links ...................................... 216
7.5 Trademarks ........................................ 216
7.6 Electrostatic Discharge Caution ................... 216
7.7 Glossary............................................ 216
8 Mechanical Packaging and Orderable
Information............................................. 217
8.1 Thermal Data for ZKB ............................. 217
8.2 Thermal Data for PTP ............................. 218
8.3 Supplementary Information About the 176-pin PTP
PowerPAD™ Package............................. 218
8.4 Packaging Information ............................. 219

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Revision History Copyright © 2008–2014, Texas Instruments Incorporated
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data manual revision history highlights the changes made to the SPRS377E device-specific data
manual to make it an SPRS377F revision.
Scope: Applicable updates to the TMS320C6747/C6745 Fixed- and Floating-Point Digital Signal
Processor device family, specifically relating to the TMS320C6747 and TMS320C6745 devices, which are
all now in the production data (PD) stage of development, have been incorporated.
Revision History
SEE ADDITIONS/MODIFICATIONS/DELETIONS
Global
• Turned on Navigation Icons on top of first page.
• Updated Features, Applications, and Description for consistency and translation.
• Moved Trademarks information from first page to within Section 7, Device and Documentation Support.
• Moved ESDS Warning to within Section 7, Device and Documentation Support.
Section 1.1
Features Deleted Highlights section. Information was duplicated elsewhere in Features.
Section 1.2
Applications Added NEW section.
Section 1.3
Description Added NEW Device Information Table.
Section 3.3.2.3
C674x CPU
Table 3-2, C674x Cache Registers:
• Updated/Changed REGISTER DESCRIPTION for BYTE ADDRESSES 0000, 0020, and 0040 from
"...See the System reference Guide..." to "See the Technical Reference Manual..."
Section 3.6
Terminal Functions
Table 3-21, Universal Serial Bus (USB) Terminal Functions:
• Updated/Changed USB0_VDDA12 DESCRIPTION from "...must always be connected via a 1 μF
capacitor..." to "...is recommended to be connected via a 0.22-μFcapacitor..."
Section 3.6.11
Universal
Asynchronous
Receiver/Transmitter
s (UART0, UART1,
UART2)
Table 3-16, Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions:
• Updated/Changed footnote from "...DSP Reference Guide - Literature Number SPRUFK4..." to "...DSP
Technical Reference Manual (SPRUH91)..."
Section 3.6.21
Reserved and No
Connect
Table 3-26, Reserved and No Connect Terminal Functions:
• Updated/Changed RSV4 DESCRIPTION from "...This pin may be tied high or low." to "...For proper
device operation, this pin must be tied low or to CVDD."
Section 3.6.23
Unused USB0
(USB2.0) and USB1
(USB1.1) Pin
Configurations
Moved to within Section 3.6, Terminal Functions
Table 3-28, Unused USB0 and USB1 Pin Configurations:
• Updated/Changed USB0_VDDA12 Configuration by combining both Configuration columns and
changing text to "Internal USB0 PHY output connected to an external..."
Section 5
Device Operating
Conditions
Section 5.2, Handling Ratings:
• Split handling, ratings, and certifications from the Abs Max table and placed in NEW Handling Ratings
table.
Section 5.4
Notes on
Recommended
Power-On Hours
(POH)
Table 5-1, Recommended Power-On Hours:
• Added Silicon Revision column.
Section 6.10.6
EMIFA Electrical
Data/Timing
Table 6-22, EMIFA Asynchronous Memory Switching Characteristics:
• Updated/Changed the MIN, NOM, and MAX equations for NO. 3, 10, 15, and 24 from "...(EWC*16)..." to
"...EWC..."
Section 5.3, Recommended Operating Conditions:
• Added "Unless specifically indicated" to "These I/O specifications apply to ..." footnote

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Revision HistoryCopyright © 2008–2014, Texas Instruments Incorporated
Revision History (continued)
SEE ADDITIONS/MODIFICATIONS/DELETIONS
Section 6.11.3
EMIFB Electrical
Data/Timing
Table 6-26, EMIFB SDRAM Interface Timing Requirements:
• Updated/Changed Parameter No. 19 from "tsu(DV-CLKH)" to "t(DV-CLKH)"
• Added new column: "CVDD = 1.3V"
• Added new footnote containing "...range rated devices for 456 MHz max CPU operating..."
• Added new footnote containing "...range rated devices for 400/375/300/266/200 MHz max CPU
operating ..."
Table 6-27, EMIFB SDRAM Interface Switching Characteristics for Commercial (Default) Temperature
Range:
• Updated/Changed table title from "...Switching Characteristics..." to "...Switching Characteristics for
Commercial (Default) Temperature Range"
• Added new footnote containing "...range rated devices for 456 MHz max CPU operating ..."
• Added new footnote containing "...range rated devices for 400/375/300/266/200 MHz max CPU
operating..."
• Updated/Changed CVDD = 1.3V MIN column values for Parameter No. 4, 6, 8, 10, 12, 14, 16, and 18
from "0.9" to "1.1"
• Updated/Changed CVDD = 1.3V MAX column values for Parameter No. 3, 5, 7, 9, 11, 13, 15, and 17
from "5.1" to "4.25"
• Populated CVDD = 1.2V column with values (was empty)
• Updated/Changed Parameter No. 18 from "tena(CLKH-DLZ)" to "t(CLKH-DLZ)"
Table 6-28, EMIFB SDRAM Interface Switching Characteristics for Industrial, Extended, and Automotive
Temperature Ranges:
• Added NEW table
Section 6.16
Multichannel Audio
Serial Ports
(McASP0, McASP1,
and McASP2)
Table 6-45, McASP Registers Accessed Through DMA Port:
• Updated/Changed Read Accesses Register Description from "XBUSEL = 0 in XFMT" to "RBUSEL = 0 in
RFMT"
• Updated/Changed Write Accesses Register Description from "RBUSEL = 0 in RFMT" to "XBUSEL = 0 in
XFMT"
Section 7.4
Related Links Added NEW section.
Section 7.7
Glossary Added NEW section.

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Device Overview Copyright © 2008–2014, Texas Instruments Incorporated
3 Device Overview
3.1 Device Characteristics
Table 3-1 provides an overview of the C6745/6747 low power digital signal processor. The table shows
significant features of the device, including the capacity of on-chip RAM, peripherals, and the package
type with pin count.
Table 3-1. Characteristics of the C6745/C6747 Processor
HARDWARE FEATURES C6745 C6747
Peripherals
Not all peripherals pins
are available at the
same time (for more
detail, see the Device
Configurations section).
EMIFB 16bit, up to 128MB SDRAM 16/32bit, up to 256MB SDRAM
EMIFA Asynchronous (8-bit bus width) RAM,
Flash, NOR, NAND Asynchronous (8/16-bit bus width) RAM,
Flash, 16bit up to 128MB SDRAM, NOR,
NAND
Flash Card Interface MMC and SD cards supported.
EDMA3 32 independent channels, 8 QDMA channels, 2 Transfer controllers
Timers 2 64-Bit General Purpose (each configurable as 2 separate 32-bit timers, 1 configurable
as Watch Dog)
UART 3 (one with RTS and CTS flow control)
SPI 2 (each with one hardware chip select)
I2C 2 (both Master/Slave)
Multichannel Audio
Serial Port [McASP] 2 (each with transmit/receive, FIFO buffer, 16/9 serializers) 3 (each with transmit/receive, FIFO buffer, 16/9 serializers)
10/100 Ethernet MAC
with Management Data
I/O 1 (RMII Interface)
eHRPWM 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
eCAP 3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs
eQEP 2 32-bit QEP channels with 4 inputs/channel
UHPI - 1 (16-bit multiplexed address/data)
USB 2.0 (USB0) Full Speed Host Or Device with On-Chip
PHY High-Speed OTG Controller with on-chip OTG PHY
USB 1.1 (USB1) - Full-Speed OHCI (as host) with on-chip
PHY
General-Purpose
Input/Output Port 8 banks of 16-bit
LCD Controller - 1
RTC - 1 (32 KHz oscillator and seperate power trail. Provides time and date tracking and
alarm capability.)
PRU Subsystem
(PRUSS) 2 Programmable PRU Cores
On-Chip Memory
Size (Bytes) 320 KB RAM 448 KB RAM
Organization
DSP
32KB L1 Program (L1P)/Cache (up to 32KB)
32KB L1 Data (L1D)/Cache (up to 32KB)
256KB Unified Mapped RAM/Cache (L2)
DSP Memories can be made accessible to EDMA3, and other peripherals.
-ADDITIONAL MEMORY
128KB RAM
C674x CPU ID + CPU
Rev ID Control Status Register (CSR.[31:16]) 0x1400
C674x Megamodule
Revision Revision ID Register (MM_REVID[15:0]) 0x0000

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Table 3-1. Characteristics of the C6745/C6747 Processor (continued)
HARDWARE FEATURES C6745 C6747
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
JTAG BSDL_ID DEVIDR0 register 0x0B7D F02F (Silicon Revision 1.0) 0x8B7D F02F (Silicon Revision 1.1)
0x9B7D F02F (Silicon Revisions 3.0, 2.1, and 2.0)
CPU Frequency MHz 674x DSP at 375 MHz(1.2V) or 456 MHz (1.3V)
Voltage Core (V) 1.2V / 1.3V
I/O (V) 3.3 V
Package 24 mm x 24 mm, 176-Pin, 0.5 mm pitch,
TQFP (PTP) 17 mm x 17 mm, 256-Ball 1 mm pitch, PBGA (ZKB)
Product Status(1)
Product Preview (PP),
Advance Information
(AI),
or Production Data
(PD)
375 MHz Versions -PD
456 MHz Version - PD
3.2 Device Compatibility
The C674x DSP core is code-compatible with the C6000™ DSP platform and supports features of both
the C64x+ and C67x+ DSP families.

Instruction Fetch
C674x
Fixed/Floating Point CPU
Register
File A
Register
File B
Cache Control
Memory Protect
Bandwidth Mgmt
L1P
256
Cache Control
Memory Protect
Bandwidth Mgmt
L1D
64 64
8 x 32
32K Bytes
L1D RAM/
Cache
32K Bytes
L1P RAM/
Cache
256
Cache Control
Memory Protect
Bandwidth Mgmt
L2
256K Bytes
L2 RAM
256
Boot ROM
256
CFG
MDMA SDMA
EMC
Power Down
Interrupt
Controller
IDMA
256
256
256
256
256
64
High
Performance
Switch Fabric
64 64 64
Configuration
Peripherals
Bus
32
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3.3 DSP Subsystem
The DSP Subsystem includes the following features:
• C674x DSP CPU
• 32KB L1 Program (L1P)/Cache (up to 32KB)
• 32KB L1 Data (L1D)/Cache (up to 32KB)
• 256KB Unified Mapped RAM/Cache (L2)
• Boot ROM (cannot be used for application code)
• Little endian
Figure 3-1. C674x Megamodule Block Diagram

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3.3.1 C674x DSP CPU Description
The C674x Central Processing Unit (CPU) consists of eight functional units, two register files, and two
data paths as shown in Figure 3-2. The two general-purpose register files (A and B) each contain 32 32-
bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data
address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-
bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in
register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the
next upper register (which is always an odd-numbered register).
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one
instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units
perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from
memory to the register file and store results from the register file into memory.
The C674x CPU combines the performance of the C64x+ core with the floating-point capabilities of the
C67x+ core.
Each C674x .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x
32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with
add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four
16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for
Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and
modems require complex multiplication. The complex multiply (CMPY) instruction takes four 16-bit inputs
and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding
capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The
32 x 32 bit multiply instructions provide the extended precision necessary for high-precision algorithms on
a variety of signed and unsigned 32-bit data types.
The .L Unit (or Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on
a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data
performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.
The C674x core enhances the .S unit in several ways. On the previous cores, dual 16-bit MIN2 and MAX2
comparisons were only available on the .L units. On the C674x core they are also available on the .S unit
which increases the performance of algorithms that do searching and sorting. Finally, to increase data
packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit
and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack
instructions return parallel results to output precision including saturation support.
Other new features include:
•SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where
multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size
associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.
•Compact Instructions - The native instruction size for the C6000™ devices is 32 bits. Many common
instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C674x
compiler can restrict the code to use certain registers in the register file. This compression is
performed by the code generation tools.
•Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit
multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field
multiplication.
•Exceptions Handling - Intended to aid the programmer in isolating bugs. The C674x CPU is able to
detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and
from system events (such as a watchdog time expiration).
•Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a
basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with
read, write, and execute permissions.

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•Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-
running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.
For more details on the C674x CPU and its enhancements over the C64x architecture, see the following
documents:
•TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (SPRU732)
•TMS320C64x Technical Overview (SPRU395)

src2
src2
Á
Á
Á
Á
Á
Á
Á
.D1
.M1
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
.S1
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
.L1
long src
odd dst
src2
src1
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
src1
src1
src1
even dst
even dst
odd dst
dst1
dst
src2
src2
src2
long src
DA1
ST1b
LD1b
LD1a
ST1a
Data path A
Odd
register
file A
(A1, A3,
A5...A31)
Á
Á
Á
Odd
register
file B
(B1, B3,
B5...B31)
Á
Á
Á
.D2
Á
Á
Á
Á
src1
dst
src2
DA2
LD2a
LD2b
src2
.M2 src1
Á
Á
Á
dst1
Á
Á
Á
.S2
src1
Á
Á
Á
Á
even dst
long src
odd dst
ST2a
ST2b
long src
.L2
Á
Á
Á
Á
even dst
odd dst
Á
Á
Á
src1
Data path B
Control Register
32 MSB
32 LSB
dst2 (A)
32 MSB
32 LSB
2x
1x
32 LSB
32 MSB
32 LSB
32 MSB
dst2
(B)
(B)
(A)
8
8
8
8
32
32
32
32
(C)
(C)
Even
register
file A
(A0, A2,
A4...A30)
Even
register
file B
(B0, B2,
B4...B30)
(D)
(D)
(D)
(D)
A. On .M unit, dst2 is 32 MSB.
B. On .M unit, dst1 is 32 LSB.
C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.
D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.
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Figure 3-2. TMS320C674x CPU (DSP Core) Data Paths

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3.3.2 DSP Memory Mapping
The DSP memory map is shown in Section 3.4.
3.3.2.1 External Memories
The DSP has access to the following External memories:
• Asynchronous EMIF / SDRAM / NAND / NOR Flash (EMIFA)
• SDRAM (EMIFB)
3.3.2.2 DSP Internal Memories
The DSP has access to the following DSP memories:
• L2 RAM
• L1P RAM
• L1D RAM
3.3.2.3 C674x CPU
The C674x core uses a two-level cache-based architecture. The Level 1 Program cache (L1P) is 32 KB
direct mapped cache and the Level 1 Data cache (L1D) is 32 KB 2-way set associated cache. The Level 2
memory/cache (L2) consists of a 256 KB memory space that is shared between program and data space.
L2 memory can be configured as mapped memory, cache, or a combination of both.
Table 3-2 shows a memory map of the C674x CPU cache registers for the device.
Table 3-2. C674x Cache Registers
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x0184 0000 L2CFG L2 Cache configuration register (See the Technical Reference Manual
SPRUH91 for the reset configuration)
0x0184 0020 L1PCFG L1P Size Cache configuration register (See the Technical Reference
Manual SPRUH91 for the reset configuration)
0x0184 0024 L1PCC L1P Freeze Mode Cache configuration register
0x0184 0040 L1DCFG L1D Size Cache configuration register (See the Technical Reference
Manual SPRUH91 for the reset configuration)
0x0184 0044 L1DCC L1D Freeze Mode Cache configuration register
0x0184 0048 - 0x0184 0FFC - Reserved
0x0184 1000 EDMAWEIGHT L2 EDMA access control register
0x0184 1004 - 0x0184 1FFC - Reserved
0x0184 2000 L2ALLOC0 L2 allocation register 0
0x0184 2004 L2ALLOC1 L2 allocation register 1
0x0184 2008 L2ALLOC2 L2 allocation register 2
0x0184 200C L2ALLOC3 L2 allocation register 3
0x0184 2010 - 0x0184 3FFF - Reserved
0x0184 4000 L2WBAR L2 writeback base address register
0x0184 4004 L2WWC L2 writeback word count register
0x0184 4010 L2WIBAR L2 writeback invalidate base address register
0x0184 4014 L2WIWC L2 writeback invalidate word count register
0x0184 4018 L2IBAR L2 invalidate base address register
0x0184 401C L2IWC L2 invalidate word count register
0x0184 4020 L1PIBAR L1P invalidate base address register
0x0184 4024 L1PIWC L1P invalidate word count register
0x0184 4030 L1DWIBAR L1D writeback invalidate base address register
0x0184 4034 L1DWIWC L1D writeback invalidate word count register

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Table 3-2. C674x Cache Registers (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x0184 4038 - Reserved
0x0184 4040 L1DWBAR L1D writeback base address register
0x0184 4044 L1DWWC L1D writeback word count register
0x0184 4048 L1DIBAR L1D invalidate base address register
0x0184 404C L1DIWC L1D invalidate word count register
0x0184 4050 - 0x0184 4FFF - Reserved
0x0184 5000 L2WB L2 writeback all register
0x0184 5004 L2WBINV L2 writeback invalidate all register
0x0184 5008 L2INV L2 Global Invalidate without writeback
0x0184 500C - 0x0184 5027 - Reserved
0x0184 5028 L1PINV L1P Global Invalidate
0x0184 502C - 0x0184 5039 - Reserved
0x0184 5040 L1DWB L1D Global Writeback
0x0184 5044 L1DWBINV L1D Global Writeback with Invalidate
0x0184 5048 L1DINV L1D Global Invalidate without writeback
0x0184 8000 – 0x0184 80FF MAR0 - MAR63 Reserved 0x0000 0000 – 0x3FFF FFFF
0x0184 8100 – 0x0184 817F MAR64 – MAR95 Memory Attribute Registers for EMIFA SDRAM Data (CS0)
0x4000 0000 – 0x5FFF FFFF
0x0184 8180 – 0x0184 8187 MAR96 - MAR97 Memory Attribute Registers for EMIFA Async Data (CS2)
0x6000 0000 – 0x61FF FFFF
0x0184 8188 – 0x0184 818F MAR98 – MAR99 Memory Attribute Registers for EMIFA Async Data (CS3)
0x6200 0000 – 0x63FF FFFF
0x0184 8190 – 0x0184 8197 MAR100 – MAR101 Memory Attribute Registers for EMIFA Async Data (CS4)
0x6400 0000 – 0x65FF FFFF
0x0184 8198 – 0x0184 819F MAR102 – MAR103 Memory Attribute Registers for EMIFA Async Data (CS5)
0x6600 0000 – 0x67FF FFFF
0x0184 81A0 – 0x0184 81FF MAR104 – MAR127 Reserved 0x6800 0000 – 0x7FFF FFFF
0x0184 8200 MAR128 Memory Attribute Register for Shared RAM 0x8000 0000 – 0x8001 FFFF
Reserved 0x8002 0000 – 0x81FF FFFF
0x0184 8204 – 0x0184 82FF MAR129 – MAR191 Reserved 0x8200 0000 – 0xBFFF FFFF
0x0184 8300 – 0x0184 837F MAR192 – MAR223 Memory Attribute Registers for EMIFB SDRAM Data (CS0)
0xC000 0000 – 0xDFFF FFFF
0x0184 8380 – 0x0184 83FF MAR224 – MAR255 Reserved 0xE000 0000 – 0xFFFF FFFF
Table 3-3. C674x L1/L2 Memory Protection Registers
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x0184 A000 L2MPFAR L2 memory protection fault address register
0x0184 A004 L2MPFSR L2 memory protection fault status register
0x0184 A008 L2MPFCR L2 memory protection fault command register
0x0184 A00C - 0x0184 A0FF - Reserved
0x0184 A100 L2MPLK0 L2 memory protection lock key bits [31:0]
0x0184 A104 L2MPLK1 L2 memory protection lock key bits [63:32]
0x0184 A108 L2MPLK2 L2 memory protection lock key bits [95:64]
0x0184 A10C L2MPLK3 L2 memory protection lock key bits [127:96]
0x0184 A110 L2MPLKCMD L2 memory protection lock key command register
0x0184 A114 L2MPLKSTAT L2 memory protection lock key status register
0x0184 A118 - 0x0184 A1FF - Reserved
0x0184 A200 L2MPPA0 L2 memory protection page attribute register 0
(controls memory address 0x0080 0000 - 0x0080 1FFF)

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Table 3-3. C674x L1/L2 Memory Protection Registers (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x0184 A204 L2MPPA1 L2 memory protection page attribute register 1
(controls memory address 0x0080 2000 - 0x0080 3FFF)
0x0184 A208 L2MPPA2 L2 memory protection page attribute register 2
(controls memory address 0x0080 4000 - 0x0080 5FFF)
0x0184 A20C L2MPPA3 L2 memory protection page attribute register 3
(controls memory address 0x0080 6000 - 0x0080 7FFF)
0x0184 A210 L2MPPA4 L2 memory protection page attribute register 4
(controls memory address 0x0080 8000 - 0x0080 9FFF)
0x0184 A214 L2MPPA5 L2 memory protection page attribute register 5
(controls memory address 0x0080 A000 - 0x0080 BFFF)
0x0184 A218 L2MPPA6 L2 memory protection page attribute register 6
(controls memory address 0x0080 C000 - 0x0080 DFFF)
0x0184 A21C L2MPPA7 L2 memory protection page attribute register 7
(controls memory address 0x0080 E000 - 0x0080 FFFF)
0x0184 A220 L2MPPA8 L2 memory protection page attribute register 8
(controls memory address 0x0081 0000 - 0x0081 1FFF)
0x0184 A224 L2MPPA9 L2 memory protection page attribute register 9
(controls memory address 0x0081 2000 - 0x0081 3FFF)
0x0184 A228 L2MPPA10 L2 memory protection page attribute register 10
(controls memory address 0x0081 4000 - 0x0081 5FFF)
0x0184 A22C L2MPPA11 L2 memory protection page attribute register 11
(controls memory address 0x0081 6000 - 0x0081 7FFF)
0x0184 A230 L2MPPA12 L2 memory protection page attribute register 12
(controls memory address 0x0081 8000 - 0x0081 9FFF)
0x0184 A234 L2MPPA13 L2 memory protection page attribute register 13
(controls memory address 0x0081 A000 - 0x0081 BFFF)
0x0184 A238 L2MPPA14 L2 memory protection page attribute register 14
(controls memory address 0x0081 C000 - 0x0081 DFFF)
0x0184 A23C L2MPPA15 L2 memory protection page attribute register 15
(controls memory address 0x0081 E000 - 0x0081 FFFF)
0x0184 A240 L2MPPA16 L2 memory protection page attribute register 16
(controls memory address 0x0082 0000 - 0x0082 1FFF)
0x0184 A244 L2MPPA17 L2 memory protection page attribute register 17
(controls memory address 0x0082 2000 - 0x0082 3FFF)
0x0184 A248 L2MPPA18 L2 memory protection page attribute register 18
(controls memory address 0x0082 4000 - 0x0082 5FFF)
0x0184 A24C L2MPPA19 L2 memory protection page attribute register 19
(controls memory address 0x0082 6000 - 0x0082 7FFF)
0x0184 A250 L2MPPA20 L2 memory protection page attribute register 20
(controls memory address 0x0082 8000 - 0x0082 9FFF)
0x0184 A254 L2MPPA21 L2 memory protection page attribute register 21
(controls memory address 0x0082 A000 - 0x0082 BFFF)
0x0184 A258 L2MPPA22 L2 memory protection page attribute register 22
(controls memory address 0x0082 C000 - 0x0082 DFFF)
0x0184 A25C L2MPPA23 L2 memory protection page attribute register 23
(controls memory address 0x0082 E000 - 0x0082 FFFF)
0x0184 A260 L2MPPA24 L2 memory protection page attribute register 24
(controls memory address 0x0083 0000 - 0x0083 1FFF)
0x0184 A264 L2MPPA25 L2 memory protection page attribute register 25
(controls memory address 0x0083 2000 - 0x0083 3FFF)
0x0184 A268 L2MPPA26 L2 memory protection page attribute register 26
(controls memory address 0x0083 4000 - 0x0083 5FFF)
0x0184 A26C L2MPPA27 L2 memory protection page attribute register 27
(controls memory address 0x0083 6000 - 0x0083 7FFF)
0x0184 A270 L2MPPA28 L2 memory protection page attribute register 28
(controls memory address 0x0083 8000 - 0x0083 9FFF)

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Table 3-3. C674x L1/L2 Memory Protection Registers (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x0184 A274 L2MPPA29 L2 memory protection page attribute register 29
(controls memory address 0x0083 A000 - 0x0083 BFFF)
0x0184 A278 L2MPPA30 L2 memory protection page attribute register 30
(controls memory address 0x0083 C000 - 0x0083 DFFF)
0x0184 A27C L2MPPA31 L2 memory protection page attribute register 31
(controls memory address 0x0083 E000 - 0x0083 FFFF)
0x0184 A280 L2MPPA32 L2 memory protection page attribute register 32
(controls memory address 0x0070 0000 - 0x0070 7FFF)
0x0184 A284 L2MPPA33 L2 memory protection page attribute register 33
(controls memory address 0x0070 8000 - 0x0070 FFFF)
0x0184 A288 L2MPPA34 L2 memory protection page attribute register 34
(controls memory address 0x0071 0000 - 0x0071 7FFF)
0x0184 A28C L2MPPA35 L2 memory protection page attribute register 35
(controls memory address 0x0071 8000 - 0x0071 FFFF)
0x0184 A290 L2MPPA36 L2 memory protection page attribute register 36
(controls memory address 0x0072 0000 - 0x0072 7FFF)
0x0184 A294 L2MPPA37 L2 memory protection page attribute register 37
(controls memory address 0x0072 8000 - 0x0072 FFFF)
0x0184 A298 L2MPPA38 L2 memory protection page attribute register 38
(controls memory address 0x0073 0000 - 0x0073 7FFF)
0x0184 A29C L2MPPA39 L2 memory protection page attribute register 39
(controls memory address 0x0073 8000 - 0x0073 FFFF)
0x0184 A2A0 L2MPPA40 L2 memory protection page attribute register 40
(controls memory address 0x0074 0000 - 0x0074 7FFF)
0x0184 A2A4 L2MPPA41 L2 memory protection page attribute register 41
(controls memory address 0x0074 8000 - 0x0074 FFFF)
0x0184 A2A8 L2MPPA42 L2 memory protection page attribute register 42
(controls memory address 0x0075 0000 - 0x0075 7FFF)
0x0184 A2AC L2MPPA43 L2 memory protection page attribute register 43
(controls memory address 0x0075 8000 - 0x0075 FFFF)
0x0184 A2B0 L2MPPA44 L2 memory protection page attribute register 44
(controls memory address 0x0076 0000 - 0x0076 7FFF)
0x0184 A2B4 L2MPPA45 L2 memory protection page attribute register 45
(controls memory address 0x0076 8000 - 0x0076 FFFF)
0x0184 A2B8 L2MPPA46 L2 memory protection page attribute register 46
(controls memory address 0x0077 0000 - 0x0077 7FFF)
0x0184 A2BC L2MPPA47 L2 memory protection page attribute register 47
(controls memory address 0x0077 8000 - 0x0077 FFFF)
0x0184 A2C0 L2MPPA48 L2 memory protection page attribute register 48
(controls memory address 0x0078 0000 - 0x0078 7FFF)
0x0184 A2C4 L2MPPA49 L2 memory protection page attribute register 49
(controls memory address 0x0078 8000 - 0x0078 FFFF)
0x0184 A2C8 L2MPPA50 L2 memory protection page attribute register 50
(controls memory address 0x0079 0000 - 0x0079 7FFF)
0x0184 A2CC L2MPPA51 L2 memory protection page attribute register 51
(controls memory address 0x0079 8000 - 0x0079 FFFF)
0x0184 A2D0 L2MPPA52 L2 memory protection page attribute register 52
(controls memory address 0x007A 0000 - 0x007A 7FFF)
0x0184 A2D4 L2MPPA53 L2 memory protection page attribute register 53
(controls memory address 0x007A 8000 - 0x007A FFFF)
0x0184 A2D8 L2MPPA54 L2 memory protection page attribute register 54
(controls memory address 0x007B 0000 - 0x007B 7FFF)
0x0184 A2DC L2MPPA55 L2 memory protection page attribute register 55
(controls memory address 0x007B 8000 - 0x007B FFFF)
0x0184 A2E0 L2MPPA56 L2 memory protection page attribute register 56
(controls memory address 0x007C 0000 - 0x007C 7FFF)

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Table 3-3. C674x L1/L2 Memory Protection Registers (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
(1) These addresses correspond to the L1P memory protection page attribute registers 0-15 (L1PMPPA0-L1PMPPA15) of the C674x
megamaodule. These registers are not supported for this device.
0x0184 A2E4 L2MPPA57 L2 memory protection page attribute register 57
(controls memory address 0x007C 8000 - 0x007C FFFF)
0x0184 A2E8 L2MPPA58 L2 memory protection page attribute register 58
(controls memory address 0x007D 0000 - 0x007D 7FFF)
0x0184 A2EC L2MPPA59 L2 memory protection page attribute register 59
(controls memory address 0x007D 8000 - 0x007D FFFF)
0x0184 A2F0 L2MPPA60 L2 memory protection page attribute register 60
(controls memory address 0x007E 0000 - 0x007E 7FFF)
0x0184 A2F4 L2MPPA61 L2 memory protection page attribute register 61
(controls memory address 0x007E 8000 - 0x007E FFFF)
0x0184 A2F8 L2MPPA62 L2 memory protection page attribute register 62
(controls memory address 0x007F 0000 - 0x007F 7FFF)
0x0184 A2FC L2MPPA63 L2 memory protection page attribute register 63
(controls memory address 0x007F 8000 - 0x007F FFFF)
0x0184 A300 - 0x0184 A3FF - Reserved
0x0184 A400 L1PMPFAR L1P memory protection fault address register
0x0184 A404 L1PMPFSR L1P memory protection fault status register
0x0184 A408 L1PMPFCR L1P memory protection fault command register
0x0184 A40C - 0x0184 A4FF - Reserved
0x0184 A500 L1PMPLK0 L1P memory protection lock key bits [31:0]
0x0184 A504 L1PMPLK1 L1P memory protection lock key bits [63:32]
0x0184 A508 L1PMPLK2 L1P memory protection lock key bits [95:64]
0x0184 A50C L1PMPLK3 L1P memory protection lock key bits [127:96]
0x0184 A510 L1PMPLKCMD L1P memory protection lock key command register
0x0184 A514 L1PMPLKSTAT L1P memory protection lock key status register
0x0184 A518 - 0x0184 A5FF - Reserved
0x0184 A600 - 0x0184 A63F - Reserved (1)
0x0184 A640 L1PMPPA16 L1P memory protection page attribute register 16
(controls memory address 0x00E0 0000 - 0x00E0 07FF)
0x0184 A644 L1PMPPA17 L1P memory protection page attribute register 17
(controls memory address 0x00E0 0800 - 0x00E0 0FFF)
0x0184 A648 L1PMPPA18 L1P memory protection page attribute register 18
(controls memory address 0x00E0 1000 - 0x00E0 17FF)
0x0184 A64C L1PMPPA19 L1P memory protection page attribute register 19
(controls memory address 0x00E0 1800 - 0x00E0 1FFF)
0x0184 A650 L1PMPPA20 L1P memory protection page attribute register 20
(controls memory address 0x00E0 2000 - 0x00E0 27FF)
0x0184 A654 L1PMPPA21 L1P memory protection page attribute register 21
(controls memory address 0x00E0 2800 - 0x00E0 2FFF)
0x0184 A658 L1PMPPA22 L1P memory protection page attribute register 22
(controls memory address 0x00E0 3000 - 0x00E0 37FF)
0x0184 A65C L1PMPPA23 L1P memory protection page attribute register 23
(controls memory address 0x00E0 3800 - 0x00E0 3FFF)
0x0184 A660 L1PMPPA24 L1P memory protection page attribute register 24
(controls memory address 0x00E0 4000 - 0x00E0 47FF)
0x0184 A664 L1PMPPA25 L1P memory protection page attribute register 25
(controls memory address 0x00E0 4800 - 0x00E0 4FFF)
0x0184 A668 L1PMPPA26 L1P memory protection page attribute register 26
(controls memory address 0x00E0 5000 - 0x00E0 57FF)
0x0184 A66C L1PMPPA27 L1P memory protection page attribute register 27
(controls memory address 0x00E0 5800 - 0x00E0 5FFF)

19
TMS320C6745, TMS320C6747
www.ti.com SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
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Product Folder Links: TMS320C6745 TMS320C6747
Device OverviewCopyright © 2008–2014, Texas Instruments Incorporated
Table 3-3. C674x L1/L2 Memory Protection Registers (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
(2) These addresses correspond to the L1D memory protection page attribute registers 0-15 (L1DMPPA0-L1DMPPA15) of the C674x
megamaodule. These registers are not supported for this device.
0x0184 A670 L1PMPPA28 L1P memory protection page attribute register 28
(controls memory address 0x00E0 6000 - 0x00E0 67FF)
0x0184 A674 L1PMPPA29 L1P memory protection page attribute register 29
(controls memory address 0x00E0 6800 - 0x00E0 6FFF)
0x0184 A678 L1PMPPA30 L1P memory protection page attribute register 30
(controls memory address 0x00E0 7000 - 0x00E0 77FF)
0x0184 A67C L1PMPPA31 L1P memory protection page attribute register 31
(controls memory address 0x00E0 7800 - 0x00E0 7FFF)
0x0184 A67F – 0x0184 ABFF - Reserved
0x0184 AC00 L1DMPFAR L1D memory protection fault address register
0x0184 AC04 L1DMPFSR L1D memory protection fault status register
0x0184 AC08 L1DMPFCR L1D memory protection fault command register
0x0184 AC0C - 0x0184 ACFF - Reserved
0x0184 AD00 L1DMPLK0 L1D memory protection lock key bits [31:0]
0x0184 AD04 L1DMPLK1 L1D memory protection lock key bits [63:32]
0x0184 AD08 L1DMPLK2 L1D memory protection lock key bits [95:64]
0x0184 AD0C L1DMPLK3 L1D memory protection lock key bits [127:96]
0x0184 AD10 L1DMPLKCMD L1D memory protection lock key command register
0x0184 AD14 L1DMPLKSTAT L1D memory protection lock key status register
0x0184 AD18 - 0x0184 ADFF - Reserved
0x0184 AE00 - 0x0184 AE3F - Reserved (2)
0x0184 AE40 L1DMPPA16 L1D memory protection page attribute register 16
(controls memory address 0x00F0 0000 - 0x00F0 07FF)
0x0184 AE44 L1DMPPA17 L1D memory protection page attribute register 17
(controls memory address 0x00F0 0800 - 0x00F0 0FFF)
0x0184 AE48 L1DMPPA18 L1D memory protection page attribute register 18
(controls memory address 0x00F0 1000 - 0x00F0 17FF)
0x0184 AE4C L1DMPPA19 L1D memory protection page attribute register 19
(controls memory address 0x00F0 1800 - 0x00F0 1FFF)
0x0184 AE50 L1DMPPA20 L1D memory protection page attribute register 20
(controls memory address 0x00F0 2000 - 0x00F0 27FF)
0x0184 AE54 L1DMPPA21 L1D memory protection page attribute register 21
(controls memory address 0x00F0 2800 - 0x00F0 2FFF)
0x0184 AE58 L1DMPPA22 L1D memory protection page attribute register 22
(controls memory address 0x00F0 3000 - 0x00F0 37FF)
0x0184 AE5C L1DMPPA23 L1D memory protection page attribute register 23
(controls memory address 0x00F0 3800 - 0x00F0 3FFF)
0x0184 AE60 L1DMPPA24 L1D memory protection page attribute register 24
(controls memory address 0x00F0 4000 - 0x00F0 47FF)
0x0184 AE64 L1DMPPA25 L1D memory protection page attribute register 25
(controls memory address 0x00F0 4800 - 0x00F0 4FFF)
0x0184 AE68 L1DMPPA26 L1D memory protection page attribute register 26
(controls memory address 0x00F0 5000 - 0x00F0 57FF)
0x0184 AE6C L1DMPPA27 L1D memory protection page attribute register 27
(controls memory address 0x00F0 5800 - 0x00F0 5FFF)
0x0184 AE70 L1DMPPA28 L1D memory protection page attribute register 28
(controls memory address 0x00F0 6000 - 0x00F0 67FF)
0x0184 AE74 L1DMPPA29 L1D memory protection page attribute register 29
(controls memory address 0x00F0 6800 - 0x00F0 6FFF)
0x0184 AE78 L1DMPPA30 L1D memory protection page attribute register 30
(controls memory address 0x00F0 7000 - 0x00F0 77FF)

20
TMS320C6745, TMS320C6747
SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014 www.ti.com
Submit Documentation Feedback
Product Folder Links: TMS320C6745 TMS320C6747
Device Overview Copyright © 2008–2014, Texas Instruments Incorporated
Table 3-3. C674x L1/L2 Memory Protection Registers (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x0184 AE7C L1DMPPA31 L1D memory protection page attribute register 31
(controls memory address 0x00F0 7800 - 0x00F0 7FFF)
0x0184 AE80 – 0x0185 FFFF - Reserved
See Table 3-4 for a detailed top level C6745/6747 memory map that includes the DSP memory space.