Texas Instruments TURBO-DECODER COPROCESSOR 2 TMS320C6457 DSP User manual

TMS320C6457 DSPTurbo-Decoder Coprocessor 2 (TCP2)
User's Guide
Literature Number: SPRUGK1March 2009

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Contents
Preface ........................................................................................................................................ 81 Features .............................................................................................................................. 92 Introduction ....................................................................................................................... 103 Overview ........................................................................................................................... 114 Standalone (SA) Mode ........................................................................................................ 124.1 Input Data Format ....................................................................................................... 134.2 Output Decision Data Format .......................................................................................... 164.3 Stopping Criteria ......................................................................................................... 164.4 Stopping Test Unit ....................................................................................................... 175 Shared-Processing (SP) Mode ............................................................................................. 185.1 Input Data Format ....................................................................................................... 225.2 Output Data Format ..................................................................................................... 246 Registers ........................................................................................................................... 256.1 Peripheral Identification Register (PID) ............................................................................... 276.2 TCP2 Input Configuration Register 0 (TCPIC0) ..................................................................... 286.3 TCP2 Input Configuration Register 1 (TCPIC1) ..................................................................... 296.4 TCP2 Input Configuration Register 2 (TCPIC2) ..................................................................... 296.5 TCP2 Input Configuration Register 3 (TCPIC3) ..................................................................... 306.6 TCP2 Input Configuration Register 4 (TCPIC4) ..................................................................... 316.7 TCP2 Input Configuration Register 5 (TCPIC5) ..................................................................... 326.8 Tail Symbols .............................................................................................................. 326.9 TCP2 Input Configuration Register 6 (TCPIC6) ..................................................................... 336.10 TCP2 Input Configuration Register 7 (TCPIC7) ..................................................................... 346.11 TCP2 Input Configuration Register 8 (TCPIC8) ..................................................................... 356.12 TCP2 Input Configuration Register 9 (TCPIC9) ..................................................................... 366.13 TCP2 Input Configuration Register 10 (TCPIC10) .................................................................. 376.14 TCP2 Input Configuration Register 11 (TCPIC11) .................................................................. 376.15 TCP2 Input Configuration Register 12 (TCPIC12) .................................................................. 396.16 TCP2 Input Configuration Register 13 (TCPIC13) .................................................................. 396.17 TCP2 Input Configuration Register 14 (TCPIC14) .................................................................. 406.18 TCP2 Input Configuration Register 15 (TCPIC15) .................................................................. 416.19 TCP2 Output Parameter Register 0 (TCPOUT0).................................................................... 426.20 TCP2 Output Parameter Register 1 (TCPOUT1).................................................................... 426.21 TCP2 Output Parameter Register 2 (TCPOUT2).................................................................... 436.22 TCP2 Execution Register (TCPEXE) ................................................................................. 436.23 TCP2 Endian Register (TCPEND) .................................................................................... 446.24 TCP2 Error Register (TCPERR) ....................................................................................... 456.25 TCP2 Status Register (TCPSTAT) .................................................................................... 476.26 TCP2 Emulation Register (TCPEMU)................................................................................. 497 Endianness ........................................................................................................................ 507.1 Data Memory for Systematic ........................................................................................... 50
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8 Architecture ....................................................................................................................... 598.1 Sub-block and Sliding Window Segmentation ....................................................................... 608.2 Subframe Segmentation (SP mode only) ............................................................................ 618.3 Reliability and Prolog Length Calculation ............................................................................ 628.4 Added Features .......................................................................................................... 639 Programming ..................................................................................................................... 649.1 EDMA3 Resources ...................................................................................................... 659.2 Programming Standalone (SA) Mode ................................................................................. 669.3 Programming Shared-Processing (SP) Mode ....................................................................... 7010 Output Parameters ............................................................................................................. 7411 Events Generation .............................................................................................................. 7412 Debug Mode: Pause After Each Map ..................................................................................... 7513 Errors and Status ............................................................................................................... 7513.1 Errors ...................................................................................................................... 7513.2 Status ..................................................................................................................... 77
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List of Figures
1 3GPP and IS2000 Turbo-Encoder Block Diagram ..................................................................... 102 3GPP and IS2000 Turbo-Decoder Block Diagram ..................................................................... 113 TCP2 Block Diagram ...................................................................................................... 124 Standalone (SA) Mode Block Diagram .................................................................................. 135 Systematic/Parity Data for Rates 1/2, 1/3, 1/4, 1/5, and 3/4 ......................................................... 146 EN = 1 (Little-Endian Mode) Rate = 1/2 ................................................................................. 147 EN = 0 (Big-Endian Mode) Rate = 1/2................................................................................... 148 EN = 1 (Little-Endian Mode) Rate = 1/3 ................................................................................. 149 EN = 0 (Big-Endian Mode) Rate = 1/3................................................................................... 1410 EN = 1 (Little-Endian Mode) Rate = 1/4 ................................................................................. 1411 EN = 0 (Big-Endian Mode) Rate = 1/4................................................................................... 1512 EN = 1 (Little-Endian Mode) Rate = 1/5 ................................................................................. 1513 EN = 0 (Big-Endian Mode) Rate = 1/5................................................................................... 1514 EN = 1 (Little-Endian Mode) Rate = 3/4 ................................................................................. 1515 Rate 3/4 EN = 0 (Big-Endian Mode) Rate = 3/4 ....................................................................... 1616 Shared-Processing (SP) Mode Block Diagram ......................................................................... 1917 Subframe Equations ....................................................................................................... 2018 Frame Process ............................................................................................................. 2019 TCP2 Shared Processing Block Diagram ............................................................................... 2220 Systematic/Parity Data for Rates 1/2, 1/3, 1/4, 1/5, and 3/4 ......................................................... 2221 EN = 1 (Little-Endian Mode) Rate = 1/2 ................................................................................. 2222 EN = 0 (Big-Endian Mode) Rate = 1/2................................................................................... 2223 EN = 1 (Little-Endian Mode) Rate = 1/3 ................................................................................. 2324 EN = 0 (Big-Endian Mode) Rate = 1/3................................................................................... 2325 EN = 1 (Little-Endian Mode) Rate = 1/4 ................................................................................. 2326 EN = 0 (Big-Endian Mode) Rate = 1/4................................................................................... 2327 EN = 1 (Little-Endian Mode) Rate = 1/5 ................................................................................. 2328 EN = 0 (Big-Endian Mode) Rate = 1/5................................................................................... 2429 EN = 1 (Little-Endian Mode) Rate = 3/4 ................................................................................. 2430 Rate 3/4 EN = 0 (Big-Endian Mode) Rate = 3/4 ....................................................................... 2431 A Priori Data ................................................................................................................ 2432 Peripheral Identification Register (PID) .................................................................................. 2733 TCP2 Input Configuration Register 0 (TCPIC0) ........................................................................ 2834 TCP2 Input Configuration Register 1 (TCPIC1) ........................................................................ 2935 TCP2 Input Configuration Register 2 (TCPIC2) ........................................................................ 2936 TCP2 Input Configuration Register 3 (TCPIC3) ........................................................................ 3037 TCP2 Input Configuration Register 4 (TCPIC4) ........................................................................ 3138 TCP2 Input Configuration Register 5 (TCPIC5) ........................................................................ 3239 TCP2 Input Configuration Register 6 (TCPIC6) ........................................................................ 3340 TCP2 Input Configuration Register 7 (TCPIC7) ........................................................................ 3441 TCP2 Input Configuration Register 8 (TCPIC8) ........................................................................ 3542 CP2 Input Configuration Register 9 (TCPIC9) ......................................................................... 3643 TCP2 Input Configuration Register 10 (TCPIC10) ..................................................................... 3744 TCP2 Input Configuration Register 11 (TCPIC11) ..................................................................... 3845 TCP2 Input Configuration Register 12 (TCPIC12) ..................................................................... 3946 TCP2 Input Configuration Register 13 (TCPIC13) ..................................................................... 3947 TCP2 Input Configuration Register 14 (TCPIC14) ..................................................................... 4048 TCP2 Input Configuration Register 15 (TCPIC15) ..................................................................... 4149 TCP2 Output Parameter Register 0 (TCPOUT0) ...................................................................... 4250 TCP2 Output Parameter Register 1 (TCPOUT1) ...................................................................... 4251 TCP2 Output Parameter Register 2 (TCPOUT2) ...................................................................... 4352 TCP2 Execution Register (TCPEXE) .................................................................................... 43
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53 TCP2 Endian Register (TCPEND) ....................................................................................... 4454 TCP2 Error Register (TCPERR).......................................................................................... 4555 TCP2 Status Register (TCPSTAT) ....................................................................................... 4756 TCP2 Emulation Register (TCPEMU) ................................................................................... 4957 Data Source - EDMA3 (Big Endian) ..................................................................................... 5058 Data Destination - Kernel (Little Endian) ................................................................................ 5059 Data Source - Kernel (Little Endian) ..................................................................................... 5060 Data Destination - EDMA3 (Big Endian) ................................................................................ 5061 Data Memory................................................................................................................ 5162 EN = 1 (Little-Endian Mode) Rate = 1/2 ................................................................................. 5163 EN = 0 (Big-Endian Mode) Rate = 1/2................................................................................... 5164 EN = 1 (Little-Endian Mode) Rate = 1/3 ................................................................................. 5165 EN = 0 (Big-Endian Mode) Rate = 1/3................................................................................... 5166 EN = 1 (Little-Endian Mode) Rate = 1/4 ................................................................................. 5167 EN = 0 (Big-Endian Mode) Rate = 1/4................................................................................... 5268 EN = 1 (Little-Endian Mode) Rate = 1/5 ................................................................................. 5269 EN = 0 (Big-Endian Mode) Rate = 1/5................................................................................... 5270 EN = 1 (Little-Endian Mode) Rate = 3/4 ................................................................................. 5271 EN = 0 (Big-Endian Mode) Rate = 3/4................................................................................... 5372 Source of Endianness Manager - Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 0) ............ 5373 Destination of Endianness Manager - Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 0) ....... 5374 Source of Endianness Manager - Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 1) ............ 5375 Destination of Endianness Manager - Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 1) ....... 5376 Source of Endianness Manager - Trellis Stage Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER= 0) ........................................................................................................................... 5377 Destination of Endianness Manager (OUT_ORDER = 0) ............................................................. 5478 Trellis Stage Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 1) ..................................... 5479 Trellis Stage Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 1) ..................................... 5480 Data Source = Kernel ...................................................................................................... 5481 Data Destination = EDMA3 EN = 0 (Big-Endian Mode) ............................................................... 5482 TCP_ENDIAN Register .................................................................................................... 5583 Interleaver Indexes in DSP Memory (ENDIAN_INTR = 1) ............................................................ 5684 Data Source - EDMA3 (ENDIAN_INTR = 1) ............................................................................ 5685 Data Destination - Kernel (ENDIAN_INTR = 1) ........................................................................ 5686 Interleaver Indexes in DSP Memory (ENDIAN_INTR = 0) ............................................................ 5687 Data Source - EDMA3 (ENDIAN_INTR = 0) ............................................................................ 5788 Data Destination - Kernel (ENDIAN_INTR = 0) ........................................................................ 5789 Extrinsic in DSP Memory (ENDIAN_EXTR = 1) ........................................................................ 5790 Data Source - Kernel (ENDIAN_EXTR = 1) ............................................................................ 5891 Data Destination - EDMA3 (ENDIAN_EXTR = 1) ...................................................................... 5892 Extrinsic in DSP Memory (ENDIAN_EXTR = 0) ........................................................................ 5993 Data Source - Kernel (ENDIAN_EXTR = 0) ............................................................................ 5994 Data Destination - EDMA3 (ENDIAN_EXTR = 0) ...................................................................... 5995 MAP Unit Block Diagram .................................................................................................. 6096 Sliding Windows and Sub-blocks Segmentation (Example with 5 Sub-blocks, frame length ≤20730) ......... 6197 Shared Processing Subframe Segmentation (Example with 5 Subframes) ........................................ 6298 Example R Formula ........................................................................................................ 6399 EDMA3 Parameters Structure ............................................................................................ 65100 TCP2 Events Generation in Standalone (SA) Mode................................................................... 74101 TCP2 Events Generation in Shared-Processing (SP) Mode ......................................................... 75
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List of Tables
1 Frame Sizes for Standalone (SA) Mode and Shared-Processing (SP) Mode ...................................... 122 Interleaver Data............................................................................................................. 163 TCP2 Registers ............................................................................................................. 254 TCP2 RAMs ................................................................................................................. 255 Peripheral Identification Register (PID) Field Descriptions ........................................................... 276 TCP2 Input Configuration Register 0 (TCPIC0) Field Descriptions .................................................. 287 TCP2 Input Configuration Register 1 (TCPIC1) Field Desccriptions ................................................ 298 TCP2 Input Configuration Register 2 (TCPIC2) Field Descriptions .................................................. 299 TCP2 Input Configuration Register 3 (TCPIC3) ........................................................................ 3010 TCP2 Input Configuration Register 4 (TCPIC4) Field Descriptions .................................................. 3111 TCP2 Input Configuration Register 5 (TCPIC5) Field Descriptions .................................................. 3212 CRC Examples ............................................................................................................. 3213 TCP2 Input Configuration Register 6 (TCPIC6) Field Descriptions .................................................. 3314 TCP2 Input Configuration Register 7 (TCPIC7) Field Descriptions .................................................. 3415 TCP2 Input Configuration Register 8 (TCPIC8) Field Descriptions .................................................. 3516 CP2 Input Configuration Register 9 (TCPIC9) Field Descriptions ................................................... 3617 TCP2 Input Configuration Register 10 (TCPIC10) Field Descriptions ............................................... 3718 TCP2 Input Configuration Register 11 (TCPIC11) Field Descriptions ............................................... 3819 TCP2 Input Configuration Register 12 (TCPIC12) Field Descriptions ............................................... 3920 TCP2 Input Configuration Register 13 (TCPIC13) Field Descriptions ............................................... 3921 TCP2 Input Configuration Register 14 (TCPIC14) Field Descriptions ............................................... 4022 TCP2 Input Configuration Register 15 (TCPIC15) Field Descriptions ............................................... 4123 Extrinsic Scale Registers .................................................................................................. 4124 TCP2 Output Parameter Register 0 (TCPOUT0) Field Descriptions ................................................ 4225 TCP2 Output Parameter Register 1 (TCPOUT1) Field Descriptions ................................................ 4226 TCP2 Output Parameter Register 2 (TCPOUT2) Field Descriptions ................................................ 4327 TCP2 Execution Register (TCPEXE) Field Descriptions .............................................................. 4328 TCP2 Endian Register (TCPEND) Field Descriptions ................................................................. 4429 TCP2 Error Register (TCPERR) Field Descriptions ................................................................... 4530 TCP2 Status Register (TCPSTAT) Field Descriptions ................................................................ 4731 TCP2 Emulation Register (TCPEMU) Field Descriptions ............................................................. 4932 Hard Decisions in DSP Memory .......................................................................................... 5433 TCP_ENDIAN Programming Register ................................................................................... 5534 Interleaver Data............................................................................................................. 5535 Interleaver Indexes in DSP Memory (ENDIAN_INTR = 1) ............................................................ 5536 Interleaver Indexes in DSP Memory (ENDIAN_INTR = 0) ............................................................ 5637 Extrinsic Data ............................................................................................................... 5738 Extrinsic in DSP Memory (ENDIAN_EXTR = 1) ........................................................................ 5739 Extrinsic in DSP Memory (ENDIAN_EXTR = 0) ........................................................................ 5940 Examples for NUM_BLOCK, NUM_SUBBLOCK, NUM_SW, and WIN_REL ...................................... 6141 Valid Re-Encode Symbols Used for Comparison ...................................................................... 6442 EDMA3 Parameters in Standalone (SA) Mode ......................................................................... 6543 EDMA3 Parameters in Shared Processing (SP) Mode ............................................................... 6544 Input Configuration Parameters Settings in Standalone (SA) Mode ................................................ 7045 Input Configuration Parameters Settings in Shared-Processing (SP) Mode ....................................... 74
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PrefaceSPRUGK1 – March 2009
Read This First
About This Manual
Channel decoding of high bit-rate data channels found in third-generation (3G) cellular standards requiresdecoding of turbo-encoded data. The turbo-decoder coprocessor (TCP2) in some of the digital signalprocessors (DSPs) of the TMS320C6000™ DSP family has been designed to perform this operation forIS2000 and 3GPP wireless standards. This document describes the operation and programming of theTCP2 for the TMS320C6457 DSPs.
Notational Conventions
This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.•The term "word" describes a 32-bit value. The term "halfword" describes a 16-bit value.
Related Documentation From Texas InstrumentsThe following documents describe the C6000™ devices and related support tools. Copies of thesedocuments are available on the Internet at www.ti.com. Tip: Enter the literature number in the search boxprovided at www.ti.com .
SPRU189 —TMS320C6000 DSP CPU and Instruction Set Reference Guide. Describes the CPUarchitecture, pipeline, instruction set, and interrupts for the TMS320C6000 digital signal processors(DSPs).
SPRU198 —TMS320C6000 Programmer's Guide. Describes ways to optimize C and assembly code forthe TMS320C6000™ DSPs and includes application program examples.
SPRU301 —TMS320C6000 Code Composer Studio Tutorial. Introduces the Code Composer Studio™integrated development environment and software tools.
SPRU321 —Code Composer Studio Application Programming Interface Reference Guide.Describes the Code Composer Studio™ application programming interface (API), which allows youto program custom plug-ins for Code Composer.
SPRU871 —TMS320C64x+ Megamodule Reference Guide. Describes the TMS320C64x+ digital signalprocessor (DSP) megamodule. Included is a discussion on the internal direct memory access(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidthmanagement, and the memory and cache.Trademarks
TMS320C6000, C6000, Code Composer Studio are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
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1 Features
User's GuideSPRUGK1 – March 2009
TMS320C6457 Turbo-Decoder Coprocessor 2
Channel decoding of high bit-rate data channels found in third-generation (3G) cellular standards requiresdecoding of turbo-encoded data. The turbo-decoder coprocessor (TCP2) in some of the digital signalprocessor (DSPs) of the TMS320C6000E DSP family has been designed to perform this operation forIS2000 and 3GPP wireless standards. This document describes the operation and programming of theTCP2.
The TCP2 provides:•High performance:
– Very-low-processing delay because of the highly paralleled architecture allowing 8 iterations of a 2Mbps 3GPP channel to be decoded in less than 1.2 ms and an IS2000 channel in less than 1.2 ms.– Processing delay can be further reduced by enabling a stopping criteria algorithm while achievingoptimal BER performance.– TCP2 and the DSP can run full speed in parallel.•System cost optimization:– Reduces board space and power consumption by performing on-chip turbo-decoding.– Communication between the DSP and the TCP2 is performed through a high performance DMAengine, the enhanced DMA (EDMA3).– TCP2 uses its own optimized memories, reducing system memory overhead and yielding higheroverall performance.
– Increased programmability.
– Power efficient and module power-saver capabilities.•High flexibility to cope with standard evolutions:– Accepts all IS2000, 3GPP rates, and polynomials.– Accepts any frame length from 40 (3GPP minimum frame size) up to 20730 for standaloneprocessing. Frame sizes greater than 20730 can be processed by breaking them up into smallersubframes for processing in shared processing mode.– Supports all interleaver combinations via interleaver table.– Frees-up DSP resources.•Improvements over TCP:– Standalone mode frame length increased from 5114 to 20730.– Code rates 1/2,1/3,1/4 and 1/5 (other rates via de-puncturing may be achieved).– Prolog reduction.– Cyclic redundancy check (CRC) stopping criteria.– Channel re-encoding.– Max-Log Maximum a Posteriori (MAP) option added to TCP2 (Max*-Log MAP still available).– Input sign programmable.
– Debug mode added to allow pausing after each MAP.– Decision ordering programmable as MSB first or LSB first.– Extrinsic scaling added for Max-Log MAP.
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2 Introduction
z−1 z−1 z−1
B
A
X
z−1 z−1 z−1
B’
A’
X’
Interleaver
Puncture
and
repetition
X
P1
P2
P3
Information
Switches in upper position for information bits and in lower position for tail bits
Introduction www.ti.com
Encoding is done as shown in Figure 1 . The 3GPP and IS2000 turbo encoders employ two recursive,systematic, convolutional (RSC) encoders connected in parallel, with an interleaver (the turbo interleaver)preceding the second recursive convolutional encoder. The two recursive convolutional codes are calledthe constituent encoders of the turbo code and have a constraint length K = 4.
Figure 1. 3GPP and IS2000 Turbo-Encoder Block Diagram
The outputs of the constituent encoders are punctured and repeated (F denotes the frame size, X and X'are systematic data, A, B, A', and B' are parity data, X', A', and B' are the interleaved versions of X, A, andB data):
•Data rate 1/2 (2 ×Fbits):X
0
A
0
X
1
A'
1
X
2
A
2
X
3
A'
3
…•Data rate 1/3 (3 ×Fbits):X
0
A
0
A'
0
X
1
A
1
A'
1
X
2
A
2
A'
2
X
3
A
3
A'
3
…•Date rate 1/4 (4 ×Fbits):X
0
A
0
B
0
B'
0
X
1
A
1
A'
1
B'
1
X
2
A
2
B
2
B'
2
X
3
A
3
A'
3
B'
3
…
For the tail bits, the sequence is:•IS2000 tail rate 1/2 and 3GPP tail rate 1/3: 12 bitsX
F
A
F
X
F+1
A
F+1
X
F+2
A
F+2
X'
F
A'
F
X'
F+1
A'
F+1
X'
F+2
A'
F+2•IS2000 tail rate 1/3: 18 bits (systematic bit repeated twice)X
F
X
F
A
F
X
F+1
X
F+1
A
F+1
X
F+2
X
F+2
A
F+2
X'
F
X'
F
A'
F
X'
F+1
X'
F+1
A'
F+1
X'
F+2
X'
F+2
A'
F+2•IS2000 tail rate 1/4: 24 bits (systematic bit repeated twice)X
F
X
F
A
F
B
F
X
F+1
X
F+1
A
F+1
B
F+1
X
F+2
X
F+2
A
F+2
B
F+2
X'
F
X'
F
A'
F
B'
F
X'
F+1
X'
F+1
A'
F+1
B'
F+1
X'
F+2
X'
F+2
A'
F+2
B'
F+2The decoding process is an iterative algorithm based on simple decoders individually matched to theRSC codes. A generic 3GPP and IS2000 turbo decoder is shown in Figure 2 .Each decoder sends a posteriori likelihood estimates of the decoded bits to the other decoder, and
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MAP1 MAP2
Received systematics
Interleave
Deinterleave
Apriori
Interleave
Apriori
Received systematics
Received parities
Received parities A’ & B ’ symbols
Hard
decisions
calculation
Decoded bits
X’ symbols
information
X symbols
A& B symbols
information
3 Overview
www.ti.com Overview
uses the corresponding estimates from the other decoder as a priori likelihood. The a priori informationis seen as beforehand knowledge, meaning that some messages are more likely to occur than others.A posteriori information adds to the a priori information the knowledge gained by the decoding.The uncoded information bits (corrupted by the noisy channel) are available to each decoder toinitialize the a priori likelihoods. The decoders use the Maximum a Posteriori (MAP) bitwise decodingalgorithm that requires the same number of states as the well known Viterbi algorithm. The turbodecoder iterates between the outputs of the two constituent decoders until it reaches satisfactoryconvergence. The final output is a hard-quantized version of the likelihood estimates of the decoders.
Figure 2. 3GPP and IS2000 Turbo-Decoder Block Diagram
The DSP controls the operation of the TCP2 (Figure 3 ) using memory-mapped registers. The DSPtypically sends and receives data using synchronized EDMA3 transfers through the 64-bit EDMA3 bus.The TCP2 sends two synchronization events to the EDMA3: a receive event (TCPREVT) and a transmitevent (TCPXEVT).
The processing unit can implement the Max*-Log-MAP or Max-Log-MAP approximations of the BCJRalgorithm and is selected with the E_MAX_STAR bit of the TCPIC3 register. (See L. R. Bahl, J. Cocke, F.Jelinek, and J. Raviv, "Optimal decoding of linear codes for minimizing symbol error rate",. IEEE Trans.Inform.Theory, vol. IT.20, pp. 284.287, Mar. 1974 and P. Robertson, E. Villebrun, and P. Hoeher, "Acomparison of optimal and sub-optimal MAP decoding algorithms operating in the log domain", in Proc.1996 IEEE Int. Conf. on Communications (Seattle, WA), June 1995, vol. 2, pp. 1009-1013.)
The TCP2 has two fundamental modes: standalone (SA) and shared processing (SP).
In SA mode, the TCP2 iterates a given number of times and outputs hard decisions. In SP mode, theTCP2 executes a single MAP decode and outputs extrinsic information (soft information). SA mode istypically used for frame sizes up to 20730. SP mode must be used for frames strictly larger than 20730.Table 1 describes which mode to use depending on the frame size.
The TCP2 input data corresponds to channel log-likelihood ratios scaled on 6 bits, while the TCP2 outputdata to hard-decisions (SA mode) or extrinsics (SP mode) scaled on 7 bits.
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32-bit configuration bus
64-bit EDMA3 bus
Turbo-decoder coprocessor (TCP2)
REVT/XEVT
generation
CPU
interrupt
generation
TCP2 control
EDMA3 I/F unit Memory block Processing unit
TCP2_INT TCPXEVT TCPREVT
4 Standalone (SA) Mode
Standalone (SA) Mode www.ti.com
Figure 3. TCP2 Block Diagram
Table 1. Frame Sizes for Standalone (SA) Mode andShared-Processing (SP) Mode
Frame Size (F) TCP2 Mode
40 ⇐F⇐20730 Standalone modeF > 20730 Shared processing
In standalone (SA) mode, the DSP sends the systematic and parity data, and the interleaver table. TheTCP2 then works independently of the DSP (standalone), iterates a defined maximum number of times,and outputs hard decision data. In this mode, minimum DSP processing is required. A stopping criteriacan be enabled to reduce the processing delay (see Section 4.3 ). Figure 4 shows the SA mode.
The standalone mode is used for frames in which the turbo interleaver length is less than or equal to20730. In this mode, the systematic, parities, extrinsics, and turbo interleaver data fit within the TCP2memory, and several iterations of decoding are run within the coprocessor without any DSP intervention.
The DSP sets up the EDMA3 to send the systematic and parity data, and the interleaver table (optional).The TCP2 then works independently of the DSP.
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Parity A
Parity A’
Parity B
Parity B’
Void input
I
I
I−1
Apriori 1
Apriori 2
Systematic
Stop?
(stopping
criterion
algo)
New
apriori
Previous apriori
Yes
Systematic
No
Slicer
Create hard
decisions
End
MAP
decoder
unit Extrinsic
saved
as new
apriori
Keep on iterations
Enable next log−map
by switching the
switches
4.1 Input Data Format
4.1.1 Systematic and Parity Data
www.ti.com Standalone (SA) Mode
One iteration of turbo decoding consists of 2 MAPs processing, the first MAP with the initial switch position(as shown in Figure 4 ), the second MAP with the other position of the switch. After each MAP, a stoppingtest can be performed based on the following methods. These tests are user configurable.•Comparing the extrinsic SNR estimate to a SNR threshold (user defined)•CRC pattern match•Max iterations
When starting a decoding, you must supply a maximum number of iterations and optionally an SNRthreshold ratio (or CRC) for the stopping test. If the stopping test is positive or the maximum number ofiterations is reached, the decoding stops, the hard decisions are computed (from both extrinsic andsystematic data), and then the coprocessor notifies EDMA3 that the processing is complete. In Figure 4 ,switch positions are for MAP0 and opposite positions are for MAP1.
Figure 4. Standalone (SA) Mode Block Diagram
Symbols (data) have to be quantized on 6 bits as (4,2) bit numbers, that is, SIII.FF (where S = sign bit, I =integer bit, F = fractional bit). Depending on the rate, Figure 6 through Figure 16 show how data must beorganized in the DSP memory to conform to a rate that is 1/5 of the input data stream, which TCP2requires. The base address must be double-word aligned. For big-endian configuration, see the TCP2endian register (TCPEND) in Section 6.22 . Also note that interleaved parities must be de-interleaved priorto being sent to TCP2.
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Standalone (SA) Mode www.ti.com
Figure 5. Systematic/Parity Data for Rates 1/2, 1/3, 1/4, 1/5, and 3/4
63:62 61:56 55:50 49:44 43:38 37:32 31:30 29:24 23:18 17:12 11:6 5:0RSVD SP9 SP8 SP7 SP6 SP5 RSVD SP4 SP3 SP2 SP1 SP0
Figure 6. EN = 1 (Little-Endian Mode) Rate = 1/2
Word WordN + 1 NSP9 SP8 SP7 SP6 SP5 SP4 SP3 SP3 SP3 SP00 A1' 0 0 X1 0 0 0 0 X0Word WordN + 3 N + 2SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP3 SP3 SP00 A3' 0 0 X3 0 0 0 0 X2
Figure 7. EN = 0 (Big-Endian Mode) Rate = 1/2
Word WordN N + 1SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP50 0 0 A0 X0 0 A1' 0 0 X1Word WordN + 2 N + 3SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP50 0 0 A2 X2 0 A3' 0 0 X3
Figure 8. EN = 1 (Little-Endian Mode) Rate = 1/3
Word WordN + 1 NSP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP00 A1' 0 A1 X1 0 A0' 0 A0 X0Word WordN + 3 N + 2SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP00 A3' 0 A3 X3 0 A2' 0 A2 X2
Figure 9. EN = 0 (Big-Endian Mode) Rate = 1/3
Word WordN N + 1SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP50 A0' 0 A0 X0 0 A1' 0 A1 X1Word WordN + 2 N + 3SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP50 A2' 0 A2 X2 0 A3' 0 A3 X3
Figure 10. EN = 1 (Little-Endian Mode) Rate = 1/4
Word WordN + 1 NSP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0B1' A1' 0 A1 X1 B0' 0 B0 A0 X0Word WordN + 3 N + 2SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0B3' A3' 0 A3 X3 B2' 0 B2 A2 X2
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www.ti.com Standalone (SA) Mode
Figure 11. EN = 0 (Big-Endian Mode) Rate = 1/4
Word WordN N + 1SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5B0' 0 B0 A0 X0 B1' A1' 0 A1 X1Word WordN + 2 N + 3SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5B2' 0 B2 A2 X2 B3' A3' 0 A3 X3
Figure 12. EN = 1 (Little-Endian Mode) Rate = 1/5
Word WordN + 1 NSP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0B1' A1' B1 A1 X1 B0' A0' B0 A0 X0Word WordN + 3 N + 2SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0B3' A3' B3' A3 X3 B2' A2' B2 A2 X2
Figure 13. EN = 0 (Big-Endian Mode) Rate = 1/5
Word WordN N + 1SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5B0' A0' B0 A0 X0 B1' A1' B1 A1 X1Word WordN + 2 N + 3SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5B2' A2 B2 A2 X2 B3' A3' B3 A3 X3
Figure 14. EN = 1 (Little-Endian Mode) Rate = 3/4
Word WordN + 1 NSP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP00 0 0 0 X1 0 0 0 A0 X0Word WordN + 3 N + 2SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP00 A3' 0 0 X3 0 0 0 0 X2Word WordN + 5 N + 4SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP00 0 0 0 X3 0 0 0 0 X2
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4.1.2 Interleaver Indexes
4.2 Output Decision Data Format
4.3 Stopping Criteria
Standalone (SA) Mode www.ti.com
Figure 15. Rate 3/4 EN = 0 (Big-Endian Mode) Rate = 3/4
Word WordN N + 1SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP50 0 0 A0 X0 0 0 0 0 X1Word WordN + 2 N + 3SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP50 0 0 0 X2 0 A3' 0 0 X3Word WordN + 4 N + 5SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP50 0 0 0 X4 0 0 0 0 X5
Each index is a 15-bit value being effectively saved as 16 bits right-justified. Given an index j, aninterleaver table t, and a data x, the interleaved data xis given as x' = x[ t(j)]. Table 2 shows how datamust be organized in the memory. The base address must be double-word aligned. For big-endianconfigurations, see the TCP2 endian register (TCPEND) in Section 6.22 .
Table 2. Interleaver Data
Little_big_endian Endian_intr Description (MSB to LSB)
0 0 1,0,3,2 ⇒3,2,1,0 (halfword)0 1 0,1,2,3 ⇒3,2,1,0 (halfword)1 0 Endianness manager has no effect3,2,1,0 ⇒3,2,1,0 (halfword)1 1 Endianness manager has no effect3,2,1,0 ⇒3,2,1,0 (halfword)
Hard decisions for TCP2 are 32-bit word-packed. The bit ordering within the 32-bit hard-decision word isprogrammable, such that the oldest bit can be either in the MSB or the LSB position. Their destinationstorage base address must be double-word aligned. Moreover, the buffer length must contain an evennumber of words.
The turbo decoder has an iterative structure, and the number of iterations that are performed for eachframe is either a deterministic number or it depends on a test performed on the turbo decoder output aftereach iteration. In the first case, you decide how many iterations should be performed prior to decoding aframe. In the second case, the turbo decoder performs tests after each iteration to determine whether theiterative process should continue. In this case, the boundary conditions are programmed (for example, theminimum and the maximum number of iterations that should be performed). The tests performed are theSNR stopping criterion and cyclic redundancy check (CRC) iterations passed.
This SNR stopping criterion on TCP2 can be used by setting the SNR threshold from 1 to 100 (0 disablesthe SNR threshold check). The stopping criteria is met and a TCPREVT is generated when the SNRthreshold is met, the minimum iterations have been processed, and sufficient CRC iterations have passed,if CRC is enabled. This indicates that decisions are ready for the EDMA3 to access.
Larger thresholds improve bit-error rate (BER) performance, but require more iterations. Smallerthresholds require fewer iterations, but may yield poorer BER performance. The actual number ofiterations run can be read from the output parameters.
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4.4 Stopping Test Unit
4.4.1 SNR Threshold Termination
4.4.2 CRC Termination
www.ti.com Standalone (SA) Mode
The CRC-based stopping criterion can be used by setting the CRC polynomial length (CRCLEN) and thenumber of CRC iterations required to pass CRCITERPASS. After each iteration, hard decisions arecomputed and a CRC is performed. The CRC polynomial is a programmable 32-bit number. To avoidsituations where a CRC test passes for a very noisy frame of data, the hard decisions need to pass theCRC test for a number of consecutive iterations, which is user-defined via the CRCITERPASS bit field.
Turbo decoders are iterative decoders. Each iteration consists of two MAP decodes except the lastiteration that executes only the first MAP decode. The turbo decoder can iterate up to 32 iterations. Thedecoder will continue to iterate until one of the following conditions occur: meet parameter conditions,CRC passed, or SNR threshold passed.
The stopping criteria algorithm generates the first two moments of the extrinsics, generates an SNR ratio,and compares the ratio with a threshold. If the calculated ratio exceeds the threshold, then the decoderhas found an optimum solution. The decoder can then stop executing any further iterations. Thecalculated SNR ratio is generated after each MAP process. The threshold is a user input and can rangefrom 0 to 100. Larger thresholds give better results but require more iterations. Smaller thresholds requirefewer iterations and give can give poorer results. Setting the threshold to 0 disables the stopping criteriaalgorithm.
The stopping criteria contains two parts. The first part executes on each extrinsic value. The sum of theextrinsics and the sum of the extrinsics squared are calculated. The second part is executed once at theend of each MAP block. The first moment is squared and multiplied by the sum of 1 plus the inverse of thethreshold. The second moment is multiplied by the number of symbols per frame. The two results arecompared. If the result is positive, then the stopping criteria has been met.
The turbo decoder will generate a block of extrinsics after each MAP decode. The SNR stopping criteriablock calculates the mean and the variance for this block. It will divide the two and compare the result withthe snr_threshold. If the result is greater then the snr_threshold for two consecutive MAP decodes, thenthe decoder will stop executing. The DSP sets the snr_threshold parameter. The SNR stopping criteriacan be turned off with a value of 0. Enabled values for snr_threshold range from 1 to 100. A value of 100gives the best BER performance at a cost of the most iterations executed, and a value of 1 gives theworst BER performance at a cost of the fewest iterations. Recommended setting for this parameter is 100.
A frame of data is sent through a CRC block which appends crc_length number of bits to the frame. Thisframe is encoded by the turbo encoder. The polynomial for the CRC check is defined with the crc_polyparameter. The turbo decoder will generate hard decision bits after each non-interleaved MAP decode.These bits are processed by the CRC block within the decoder. If the last crc_length bits match the CRCpattern, then the CRC check has passed. The turbo decoder will stop executing after CRCITERPASSnumber of consecutive CRC passes as programmed in TCPIC4.
The coefficients and the size of the CRC polynomial are programmable. The size of the polynomial isdefined with the parameter crc_length and can be set from 0 to 32 bits. A value of 0 disables the CRCcheck, values between 1 and 32 enable the CRC check. The CRC polynomial is defined with the crc_polyparameter. The CRC unit will not be enabled until the decoder iteration count is equal or greater than themin_iter parameter. The turbo decoder will generate hard decisions after each non-interleaved MAPdecode. These bits are processed by the CRC block within the decoder. If the last set of frame bits matchthe CRC pattern, then the CRC check has passed. The turbo decoder must pass a number of consecutiveiterations to terminate before max_iter. The number of consecutive iterations passed is defined with thecrc_iter_pass parameter. The crc_iter_pass parameter can be set from 0 to 31, a zero is equal to 1iteration. The dec_pass output parameter will be set to a 1 if the decoder terminated due to a passingCRC.
During the sub-block execution, up to 256 sets of data will be stored in a double buffered RAM whose sizeis 265x7x2. Two bits each will be stored for x0, p0, and p1. One bit is the sign bit and the other bit is set ifthe symbol is equal to a zero. These 6 bits will be used for re-encoding. The seventh bit will be the harddecision bit. This bit is the sign of the following summation: (x+a+w).
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4.4.3 Parameter Termination
4.4.3.1 Maximum Iterations
4.4.3.2 Minimum Iterations
5 Shared-Processing (SP) Mode
Shared-Processing (SP) Mode www.ti.com
The CRC will process one sub-block at time using the data stored from the previous sub-block. Thedecision bit will be used by a CRC block. After all sub-blocks have been processed, the CRC bits in theCRC block are checked and compared with the last crc_length bits of the frame. If they all match, then theCRC passes.
The parameters min_iter and max_iter need to be set prior to decode. The decoder must execute min_iternumber of iterations. This parameter can be set from 0 to 31. The decoder will stop executing when theiteration count equals max_iter. Max_iter can be set from 0 to 31 and must be equal or greater thanmin_iter. A zero for max is equal to 32 iterations. A zero for min is equal to 1 iteration.
Turbo decoders execute the MAP decoder twice per iteration. One execution is for non-interleaved dataand the other execution is for interleaved data. This parameter sets the maximum number of decoderiterations for each block of data. Valid sizes are 0 to 31. If either the CRC passed or the SNR stoppingcriteria threshold has been exceeded, then the decoder will stop early. The last iteration will only processthe MAP decoder for the non-interleaved data.
Turbo decoders execute the MAP decoder twice per iteration. One execution is for non-interleaved dataand the other execution is for interleaved data. This parameter sets the minimum number of decoderiterations for each block of data. Valid sizes are 0 to 31 and the min_iter must be less than or equal to themax_iter. The CRC unit will not be enabled until the decoder iteration count is equal or greater than themin_iter parameter. The turbo decoder will not process the CRC, re-encode, or write to the output RAMuntil the minimum number of iterations has been reached.
In shared-processing (SP) mode, the DSP sends systematic and parity data, and a priori data. The TCPperforms one single MAP decode and outputs extrinsic data. A priori data for MAP1 is obtained byde-interleaving the extrinsic data from the previous MAP2, and a priori data for MAP2 is obtained byinterleaving the extrinsics data from the previous MAP1. An overview of the SP mode is shown inFigure 16 . Note that the systematic and parity data to be sent to the TCP has to be demultiplexed from theoriginal flow described in Section 5.1 . The DSP must perform the input data demultiplexing, interleaving,deinterleaving operations, hard decision calculation, and any stopping criteria algorithm.
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MAP
decoder
unit
A for MAP 1
and A’ for MAP2
B for MAP1
and B’ for MAP2
(only rate 1/4)
X for MAP1
or X’ for MAP2
EXT1: extrinsics after MAP1
EXT2: extrinsics after MAP2 EXT1,2
www.ti.com Shared-Processing (SP) Mode
Figure 16. Shared-Processing (SP) Mode Block Diagram
The shared-processing mode allows the DSP/TCP2 system to support frames strictly larger than 20730.The DSP breaks the large frame into 2 or more smaller frames of 20480 or less. Each frame is called asubframe. The size of all the subframes (except the last subframe) must be divisible by 256. The DSPbreaks the large frame into several sub-frames following the process shown below. The first subframedoes not have a header section and its tail section is equal to the prolog size. The middle subframeheader and tail section sizes are each equal to the prolog size. The last subframe header size is equal tothe prolog size and the tail section is equal to the tail size. The prolog size must be integer divisible by 8.The sub-frames reliability portions are sequenced in order to create the full frame.1. The first subframe (required) will have a opmode of 1. The middle subframe(s) (optional) have aopmode of 2. The last subframe (required) will have a opmode of 3.2. The size of all the subframes (except the last subframe) must be integer divisible by 256 and Max subframe size = 20480 = 80*256.3. The first and middle subframes should have the same size. The last subframe should be approximatelythe same size as the other subframes.4. The last subframe size must be at least 129.
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NumSubframe +CEILǒSizeBlock
SizeMAX_SubframeǓ
SizeSubframe +CEILǒSizeBlock
256 NumSubframeǓ 256
whileǒSizeBlock uSizeMAX_Subsystem Ǔ{
SizeBlock +SizeBlock *SizeSubframe
if(SizeBlock u128)
}
SizeLast_Subframe +SizeBlock
if(SizeBlock v128)
NumSubframe +NumSubframe *1
SizeLast_Subframe +SizeBlock )SizeMAX_Subframe
{
}
}
1st sub−frame:
Prolog header is transferred by EDMA3, but not used by the TCP:
The TCP EDMA3 I/F unit reads and counts this data but does not
store it into the coprocessor memory.
Actually, the TCP is using the frame header symbols and does not
need any header prolog computation.
Last sub−frame
A full sub−frame including the header and tail prolog is transferred by EDMA3
but the totality is not used by the TCP.
For the useless sub−frame part, the TCP EDMA3 I/F unit reads and counts it
Actually, the TCP is using the frame tail symbol and does not need any
tail prolog computation.
Full frame (frame length >20730)
1st sub−frame Middle sub−frame Middle sub−frame Last
sub−frame
but does not store it into the coprocessor memory.
Shared-Processing (SP) Mode www.ti.com
Figure 17. Subframe Equations
Figure 18. Frame Process
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