Texas Instruments TMS320C6000 DSP Product manual

TMS320C6000 Instruction Set Simulator
Technical Reference Manual
Literature Number: SPRU600I
April 2007

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Contents
Preface ............................................................................................................................... 7
1 Introduction to the TMS320C6000 Simulator .................................................................. 91.1 Features ............................................................................................................ 101.2 Supported Processors and Simulator Configurations ........................................................ 101.3 Considerations for Choosing a Simulator ...................................................................... 111.4 Supported Hardware Resources ................................................................................ 111.4.1 CPU ........................................................................................................ 121.4.2 Memory .................................................................................................... 121.4.3 Peripherals ................................................................................................ 12
2 Supported Simulation Features .................................................................................. 152.1 External Event and Data Simulation ............................................................................ 162.1.1 Pin Connect .............................................................................................. 162.1.2 Port Connect .............................................................................................. 202.2 Reserved Memory Access Detection ........................................................................... 222.2.1 Supported Configurations ............................................................................... 222.2.2 Configuration Options .................................................................................... 222.2.3 Error Reporting Format .................................................................................. 222.2.4 Limitations ................................................................................................. 232.3 CPU Resource Conflict Detection ............................................................................... 232.3.1 Supported Configurations ............................................................................... 232.3.2 Types of Conflict Detected .............................................................................. 242.3.3 Types of Conflict Not Detected ......................................................................... 242.3.4 Configuration Options .................................................................................... 242.3.5 Error Reporting Format .................................................................................. 242.4 Simulator Analysis................................................................................................. 252.5 RTDX ............................................................................................................... 252.6 DSP/BIOS .......................................................................................................... 252.7 Bootload ............................................................................................................ 252.8 Application Memory Usage Detection .......................................................................... 252.9 EMIF Clock Configuration ........................................................................................ 252.10 Rewind .............................................................................................................. 262.11 Watchpoint ......................................................................................................... 262.12 Compiled Simulation .............................................................................................. 262.13 Interrupt Latency Detection ...................................................................................... 27
3 Detailed Capabilities of Individual Configurations ........................................................ 293.1 C62x/C64x/C67x/C672x/C64x+ CPU Cycle Accurate Simulators .......................................... 303.2 C6416/C6713/C6412/DM642 Device Functional Simulators ................................................ 303.2.1 Supported Features ...................................................................................... 303.2.2 Known Limitations ........................................................................................ 313.3 C6201/C6202/C6203/C6204/C6205/C6701 Device Simulators ............................................. 323.3.1 Supported Features ...................................................................................... 323.3.2 Known Limitations ........................................................................................ 323.4 C6211/C6711/C6712/C6713 Device Cycle Accurate Simulators ........................................... 32
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3.4.1 Supported Features ...................................................................................... 333.4.2 Known Limitations ........................................................................................ 333.5 C6411/C6412/C6414/C6415/C6416/DM642 Device Cycle Accurate Simulators ......................... 333.5.1 Supported Features ...................................................................................... 333.5.2 Known Limitations ........................................................................................ 333.6 DM6443/DM6446/C6455/TCI6482 Device Cycle Accurate Simulators .................................... 343.6.1 Supported Features ...................................................................................... 343.6.2 Known Limitations ........................................................................................ 34
4 Configuring the Simulator ......................................................................................... 354.1 Setting the Resource Conflict Detection Mode ................................................................ 364.2 Setting the Reserved Memory Access Detection Mode ...................................................... 364.3 Setting the Bootload .............................................................................................. 374.3.1 Bootload in C6x0x Device Simulators ................................................................. 374.3.2 Bootload in C64x Device Cycle Accurate/Device Functional Simulators ......................... 374.3.3 Bootload in C64x+ Device Cycle Accurate Simulators .............................................. 374.4 Setting the EMIF and CPU Clocks .............................................................................. 384.5 Enabling the Rewind Feature .................................................................................... 384.6 Setting Up the McBSP XBAR .................................................................................... 384.6.1 How to Write an XBAR File ............................................................................. 394.6.2 Format of the Configuration File to be Picked Up .................................................... 404.7 Setting Up the McASP XBAR .................................................................................... 404.7.1 Format of the Configuration File to be Picked Up .................................................... 414.8 Setting the Maximum Memory Usage Limit .................................................................... 414.9 File Format for Pin Connect ...................................................................................... 414.9.1 Setting Up the Input File ................................................................................. 414.9.2 Absolute Clock Cycle .................................................................................... 424.9.3 Relative Clock Cycle ..................................................................................... 424.9.4 Repetition of Patterns for a Specified Number of Times ............................................ 424.9.5 Repetition to the End of Simulation (EOS) ............................................................ 424.10 File Format for Port Connect..................................................................................... 434.11 Base Configuration File ........................................................................................... 43
5 Performance Numbers .............................................................................................. 45
6 Cycle Accuracy ........................................................................................................ 476.1 C6000 Simulators Benchmarking ............................................................................... 486.2 Notes on Cycle Accuracy ........................................................................................ 49
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List of Tables
1-1 Processors Supported by the C6000 Simulator ........................................................................ 101-2 TMS320C6000 CPU Cycle Accurate Simulator Configurations ...................................................... 121-3 TMS320C6201, C6202, C6203, C6204, C6205, and C6701 Simulators ........................................... 121-4 TMS320C6411, C6412, C6414, C6415, C6416, and DM642 Device Cycle Accurate; C6412, C6416 andDM642 Functional Simulators ............................................................................................ 121-5 TMS320C6211, C6711, C6712, and C6713 Device Cycle Accurate, and C6713 Device FunctionalSimulators ................................................................................................................... 132-1 Available Memory Ranges for Port Connect for TMS320C6000 Devices .......................................... 162-2 Available Pins for Configuration of the TMS320C6713 Device ...................................................... 172-3 Available Pins for Configuration of TMS320C6202, C6203, C6412, C6414, C6415, C6416 and DM642Devices ...................................................................................................................... 182-4 Available Pins for Configuration of TMS320C64x, C62x, C67x, and C672x CPU Cycle Accurate Simulators 182-5 Available Pins for Configuration of TMS320C6412, C6416, C6713, and DM642 Device FunctionalSimulators ................................................................................................................... 192-6 Available Pins for Configuration of DM4663, DM6446, TCI6482, and TMX320C6455 Device Simulators ..... 192-7 Available Memory Ranges for Port Connect for TMS320C6000 Devices .......................................... 202-8 Resources That Can Appear in the Resource Conflict Error Message ............................................. 242-9 Compiled Simulator Configuration ....................................................................................... 263-1 Timer Memory Map Details in CPU/MegaModule Simulators ........................................................ 304-1 XBAR File Pin Names ..................................................................................................... 395-1 Performance Numbers of the C6000 Simulator ........................................................................ 456-1 Benchmarking Data for C6000 Simulators .............................................................................. 48
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Preface
SPRU600I – April 2007
Read This First
About This Manual
This manual provides the following information:•Names the TMS320C6000™ ( C6000™) digital signal processors (DSPs) that are supported byconfigurations of the TMS320C6000 Instruction Set Simulator•Lists which modules and pins of each device are modeled•Describes capabilities and limitations of the simulator•Explains how to configure the simulator•Provides some bench marking data on cycle accuracy
Notational Conventions
This document uses the following conventions:•Program examples are shown in a special typeface.•In syntax descriptions, key words or symbols are shown in bold and variables are shown in italics.Portions of a syntax that are in bold should be entered as shown; portions of a syntax that are in italicsdescribe the type of information that should be entered.•Square brackets ([and]) identify an optional parameter. If you use an optional parameter, you specifythe information within the brackets. Unless the square brackets are in a bold typeface, do not enter thebrackets themselves.•Braces ( { and } ) indicate that you must choose one of the parameters within the braces; you do notenter the braces themselves.•The pipe symbol ( | ) represents a logical OR.
Related Documentation From Texas InstrumentsTMS320C62x DSP CPU and Instruction Set Reference Guide (SPRU731 ) describes the architecture,pipeline, instruction set, and interrupts for the TMS320C62x DSPs.
TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (SPRU732 ) describes thearchitecture, pipeline, instruction set, and interrupts for the TMS320C64x/64x+ DSPs.TMS320C67x/C67x+ DSP CPU and Instruction Set Reference Guide (SPRU733 ) describes thearchitecture, pipeline, instruction set, and interrupts for the TMS320C67x/67x+ DSPs.
TMS320C6000 Peripherals Reference Guide (SPRU190 ) describes common peripherals available onthe TMS320C6000 DSPs. This book includes information on the internal data and program memories, theexternal memory interface (EMIF), the host port, serial ports, direct memory access (DMA), enhanceddirect memory access (EDMA), expansion bus (XBUS), clocking and phase-locked loop (PLL), and thepower-down modes.
TMS320C6000 Code Composer Studio Online Help is accessible through the Code Composer Studio™Integrated Development Environment (IDE).Trademarks
TMS320C6000, C6000, Code Composer Studio, TMS320C62x, TMS320C64x, TMS320C672x,TMS320C67x, C62x, C64x, C672x, C67x, RTDX, DSP/BIOS are trademarks of Texas Instruments.
Intel, Pentium are registered trademarks of Intel Corporation or its subsidiaries in the United States andother countries.
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Chapter 1SPRU600I – April 2007
Introduction to the TMS320C6000 Simulator
The TMS320C6000™ Instruction Set Simulator, available within the Code ComposerStudio™ Integrated Development Environment (IDE) for TMS320C6000, simulates theTMS320C62x™, TMS320C64x™, TMS320C64x+™, TMS320C672x™, andTMS320C67x™ generations of devices. This chapter lists the TMS320C6000 devicessupported by the simulator and provides information to help in the selection of the bestsimulator configuration.
Topic .................................................................................................. Page
1.1 Features ................................................................................... 101.2 Supported Processors and Simulator Configurations .................... 101.3 Considerations for Choosing a Simulator .................................... 111.4 Supported Hardware Resources ................................................. 11
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1.1 Features
1.2 Supported Processors and Simulator Configurations
Features
The C6000™ simulators support the following features:•TMS320C6000 CPU full instruction set architecture execution•Support for C62x™, C64x™, C64x+™, C672x™, and C67x™. Support for all devices is based onthese cores.•Port Connect, which also supports external peripheral simulation•Pin Connect, which also supports external interrupt simulation•Analysis events support for debug and analysis•RTDX™ support•DSP/BIOS™ real-time analysis support•CPU resource conflict detection•Rewind support•Watchpoint support•Interrupt latency detection•Compiled simulation
Table 1-1 lists the devices supported by the C6000 Instruction Set Simulator with the correspondingconfiguration to be selected under the Factory Board menu of Code Composer Studio Setup.
Table 1-1. Processors Supported by the C6000 Simulator
Processor Code Composer Studio IDE Import Configuration
(1)
CPU Modeled
TMS320C62x C62xx CPU Cycle Accurate Simulator TMS320C62xTMS320C64x C64xx CPU Cycle Accurate Simulator TMS320C64xTMS320C67x C67xx CPU Cycle Accurate Simulator TMS320C67xTMS320C6211 C6211 Device Cycle Accurate Simulator TMS320C62xTMS320C6411 C6411 Device Cycle Accurate Simulator TMS320C64xTMS320C6412
(2)
C6412 Device Cycle Accurate Simulator TMS320C64xTMS320C6414 C6414 Device Cycle Accurate Simulator TMS320C64xTMS320C6415 C6415 Device Cycle Accurate Simulator TMS320C64xTMS320C6416
(2)
C6416 Device Cycle Accurate Simulator TMS320C64xTMS320C6711 C6711 Device Cycle Accurate Simulator TMS320C67xTMS320C6712 C6712 Device Cycle Accurate Simulator TMS320C67xTMS320C6713
(2)
C6713 Device Cycle Accurate Simulator TMS320C67xTMS320DM642
(2)
DM642 Device Cycle Accurate Simulator TMS320C64xTMS320C6201 C6201 Device Simulator
(3)
TMS320C62xTMS320C6202 C6202 Device Simulator
(3)
TMS320C62xTMS320C6203 C6203 Device Simulator
(3)
TMS320C62x(1)
Big Endian and Little Endian (default) configurations are available in the product.(2)
Device Functional Simulators are also available for these Device Cycle Accurate Simulators and can be used by changing theSimulator Type entry in the Code Composer Studio Setup processor properties window from Cycle Accurate to Functional.(3)
Map 0 and Map 1 (default) configurations are available.
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1.3 Considerations for Choosing a Simulator
1.4 Supported Hardware Resources
Considerations for Choosing a Simulator
Table 1-1. Processors Supported by the C6000 Simulator (continued)
Processor Code Composer Studio IDE Import Configuration
(1)
CPU Modeled
TMS320C6204 C6204 Device Simulator
(3)
TMS320C62xTMS320C6205 C6205 Device Simulator
(3)
TMS320C62xTMS320C6701 C6701 Device Simulator
(3)
TMS320C67xC6455 C6455 Device Cycle Accurate Simulator TMS230C64x+TCI6482 TCI6482 Device Cycle Accurate Simulator TMS230C64x+DM6446 DM6446 Device Cycle Accurate Simulator
(4)
TMS230C64x+DM6443 DM6443 Device Cycle Accurate Simulator
(4)
TMS230C64x+TMS230C64x+ TMS230C64x+ Cycle Accurate Simulator TMS230C64x+TMS230C64x+ C64x+ CPU Cycle Accurate Simulator TMS230C64x+TMS320C672x C672x CPU Cycle Accurate Simulator TMS230C672x
Note: Multiple C6000 simulator configurations cannot be imported in Code ComposerStudio Setup.
(4)
Only Little Endian configurations are available in the product for this device. Models the DSP subsystems, EDMA v3, and DDR2EMIF only. Does not model the ARM subsystem.
The different simulators provide a tradeoff between the functionality modeled, cycle accuracy of thesimulation, and simulation performance. Different configurations can be selected based on the needs ofthe application, in terms of the target functionality needed and the levels of cycle accuracy required. Youcan choose CPU Cycle Accurate Simulators or Device Cycle Accurate Simulators from the Factory Boardsmenu in Code Composer Studio Setup. For C6x1x simulators, you can create simulator configurations forDevice Functional Simulators by changing the Simulator Type entry in the Code Composer Studio Setupprocessor properties window from Cycle Accurate to Functional.
The CPU cycle-accurate simulator configurations can be selected if your primary interest is in optimizingcore algorithms. Here, you are concerned with the accuracy of the core and do not need full devicesimulation. Any accesses outside the core will be handled by a flat memory; the cycles measured will notaccount for any memory access latencies.
The device functional simulator configurations model the functionality of some of the key peripherals, withminimal impact on simulator performance. The peripherals in these simulators are modeled functionally tosupport the programmer view; they are not cycle-accurate. These configurations can be used when youare interested in the features of the device that are supported in the functional simulator but not present inthe core simulator, and when cycle accuracy is not important.
For example, the C6713 Device Functional Simulator can be used for application development wherecycle accuracy is not needed. The C6713 Device Functional Simulator runs faster than the C6713 DeviceCycle Accurate Simulator.
The device cycle-accurate simulator configurations model most of the peripherals of the devices. Theperipherals are cycle accurate, as in the silicon. These simulators can be used to get an indication of thecycle behavior of an application. For more details on the accuracy of a specific simulator configuration,see Chapter 3 .
The following sections provide a concise overview of the supported hardware resources for each of thesimulator configurations. For more detailed information on simulator configurations, see Chapter 3 .
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1.4.1 CPU
1.4.2 Memory
1.4.3 Peripherals
Supported Hardware Resources
The CPU model is cycle accurate. Cycle effects are modeled.
For each of the device simulators and device cycle-accurate simulators, the cache and internal memorymodels match the cache and memory architecture specifications described in the TMS320C6000Peripherals Reference Guide (SPRU190 ). They support standard cache behavior such as: LRU linereplacement, direct mapping, set associativity, cache protocols for hit/miss service, snoops, and victims.The allocation policies (allocate on read miss, write-back on write miss, etc.) are also modeled to matchthe device specifications. A flat memory model is hooked up to the EMIF in order to allow for externalmemory accesses.
For the CPU cycle-accurate simulators and device functional simulators, the whole memory range ismodeled as a flat memory.
Note: Setting up memory maps using either the GUI or GEL scripts is not supported.
The following tables show the peripherals supported under each simulator configuration. For moreinformation on these peripherals, see the TMS320C6000 Peripherals Reference Guide (SPRU190 ).
Table 1-2. TMS320C6000 CPU Cycle Accurate Simulator Configurations
C62x C64x C64x+ C672x C67x
CPU Yes Yes Yes Yes YesFlat Memory Yes Yes Yes Yes YesTimer Yes Yes Yes Yes Yes
Table 1-3. TMS320C6201, C6202, C6203, C6204, C6205, and C6701 Simulators
C6201 C6202 C6203 C6204 C6205 C6701
CPU Yes Yes Yes Yes Yes YesInternal Memory/Cache Yes Yes Yes Yes Yes YesModel
DMA Yes Yes Yes
(1)
Yes
(1)
Yes
(1)
YesEMIF Yes Yes Yes Yes Yes YesInterrupt Selector Yes Yes Yes Yes Yes YesMcBSP Yes Yes Yes Yes Yes YesTimer Yes Yes Yes Yes Yes YesGPIO No No No No No NoHPI/XBUS/PCI No No No No No No
(1)
The DMA functionality modeled on this device is the same as that of the C6202 simulator. The enhancements have not beenmodeled.
Table 1-4. TMS320C6411, C6412, C6414, C6415, C6416, and DM642 Device Cycle Accurate; C6412,C6416 and DM642 Functional Simulators
C6411 C6412 C6414 C6415 C6416 DM642 C6412 C6416 DM642FUNC FUNC FUNC
CPU Yes Yes Yes Yes Yes Yes Yes Yes YesInternal Memory/ Yes Yes Yes Yes Yes Yes Yes Yes YesCache Model
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Supported Hardware Resources
Table 1-4. TMS320C6411, C6412, C6414, C6415, C6416, and DM642 Device Cycle Accurate; C6412,C6416 and DM642 Functional Simulators (continued)
C6411 C6412 C6414 C6415 C6416 DM642 C6412 C6416 DM642FUNC FUNC FUNC
QDMA Yes Yes Yes Yes Yes Yes Yes Yes YesEDMA Yes Yes Yes Yes Yes Yes Yes Yes YesEMIF Yes Yes Yes Yes Yes Yes Yes Yes YesInterrupt Selector Yes Yes Yes Yes Yes Yes Yes Yes YesMcBSP Yes Yes Yes Yes Yes Yes Yes Yes YesTimer Yes Yes Yes Yes Yes Yes Yes Yes YesGPIO No No No No No No No No NoHPI No No No No No No No No NoTCP/VCP N/A
(1)
N/A
(1)
N/A
(1)
N/A
(1)
Yes N/A
(1)
N/A
(1)
No N/A
(1)
Utopia N/A
(1)
N/A
(1)
N/A
(1)
No No N/A
(1)
N/A
(1)
No N/A
(1)
PCI No No No No No No No No NoMcASP N/A
(1)
N/A
(1)
N/A
(1)
N/A
(1)
N/A
(1)
Yes N/A
(1)
N/A
(1)
NoVideoport N/A
(1)
N/A
(1)
N/A
(1)
N/A
(1)
N/A
(1)
No N/A
(1)
N/A
(1)
No(1)
N/A - Does not exist in the hardware.
Table 1-5. TMS320C6211, C6711, C6712, and C6713 Device Cycle Accurate,and C6713 Device Functional Simulators
C6211 C6711 C6712 C6713 C6713 FUNC
CPU Yes Yes Yes Yes YesInternal Memory/Cache Yes Yes Yes Yes YesModel
QDMA Yes Yes Yes Yes YesEDMA Yes Yes Yes Yes YesEMIF Yes Yes Yes Yes YesInterrupt Selector Yes Yes Yes Yes YesMcBSP Yes Yes Yes Yes YesMcASP No No No Yes NoTimer Yes Yes Yes Yes YesGPIO No No No No NoHPI No No No No No
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Chapter 2SPRU600I – April 2007
Supported Simulation Features
This chapter provides a concise overview of the supported simulation features for eachof the simulator configurations. For more detailed information on each configuration,see Chapter 3 .
Topic .................................................................................................. Page
2.1 External Event and Data Simulation ............................................ 162.2 Reserved Memory Access Detection ........................................... 222.3 CPU Resource Conflict Detection ................................................ 232.4 Simulator Analysis .................................................................... 252.5 RTDX ....................................................................................... 252.6 DSP/BIOS ................................................................................. 252.7 Bootload .................................................................................. 252.8 Application Memory Usage Detection .......................................... 252.9 EMIF Clock Configuration .......................................................... 252.10 Rewind .................................................................................... 262.11 Watchpoint ............................................................................... 262.12 Compiled Simulation ................................................................. 262.13 Interrupt Latency Detection ........................................................ 27
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2.1 External Event and Data Simulation
2.1.1 Pin Connect
External Event and Data Simulation
In real hardware, the DSP interacts with many external entities. The simulator provides features tosimulate these interactions. The interactions between the simulator and these external entities fall into thefollowing two categories:•Control Signals trigger activities to the simulator (such as interrupts, serial port clocks, and serial portsynchronization events).•Data Values are part of an interaction between the simulator and an external entity (such as read andwrite to peripheral registers as a part of I/O memory, and serial port data).
For example, the serial port of the DSP in an audio device is connected to A/D and D/A converters or to acodec. The interaction between the DSP and the audio device happens through transfer of asynchronization signal to start a sample, as well as the sample data itself. Here, the synchronization signalfalls into the Control Signals category and the sample data falls into the Data Values category.
The simulator provides the Pin Connect and Port Connect features for the simulation of these two types ofinteractions, respectively.
The Pin Connect tool allows you to simulate and monitor signals from external interrupts. For taking inexternal interrupts/triggers, some pins are simulated in the TMS320C6000 devices. Any file with thespecified format can be connected to those pins.
The pins being simulated are of two types: pulse and waveform. Pulse pins are sensitive to rising edgesand Waveform pins are sensitive to both rising and falling edges. For example, CPU interrupt pins aresensitive to rising edges, while the clock input pins of the serial port (CLKX, CLKR) of the TMS320C6000devices are sensitive to rising and falling edges. See the following tables for details on the various pinssupported for the different simulator configurations.
Table 2-1. Available Memory Ranges for Port Connect for TMS320C6000Devices
Pin Description Type
NMI Non-maskable interrupt PulseINT4 General purpose external interrupt pin PulseINT5 General purpose external interrupt pin PulseINT6 General purpose external interrupt pin PulseINT7 General purpose external interrupt pin PulseTINP0 Timer0 input pin WaveformTINP1 Timer1 input pin WaveformFSX0 Transmit frame synchronization pin for McBSP0 WaveformFSR0 Receive frame synchronization pin for McBSP0 WaveformCLKX0 Transmit clock pin for McBSP0 WaveformCLKR0 Receive clock pin for McBSP0 WaveformCLKS0 External clock input for McBSP0 WaveformFSX1 Transmit frame synchronization pin for McBSP1 WaveformFSR1 Receive frame synchronization pin for McBSP1 WaveformCLKX1 Transmit clock pin for McBSP1 WaveformCLKR1 Receive clock pin for McBSP1 WaveformCLKS1 External clock input for McBSP1 Waveform
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External Event and Data Simulation
Table 2-2. Available Pins for Configuration of the TMS320C6713 Device
Pin Description Type
NMI Non-maskable interrupt PulseINT4 General purpose external interrupt pin PulseINT5 General purpose external interrupt pin PulseINT6 General purpose external interrupt pin PulseINT7 General purpose external interrupt pin PulseTINP0 Timer0 input pin WaveformTINP1 Timer1 input pin WaveformFSX0 Transmit frame synchronization pin for McBSP0 WaveformFSR0 Receive frame synchronization pin for McBSP0 WaveformCLKX0 Transmit clock pin for McBSP0 WaveformCLKR0 Receive clock pin for McBSP0 WaveformCLKS0 External clock input for McBSP0 WaveformFSX1 Transmit frame synchronization pin for McBSP1 WaveformFSR1 Receive frame synchronization pin for McBSP1 WaveformCLKX1 Transmit clock pin for McBSP1 WaveformCLKR1 Receive clock pin for McBSP1 WaveformCLKS1 External clock input for McBSP1 WaveformACLKX0 Clock pin for transmit section of McASP0 PulseACLKR0 Clock pin for receive section of McASP0 PulseAHCLKX0 Clock pin at higher frequencies for transmit section of PulseMcASP0AHCLKR0 Clock pin at higher frequencies for receive section of PulseMcASP0AFSX0 Frame sync pin for transmit section of McASP0 PulseAFSR0 Frame sync pin for receive section of McASP0 PulseACLKX1 Clock pin for transmit section of McASP1 PulseACLKR1 Clock pin for receive section of McASP1 PulseAHCLKX1 Clock pin at higher frequencies for transmit section of PulseMcASP1AHCLKR1 Clock pin at higher frequencies for receive section of PulseMcASP1AFSX1 Frame sync pin for transmit section of McASP1 PulseAFSR1 Frame sync pin for receive section of McASP1 Pulse
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External Event and Data Simulation
Table 2-3. Available Pins for Configuration of TMS320C6202, C6203, C6412,C6414, C6415, C6416 and DM642 Devices
Pin Description Type
NMI Non-maskable interrupt PulseINT4 General purpose external interrupt pin PulseINT5 General purpose external interrupt pin PulseINT6 General purpose external interrupt pin PulseINT7 General purpose external interrupt pin PulseTINP0
(1)
Timer0 input pin WaveformTINP1
(1)
Timer1 input pin WaveformFSX0 Transmit frame synchronization pin for McBSP0 WaveformFSR0 Receive frame synchronization pin for McBSP0 WaveformCLKX0 Transmit clock pin for McBSP0 WaveformCLKR0 Receive clock pin for McBSP0 WaveformCLKS0 External clock input for McBSP0 WaveformFSX1 Transmit frame synchronization pin for McBSP1 WaveformFSR1 Receive frame synchronization pin for McBSP1 WaveformCLKX1 Transmit clock pin for McBSP1 WaveformCLKR1 Receive clock pin for McBSP1 WaveformCLKS1 External clock input for McBSP1 WaveformFSX2
(2)
Transmit frame synchronization pin for McBSP2 WaveformFSR2
(2)
Receive frame synchronization pin for McBSP2 WaveformCLKX2
(2)
Transmit clock pin for McBSP2 WaveformCLKR2
(2)
Receive clock pin for McBSP2 WaveformCLKS2
(2)
External clock input for McBSP2 WaveformACLKR0
(3)
Clock pin for receive section of McASP0 PulseACLKX0
(3)
Clock pin for transmit section of McASP0 PulseAHCLKR0
(3)
Clock pin at higher frequencies for receive section of PulseMcASP0AHCLKX0
(3)
Clock pin at higher frequencies for transmit section of PulseMcASP0AFSR0
(3)
Frame sync pin for receive section of McASP0 PulseAFSX0
(3)
Frame sync pin for transmit section of McASP0 Pulse(1)
This pin is applicable only to the C6202 and C6203 Device Simulators.(2)
This pin is not applicable to the DM642 Device Cycle Accurate Simulator, as it has only twoMcBSPs.
(3)
This pin is applicable only to the DM642 Device Cycle Accurate Simulator.
Table 2-4. Available Pins for Configuration of TMS320C64x, C62x, C67x, andC672xCPU Cycle Accurate Simulators
Pin Description Type
NMI Non-maskable interrupt PulseINT4 General purpose external interrupt pin PulseINT5 General purpose external interrupt pin PulseINT6 General purpose external interrupt pin PulseINT7 General purpose external interrupt pin PulseINT8
(1)
General purpose external interrupt pin PulseINT9
(1)
General purpose external interrupt pin PulseINT10
(1)
General purpose external interrupt pin Pulse
(1)
This pin is applicable only to the C64x+ CPU simulator.
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External Event and Data Simulation
Table 2-4. Available Pins for Configuration of TMS320C64x, C62x, C67x, andC672xCPU Cycle Accurate Simulators (continued)
Pin Description Type
INT11
(1)
General purpose external interrupt pin PulseINT12
(1)
General purpose external interrupt pin PulseINT13
(1)
General purpose external interrupt pin PulseINT14
(1)
General purpose external interrupt pin PulseINT15
(1)
General purpose external interrupt pin Pulse
Table 2-5. Available Pins for Configuration of TMS320C6412, C6416, C6713,and DM642 Device Functional Simulators
Pin Description Type
NMI Non-maskable interrupt PulseFSX0 Transmit frame synchronization pin for McBSP0 PulseFSR0 Receive frame synchronization pin for McBSP0 PulseCLKX0 Transmit clock pin for McBSP0 PulseCLKR0 Receive clock pin for McBSP0 PulseCLKS0 External clock input for McBSP0 PulseFSX1 Transmit frame synchronization pin for McBSP1 PulseFSR1 Receive frame synchronization pin for McBSP1 PulseCLKX1 Transmit clock pin for McBSP1 PulseCLKR1 Receive clock pin for McBSP1 PulseCLKS1 External clock input for McBSP1 PulseFSX2
(1)
Transmit frame synchronization pin for McBSP2 PulseFSR2
(1)
Receive frame synchronization pin for McBSP2 PulseCLKX2
(1)
Transmit clock pin for McBSP2 PulseCLKR2
(1)
Receive clock pin for McBSP2 PulseCLKS2
(1)
External clock input for McBSP2 Pulse(1)
This pin is available only on the C6416 Device Functional Simulator.
Table 2-6. Available Pins for Configuration of DM4663, DM6446, TCI6482, and TMX320C6455 DeviceSimulators
Pin Description Type
NMI Non-maskable interrupt PulseINT4 General purpose external interrupt pin PulseINT5 General purpose external interrupt pin PulseINT6 General purpose external interrupt pin PulseINT7 General purpose external interrupt pin PulseFSX0 Transmit frame synchronization pin for McBSP0 PulseFSR0 Receive frame synchronization pin for McBSP0 PulseCLKX0 Transmit clock pin for McBSP0 PulseCLKR0 Receive clock pin for McBSP0 PulseCLKS0 External clock pin for McBSP0 PulseFSX1
(1)
Transmit frame synchronization pin for McBSP1 PulseFSR1
(1)
Receive frame synchronization pin for McBSP1 PulseCLKX1
(1)
Transmit clock pin for McBSP1 PulseCLKR1
(1)
Receive clock pin for McBSP1 Pulse
(1)
This pin is applicable only to the TCI6482 and C6455 simulators.
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2.1.2 Port Connect
External Event and Data Simulation
Table 2-6. Available Pins for Configuration of DM4663, DM6446, TCI6482, and TMX320C6455 DeviceSimulators (continued)
Pin Description Type
CLKS1
(1)
External clock pin for McBSP1 Pulse
The Pin Connect feature can be enabled through the Code Composer Studio command window, GELcommands, or through the Pin Connect plug-in. See Section 4.9 for more information on the Pin Connectfile format. See Code Composer Studio online help for more information on how to connect anddisconnect a specific pin.
The Port Connect feature allows you to feed in external data to the simulator and send simulator data outto an external entity. External data is fed into and out of the simulator (memory or serial port) through PortConnect files (the file format is discussed in Section 4.10 ). This feature can be used to setup an input oroutput data stream to the simulator at the supported address. Whenever a file is connected to a memory(port) address for reads, data from the file is accessed whenever there is a read to the memory in thedevice. Similarly, whenever a file is connected to a memory (port) address for writes, all data writes to thataddress will be written to the file. The simulator provides Port Connect for all processor configurations.
In the case of serial ports, data can be transmitted by connecting some files at the memory-mappedlocations for the serial port transmit register in write mode. Similarly, data can be received by connectingsome files at the memory-mapped locations for the serial port receive register in read mode. Availablememory ranges on the TMS320C6000 devices, to which a file can be connected for reading/writing, aregiven in Table 2-7 .
Table 2-7. Available Memory Ranges for Port Connect for TMS320C6000 Devices
Configuration File
(1)
Available Memory Range
C6201 Device Simulator, Map 1 0x0040 0000 - 0x017F FFFFDXR0, DRR0, DXR1, DRR1
(2)
C6201 Device Simulator, Map 0 0x0000 0000 - 0x013F FFFFDXR0, DRR0, DXR1, DRR1
(2)
C6202 Device Simulator, Map 1 0x0040 0000 - 0x017F FFFFDXR0, DRR0, DXR1, DRR1, DXR2, DRR2
(2)
C6202 Device Simulator, Map 0 0x0000 0000 - 0x013F FFFFDXR0, DRR0, DXR1, DRR1, DXR2, DRR2
(2)
C6203 Device Simulator, Map 1 0x0040 0000 - 0x017F FFFFDXR0, DRR0, DXR1, DRR1, DXR2, DRR2
(2)
C6203 Device Simulator, Map 0 0x0000 0000 - 0x013F FFFFDXR0, DRR0, DXR1, DRR1, DXR2, DRR2
(2)
C6204 Device Simulator, Map 1 0x0040 0000 - 0x017F FFFFDXR0, DRR0, DXR1, DRR1
(2)
C6204 Device Simulator, Map 0 0x0000 0000 - 0x013F FFFFDXR0, DRR0, DXR1, DRR1
(2)
C6205 Device Simulator, Map 1 0x0040 0000 - 0x017F FFFFDXR0, DRR0, DXR1, DRR1
(2)
C6205 Device Simulator, Map 0 0x0000 0000 - 0x013F FFFFDXR0, DRR0, DXR1, DRR1
(2)
C6411 Device Cycle Accurate Simulator 0x8000 0000 - 0xBFFF FFFFDXR0, DRR0, DXR1, DRR1
(2)
C6412 Device Cycle Accurate Simulator 0x0800 0000 - 0xBFFF FFFFDXR0, DRR0, DXR1, DRR1
(2)
C6412 Device Functional Simulator 0x8000 0000 - 0xBFFF FFFF
(1)
For each configuration listed, Little Endian (default) and Big Endian versions are provided with the same available memoryrange for the serial port connection.(2)
To connect to these peripheral registers, use the memory-mapped addresses. Port connects to the McBSP can be done only tothe following locations: 0x3000 0000 for DX0 and DR0, 0x3400 0000 for DX1 and DR1, and 0x3800 0000 for DX2 and DR2.
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