Texas Instruments SM320F2812-HT Data Installation and user guide

SM320F2812-HT
Digital Signal Processor
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SGUS062B
June 2009–Revised June 2011

SM320F2812-HT
SGUS062B–JUNE 2009–REVISED JUNE 2011 www.ti.com
Contents
1 Features ........................................................................................................................... 11
1.1 SUPPORTS EXTREME TEMPERATURE APPLICATIONS ......................................................... 12
2 Introduction ...................................................................................................................... 13
2.1 Description ................................................................................................................. 13
2.2 Device Summary .......................................................................................................... 13
2.3 Die Layout .................................................................................................................. 14
2.4 Pin Assignments ........................................................................................................... 15
2.5 Signal Descriptions ........................................................................................................ 16
3 Functional Overview .......................................................................................................... 25
3.1 Memory Map ............................................................................................................... 26
3.2 Brief Descriptions .......................................................................................................... 29
3.2.1 C28x CPU ....................................................................................................... 29
3.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 29
3.2.3 Peripheral Bus .................................................................................................. 29
3.2.4 Real-Time JTAG and Analysis ................................................................................ 29
3.2.5 External Interface (XINTF) .................................................................................... 30
3.2.6 Flash ............................................................................................................. 30
3.2.7 L0, L1, H0 SARAMs ............................................................................................ 30
3.2.8 Boot ROM ....................................................................................................... 30
3.2.9 Security .......................................................................................................... 31
3.2.10 Peripheral Interrupt Expansion (PIE) Block ................................................................. 32
3.2.11 External Interrupts (XINT1, XINT2, XINT13, XNMI) ........................................................ 32
3.2.12 Oscillator and PLL .............................................................................................. 32
3.2.13 Watchdog ........................................................................................................ 32
3.2.14 Peripheral Clocking ............................................................................................. 32
3.2.15 Low-Power Modes .............................................................................................. 32
3.2.16 Peripheral Frames 0, 1, 2 (PFn) .............................................................................. 33
3.2.17 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 33
3.2.18 32-Bit CPU Timers (0, 1, 2) ................................................................................... 33
3.2.19 Control Peripherals ............................................................................................. 33
3.2.20 Serial Port Peripherals ......................................................................................... 34
3.3 Register Map ............................................................................................................... 34
3.4 Device Emulation Registers .............................................................................................. 37
3.5 External Interface, XINTF ................................................................................................ 37
3.5.1 Timing Registers ................................................................................................ 39
3.5.2 XREVISION Register ........................................................................................... 39
3.6 Interrupts .................................................................................................................... 40
3.6.1 External Interrupts .............................................................................................. 43
3.7 System Control ............................................................................................................ 44
3.8 OSC and PLL Block ....................................................................................................... 46
3.8.1 Loss of Input Clock ............................................................................................. 47
3.9 PLL-Based Clock Module ................................................................................................ 47
3.10 External Reference Oscillator Clock Option ........................................................................... 47
3.11 Watchdog Block ........................................................................................................... 48
3.12 Low-Power Modes Block ................................................................................................. 49
2Contents Copyright ©2009–2011, Texas Instruments Incorporated

SM320F2812-HT
www.ti.com SGUS062B–JUNE 2009–REVISED JUNE 2011
4 Peripherals ....................................................................................................................... 50
4.1 32-Bit CPU-Timers 0/1/2 ................................................................................................. 50
4.2 Event Manager Modules (EVA, EVB) ................................................................................... 53
4.2.1 General-Purpose (GP) Timers ................................................................................ 56
4.2.2 Full-Compare Units ............................................................................................. 56
4.2.3 Programmable Deadband Generator ........................................................................ 56
4.2.4 PWM Waveform Generation .................................................................................. 56
4.2.5 Double Update PWM Mode ................................................................................... 56
4.2.6 PWM Characteristics ........................................................................................... 57
4.2.7 Capture Unit ..................................................................................................... 57
4.2.8 Quadrature-Encoder Pulse (QEP) Circuit ................................................................... 57
4.2.9 External ADC Start-of-Conversion ........................................................................... 57
4.3 Enhanced Analog-to-Digital Converter (ADC) Module ............................................................... 58
4.4 Enhanced Controller Area Network (eCAN) Module .................................................................. 63
4.5 Multichannel Buffered Serial Port (McBSP) Module .................................................................. 67
4.6 Serial Communications Interface (SCI) Module ....................................................................... 71
4.7 Serial Peripheral Interface (SPI) Module ............................................................................... 74
4.8 GPIO MUX ................................................................................................................. 77
5 Development Support ........................................................................................................ 80
5.1 Device and Development Support Tool Nomenclature ............................................................... 80
5.2 Documentation Support ................................................................................................... 81
6 Electrical Specifications ..................................................................................................... 84
6.1 Absolute Maximum Ratings .............................................................................................. 84
6.2 Recommended Operating Conditions .................................................................................. 85
6.3 Electrical Characteristics ................................................................................................. 85
6.4 Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During
Low-Power Modes at 150-MHz SYSCLKOUT ......................................................................... 87
6.5 Current Consumption Graphs ............................................................................................ 88
6.6 Reducing Current Consumption ......................................................................................... 89
6.7 Power Sequencing Requirements ....................................................................................... 89
6.8 Signal Transition Levels .................................................................................................. 91
6.9 Timing Parameter Symbology ........................................................................................... 92
6.10 General Notes on Timing Parameters .................................................................................. 92
6.11 Test Load Circuit .......................................................................................................... 92
6.12 Device Clock Table ........................................................................................................ 93
6.13 Clock Requirements and Characteristics ............................................................................... 93
6.13.1 Input Clock Requirements ..................................................................................... 93
6.13.2 Output Clock Characteristics .................................................................................. 94
6.14 Reset Timing ............................................................................................................... 95
6.15 Low-Power Mode Wakeup Timing ...................................................................................... 99
6.16 Event Manager Interface ................................................................................................ 103
6.16.1 PWM Timing ................................................................................................... 103
6.16.2 Interrupt Timing ................................................................................................ 105
6.17 General-Purpose Input/Output (GPIO) –Output Timing ............................................................ 106
6.18 General-Purpose Input/Output (GPIO) –Input Timing .............................................................. 107
6.19 SPI Master Mode Timing ................................................................................................ 108
6.20 SPI Slave Mode Timing ................................................................................................. 112
Copyright ©2009–2011, Texas Instruments Incorporated Contents 3

SM320F2812-HT
SGUS062B–JUNE 2009–REVISED JUNE 2011 www.ti.com
6.21 External Interface (XINTF) Timing ..................................................................................... 114
6.22 XINTF Signal Alignment to XCLKOUT ................................................................................ 118
6.23 External Interface Read Timing ........................................................................................ 119
6.24 External Interface Write Timing ........................................................................................ 120
6.25 External Interface Ready-on-Read Timing With One External Wait State ....................................... 122
6.26 External Interface Ready-on-Write Timing With One External Wait State ........................................ 125
6.27 XHOLD and XHOLDA ................................................................................................... 128
6.28 XHOLD/XHOLDA Timing ............................................................................................... 129
6.29 On-Chip Analog-to-Digital Converter .................................................................................. 131
6.29.1 ADC Absolute Maximum Ratings ........................................................................... 131
6.29.2 ADC Electrical Characteristics Over Recommended Operating Conditions ........................... 132
6.29.3 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) ...................... 133
6.29.4 ADC Power-Up Control Bit Timing .......................................................................... 134
6.29.5 Detailed Description .......................................................................................... 135
6.29.5.1 Reference Voltage ................................................................................ 135
6.29.5.2 Analog Inputs ..................................................................................... 135
6.29.5.3 Converter .......................................................................................... 135
6.29.5.4 Conversion Modes ............................................................................... 135
6.29.6 Sequential Sampling Mode (Single Channel) (SMODE = 0) ............................................ 135
6.29.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) .......................................... 137
6.29.8 Definitions of Specifications and Terminology ............................................................. 138
6.29.8.1 Integral Nonlinearity .............................................................................. 138
6.29.8.2 Differential Nonlinearity .......................................................................... 138
6.29.8.3 Zero Offset ........................................................................................ 138
6.29.8.4 Gain Error ......................................................................................... 138
6.29.8.5 Signal-to-Noise Ratio + Distortion (SINAD) ................................................... 138
6.29.8.6 Effective Number of Bits (ENOB) ............................................................... 138
6.29.8.7 Total Harmonic Distortion (THD) ............................................................... 138
6.29.8.8 Spurious Free Dynamic Range (SFDR) ....................................................... 138
6.30 Multichannel Buffered Serial Port (McBSP) Timing ................................................................. 139
6.30.1 McBSP Transmit and Receive Timing ...................................................................... 139
6.30.2 McBSP as SPI Master or Slave Timing .................................................................... 142
6.31 Flash Timing .............................................................................................................. 146
6.31.1 Recommended Operating Conditions ...................................................................... 146
7 Mechanical Data .............................................................................................................. 148
Revision History ....................................................................................................................... 149
4Contents Copyright ©2009–2011, Texas Instruments Incorporated

SM320F2812-HT
www.ti.com SGUS062B–JUNE 2009–REVISED JUNE 2011
List of Figures
2-1 SM320F2812 Die Layout........................................................................................................ 14
2-2 SM320F2812 172-Pin HFG CQFP (Top View)............................................................................... 15
3-1 Functional Block Diagram....................................................................................................... 26
3-2 F2812 Memory Map (See Notes A. Through G.) ............................................................................ 26
3-3 External Interface Block Diagram .............................................................................................. 38
3-4 Interrupt Sources................................................................................................................. 40
3-5 Multiplexing of Interrupts Using the PIE Block ............................................................................... 41
3-6 Clock and Reset Domains ...................................................................................................... 44
3-7 OSC and PLL Block.............................................................................................................. 46
3-8 Recommended Crystal/Clock Connection .................................................................................... 47
3-9 Watchdog Module................................................................................................................ 48
4-1 CPU-Timers....................................................................................................................... 50
4-2 CPU-Timer Interrupts Signals and Output Signal (See Notes A. and B.)................................................. 51
4-3 Event Manager A Functional Block Diagram (See Note A.)................................................................ 56
4-4 Block Diagram of the F2812 ADC Module.................................................................................... 59
4-5 ADC Pin Connections With Internal Reference (See Notes A and B)..................................................... 60
4-6 ADC Pin Connections With External Reference ............................................................................. 61
4-7 eCAN Block Diagram and Interface Circuit ................................................................................... 64
4-8 eCAN Memory Map.............................................................................................................. 65
4-9 McBSP Module With FIFO...................................................................................................... 68
4-10 Serial Communications Interface (SCI) Module Block Diagram............................................................ 73
4-11 Serial Peripheral Interface Module Block Diagram (Slave Mode).......................................................... 76
4-12 GPIO/Peripheral Pin Multiplexing .............................................................................................. 79
5-1 28x Device Nomenclature....................................................................................................... 81
6-1 SM320F2812-HT Life Expectancy Curve ..................................................................................... 86
6-2 Typical Current Consumption Over Frequency............................................................................... 88
6-3 Typical Power Consumption Over Frequency................................................................................ 89
6-4 F2812 Typical Power-Up and Power-Down Sequence –Option 2 ........................................................ 90
6-5 Output Levels..................................................................................................................... 91
6-6 Input Levels ....................................................................................................................... 91
6-7 3.3-V Test Load Circuit.......................................................................................................... 92
6-8 Clock Timing ...................................................................................................................... 95
6-9 Power-on Reset in Microcomputer Mode (XMP/MC = 0) (See Note A)................................................... 97
6-10 Power-on Reset in Microprocessor Mode (XMP/MC = 1)................................................................... 98
6-11 Warm Reset in Microcomputer Mode.......................................................................................... 98
6-12 Effect of Writing Into PLLCR Register......................................................................................... 98
6-13 IDLE Entry and Exit Timing ..................................................................................................... 99
6-14 STANDBY Entry and Exit Timing............................................................................................. 101
6-15 HALT Wakeup Using XNMI ................................................................................................... 103
6-16 PWM Output Timing............................................................................................................ 104
6-17 TDIRx Timing.................................................................................................................... 105
6-18 EVASOC Timing ................................................................................................................ 105
6-19 EVBSOC Timing ................................................................................................................ 105
6-20 External Interrupt Timing....................................................................................................... 106
6-21 General-Purpose Output Timing.............................................................................................. 107
6-22 GPIO Input Qualifier –Example Diagram for QUALPRD = 1............................................................. 107
6-23 General-Purpose Input Timing................................................................................................ 108
Copyright ©2009–2011, Texas Instruments Incorporated List of Figures 5

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SGUS062B–JUNE 2009–REVISED JUNE 2011 www.ti.com
6-24 SPI Master Mode External Timing (Clock Phase = 0) ..................................................................... 109
6-25 SPI Master External Timing (Clock Phase = 1)............................................................................. 111
6-26 SPI Slave Mode External Timing (Clock Phase = 0)....................................................................... 113
6-27 SPI Slave Mode External Timing (Clock Phase = 1)....................................................................... 114
6-28 Relationship Between XTIMCLK and SYSCLKOUT ....................................................................... 117
6-29 Example Read Access......................................................................................................... 119
6-30 Example Write Access ......................................................................................................... 121
6-31 Example Read With Synchronous XREADY Access ...................................................................... 123
6-32 Example Read With Asynchronous XREADY Access..................................................................... 124
6-33 Write With Synchronous XREADY Access.................................................................................. 126
6-34 Write With Asynchronous XREADY Access ................................................................................ 127
6-35 External Interface Hold Waveform............................................................................................ 129
6-36 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK).................................................. 130
6-37 ADC Analog Input Impedance Model ........................................................................................ 134
6-38 ADC Power-Up Control Bit Timing ........................................................................................... 134
6-39 Sequential Sampling Mode (Single-Channel) Timing...................................................................... 136
6-40 Simultaneous Sampling Mode Timing ....................................................................................... 137
6-41 McBSP Receive Timing........................................................................................................ 141
6-42 McBSP Transmit Timing....................................................................................................... 141
6-43 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0................................................... 142
6-44 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0................................................... 143
6-45 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1................................................... 144
6-46 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1................................................... 145
6List of Figures Copyright ©2009–2011, Texas Instruments Incorporated

SM320F2812-HT
www.ti.com SGUS062B–JUNE 2009–REVISED JUNE 2011
List of Tables
2-1 Hardware Features............................................................................................................... 13
2-2 Bare Die Information............................................................................................................. 14
2-3 Signal Descriptions .............................................................................................................. 16
3-1 Addresses of Flash Sectors in F2812 ......................................................................................... 27
3-2 Wait States........................................................................................................................ 28
3-3 Boot Mode Selection............................................................................................................. 31
3-4 Peripheral Frame 0 Registers .................................................................................................. 35
3-5 Peripheral Frame 1 Registers .................................................................................................. 35
3-6 Peripheral Frame 2 Registers .................................................................................................. 36
3-7 Device Emulation Registers..................................................................................................... 37
3-8 XINTF Configuration and Control Register Mappings....................................................................... 39
3-9 XREVISION Register Bit Definitions........................................................................................... 39
3-10 PIE Peripheral Interrupts ....................................................................................................... 41
3-11 PIE Configuration and Control Registers ..................................................................................... 42
3-12 External Interrupts Registers ................................................................................................... 43
3-13 PLL, Clocking, Watchdog, and Low-Power Mode Registers .............................................................. 45
3-14 PLLCR Register Bit Definitions................................................................................................. 46
3-15 Possible PLL Configuration Modes ............................................................................................ 47
3-16 F2812 Low-Power Modes....................................................................................................... 49
4-1 CPU-Timers 0, 1, 2 Configuration and Control Registers................................................................... 52
4-2 Module and Signal Names for EVA and EVB ................................................................................ 53
4-3 EVA Registers ................................................................................................................... 54
4-4 ADC Registers ................................................................................................................... 62
4-5 3.3-V eCAN Transceivers for the SM320F2812 DSP ....................................................................... 64
4-6 CAN Registers Map ............................................................................................................. 66
4-7 McBSP Register Summary...................................................................................................... 69
4-8 SCI-A Registers .................................................................................................................. 72
4-9 SCI-B Registers .................................................................................................................. 72
4-10 SPI Registers .................................................................................................................... 75
4-11 GPIO Mux Registers ............................................................................................................ 77
4-12 GPIO Data Registers ............................................................................................................ 78
6-1 Typical Current Consumption by Various Peripherals (at 150 MHz) ..................................................... 89
6-2 Recommended Low-Dropout Regulators ..................................................................................... 89
6-3 Clock Table and Nomenclature................................................................................................. 93
6-4 Input Clock Frequency .......................................................................................................... 93
6-5 XCLKIN Timing Requirements –PLL Bypassed or Enabled .............................................................. 94
6-6 XCLKIN Timing Requirements –PLL Disabled .............................................................................. 94
6-7 Possible PLL Configuration Modes ........................................................................................... 94
6-8 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ....................................................... 94
6-9 Reset (XRS) Timing Requirements ........................................................................................... 95
6-10 IDLE Mode Switching Characteristics ........................................................................................ 99
6-11 STANDBY Mode Switching Characteristics ................................................................................ 100
6-12 HALT Mode Switching Characteristics ...................................................................................... 102
6-13 PWM Switching Characteristics .............................................................................................. 104
6-14 Timer and Capture Unit Timing Requirements ............................................................................. 104
6-15 External ADC Start-of-Conversion –EVA –Switching Characteristics ................................................. 105
6-16 External ADC Start-of-Conversion –EVB –Switching Characteristics ................................................. 105
Copyright ©2009–2011, Texas Instruments Incorporated List of Tables 7

SM320F2812-HT
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6-17 Interrupt Switching Characteristics ........................................................................................... 105
6-18 Interrupt Timing Requirements................................................................................................ 106
6-19 General-Purpose Output Switching Characteristics........................................................................ 106
6-20 General-Purpose Input Timing Requirements .............................................................................. 107
6-21 SPI Master Mode External Timing (Clock Phase = 0) .................................................................... 108
6-22 SPI Master Mode External Timing (Clock Phase = 1) .................................................................... 110
6-23 SPI Slave Mode External Timing (Clock Phase = 0) ...................................................................... 112
6-24 SPI Slave Mode External Timing (Clock Phase = 1) ...................................................................... 113
6-25 Relationship Between Parameters Configured in XTIMING and Duration of Pulse ................................... 114
6-26 XTIMING Register Configuration Restrictions .............................................................................. 115
6-27 Valid and Invalid Timing ....................................................................................................... 115
6-28 XTIMING Register Configuration Restrictions .............................................................................. 115
6-29 Valid and Invalid Timing when using Synchronous XREADY ............................................................ 115
6-30 XTIMING Register Configuration Restrictions .............................................................................. 116
6-31 XTIMING Register Configuration Restrictions .............................................................................. 116
6-32 Asynchronous XREADY ...................................................................................................... 116
6-33 XINTF Clock Configurations................................................................................................... 116
6-34 External Memory Interface Read Switching Characteristics ............................................................. 119
6-35 External Memory Interface Read Timing Requirements .................................................................. 119
6-36 External Memory Interface Write Switching Characteristics .............................................................. 120
6-37 External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State) ....................... 122
6-38 External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) ............................ 122
6-39 Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 122
6-40 Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ...................................... 122
6-41 External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) ........................ 125
6-42 Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ....................................... 125
6-43 Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ...................................... 125
6-44 XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) ...................................................... 129
6-45 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) ................................................. 130
6-46 DC Specifications .............................................................................................................. 132
6-47 AC Specifications .............................................................................................................. 133
6-48 Current Consumption .......................................................................................................... 133
6-49 ADC Power-Up Delays ........................................................................................................ 134
6-50 Sequential Sampling Mode Timing .......................................................................................... 136
6-51 Simultaneous Sampling Mode Timing ....................................................................................... 137
6-52 McBSP Timing Requirements ................................................................................................ 139
6-53 McBSP Switching Characteristics ........................................................................................... 140
6-54 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) ............................... 142
6-55 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) ........................... 142
6-56 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) ............................... 143
6-57 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) ........................... 143
6-58 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) ............................... 144
6-59 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) ........................... 144
6-60 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) ............................... 145
6-61 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) ........................... 145
6-62 Flash Endurance Timing....................................................................................................... 146
6-63 Flash Parameters at 150-MHz SYSCLKOUT .............................................................................. 146
6-64 Flash/OTP Access Timing .................................................................................................... 146
8List of Tables Copyright ©2009–2011, Texas Instruments Incorporated

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6-65 Minimum Required Wait-States at Different Frequencies ................................................................ 147
Copyright ©2009–2011, Texas Instruments Incorporated List of Tables 9

SM320F2812-HT
SGUS062B–JUNE 2009–REVISED JUNE 2011 www.ti.com
10 List of Tables Copyright ©2009–2011, Texas Instruments Incorporated

SM320F2812-HT
www.ti.com SGUS062B–JUNE 2009–REVISED JUNE 2011
Digital Signal Processor
Check for Samples: SM320F2812-HT
1 Features
12
•High-Performance Static CMOS Technology •128 Bit Security Key/Lock
–150 MHz (6.67 ns Cycle Time) –Protects Flash/ROM/OTP and L0/L1 SARAM
–Low Power (1.8 V Core at 135 MHz, 1.9 V, –Prevents Firmware Reverse Engineering
Core at 150 MHz, 3.3 V I/O) Design •Three 32 Bit CPU Timers
–3.3 V Flash Voltage •Motor Control Peripherals
•JTAG Boundary Scan Support(1) –Two Event Managers (EVA, EVB)
•High-Performance 32 Bit CPU (TMS320C28x) –Compatible to 240xA Devices
–16 ×16 and 32 x 32 MAC Operations •Serial Port Peripherals
–16 ×16 Dual MAC –Serial Peripheral Interface (SPI)
–Harvard Bus Architecture –Two Serial Communications Interfaces
–Atomic Operations (SCIs), Standard UART
–Fast Interrupt Response and Processing –Enhanced Controller Area Network (eCAN)
–Unified Memory Programming Model –Multichannel Buffered Serial Port (McBSP)
With SPI Mode
–4M Linear Program Address Reach •12 Bit ADC, 16 Channels
–4M Linear Data Address Reach –2×8 Channel Input Multiplexer
–Code-Efficient (in C/C++ and Assembly) –Two Sample-and-Hold
–TMS320F24x/LF240x Processor Source Code
Compatible –Single/Simultaneous Conversions
•On-Chip Memory –Fast Conversion Rate: 80 ns/12.5 MSPS
–Flash Devices: Up to 128K ×16 Flash (Four •Up to 56 Individually Programmable,
8K ×16 and Six 16K ×16 Sectors) Multiplexed General-Purpose Input / Output
(GPIO) Pins
–ROM Devices: Up to 128K ×16 ROM •Advanced Emulation Features
–1K ×16 OTP ROM –Analysis and Breakpoint Functions
–L0 and L1: 2 Blocks of 4K ×16 Each
Single-Access RAM (SARAM) –Real-Time Debug via Hardware
–H0: 1 Block of 8K ×16 SARAM •Development Tools Include
–M0 and M1: 2 Blocks of 1K ×16 Each –ANSI C/C++ Compiler/Assembler/Linker
SARAM –Supports TMS320C24x™/240x Instructions
•Boot ROM (4K ×16) –Code Composer Studio™IDE
–With Software Boot Modes –DSP/BIOS™
–Standard Math Tables –JTAG Scan Controllers [Texas Instruments
•External Interface (TI) or Third-Party]
–Up to 1M Total Memory –Evaluation Modules
–Programmable Wait States –Broad Third-Party Digital Motor Control
Support
–Programmable Read/Write Strobe Timing •Low-Power Modes and Power Savings
–Three Individual Chip Selects –IDLE, STANDBY, HALT Modes Supported
•Clock and System Control –Disable Individual Peripheral Clocks
–Dynamic PLL Ratio Changes Supported xxx
–On-Chip Oscillator xxx
–Watchdog Timer Module
•Three External Interrupts xxx
•Peripheral Interrupt Expansion (PIE) Block That xxx
Supports 45 Peripheral Interrupts xxx
xxx
(1) IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port
1TMS320C24x, Code Composer Studio, DSP/BIOS, C28x, TMS320C2000, TMS320C54x, TMS320C55x, TMS320C28x are trademarks of
Texas Instruments.
2eZdsp is a trademark of Spectrum Digital Incorporated.
Copyright ©2009–2011, Texas Instruments Incorporated Features 11

SM320F2812-HT
xxx
SGUS062B–JUNE 2009–REVISED JUNE 2011 www.ti.com
1.1 SUPPORTS EXTREME TEMPERATURE APPLICATIONS
•Controlled Baseline
•One Assembly/Test Site
•One Fabrication Site
•Available in Extreme (–55°C/220°C) Temperature Range(2)
•Extended Product Life Cycle
•Extended Product-Change Notification
•Product Traceability
•Texas Instruments high temperature products utilize highly optimized silicon (die) solutions with
design and process enhancements to maximize performance over extended temperatures.
(2) Custom temperature ranges available
12 Features Copyright ©2009–2011, Texas Instruments Incorporated

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2 Introduction
This section provides a summary of the device features, lists the pin assignments, and describes the
function of each pin. This document also provides detailed descriptions of peripherals, electrical
specifications, parameter measurement information, and mechanical data about the available packaging.
32.1 Description
The SM320F2812 device, member of the C28xE DSP generation, is a highly integrated, high-performance
solution for demanding control applications. The functional blocks and the memory maps are described in
Section 3, Functional Overview.
Throughout this document SM320F2812 is abbreviated as F2812.
2.2 Device Summary
Table 2-1 provides a summary of the device features.
Table 2-1. Hardware Features
FEATURE F2812
Instruction Cycle (at 150 MHz) 6.67 ns
Single-Access RAM (SARAM) (16 bit word) 18K
3.3 V On-Chip Flash (16 bit word) 128K
On-Chip ROM (16-bit word) —
Code Security for On-Chip Flash/SARAM/OTP/ROM Yes
Boot ROM Yes
OTP ROM (1K ×16) Yes
External Memory Interface Yes
Event Managers A and B (EVA and EVB) EVA, EVB
•General-Purpose (GP) Timers 4
•Compare (CMP)/PWM 16
•Capture (CAP)/QEP Channels 6/2
Watchdog Timer Yes
12 Bit ADC Yes
•Channels 16
32 Bit CPU Timers 3
SPI Yes
SCIA, SCIB SCIA, SCIB
CAN Yes
McBSP Yes
Digital I/O Pins (Shared) 56
External Interrupts 3
Supply Voltage 1.8-V Core, (135 MHz) 1.9-V Core
(150 MHz), 3.3-V I/O
Temperature Options S: –55°C to 220°C Yes
3Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

SM320F2812-HT
SGUS062B–JUNE 2009–REVISED JUNE 2011 www.ti.com
2.3 Die Layout
The SM320F2812 die layout is shown in Figure 2-1. See Table 2-3 for a description of each pad's
function.
Figure 2-1. SM320F2812 Die Layout
Table 2-2. Bare Die Information
DIE PAD
DIE PAD DIE BACKSIDE BACKSIDE
DIE SIZE DIE PAD SIZE COMPOSITI
COORDINATES THICKNESS FINISH POTENTIAL
ON
219.4 x 207.0 (mils); Silicon with
55.0 x 64.0 (μm) See Table 2-3 11.0 mils AlCu/TiN Ground
5572.0 x 5258.0 (μm) backgrind
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VDDAIO
1
130
172
ADCINB0
ADCINB1
ADCINB2
ADCINB3
ADCINB4
ADCINB5
ADCINB6
ADCINB7
ADCREFM
ADCREFP
AVSSREFBG
AVDDREFBG
VDDA1
VSSA1
ADCRESEXT
MC
XMP/
XA[0]
MDRA
XD[0]
MDXA
VDD
XD[1]
MCLKRA
MFSXA
XD[2]
MCLKXA
MFSRA
XD[3]
VDDIO
VSS
XD[4]
SPICLKA
SPISTEA
XD[5]
VDD
VSS
XD[6]
SPISIMOA
SPISOMIA
XRD
XA[1]
XZCS0AND1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
XA[11]
TDI
XA[10] TDO
TMS
XA[9]
XA[8]
XCLKOUT
XA[7]
TCLKINA
TDIRA
XA[6] CAP3_QEPI1
XA[5]
CAP2_QEP2
CAP1_QEP1
T2PWM_T2CMP
XA[4]
T1PWM_T1CMP
PWM6 PWM5
XD[13]
XD[12]
PWM4
PWM3
PWM2
PWM1
SCIRXDB
SCITXDB
CANRXA VSS
VDD VSS
T1CTRIP_PDPINTA
VDD
VSS
VDDIO
T2CTRIP / EVASOC C1TRIP C2TRIP C3TRIP
VDD
V
PWM8
PWM9
PWM10
PWM11
PWM12
XR/W
VSS
T3PWM_T3CMP
XD[7]
T4PWM_T4CMP
VDD
CAP4_QEP3
VSS
CAP5_QEP4
CAP6_QEPI2
C4TRIP
C5TRIP
C6TRIP
VDDIO
XD[8]
TEST2
TEST1
XD[9]
VDD3VFL
TDIRB
TCLKINB
XD[10]
XD[11]
VDD
X2
X1/XCLKIN
VSS
T3CTRIP_PDPINTB
XA[2]
VDDIO
XHOLDA
T4CTRIP/EVBSOC
XWE
XA[3]
VSS
CANTXA
XZCS2
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
86
44
129 87
43
TESTSEL
TRST
TCK
EMU0
XA[12]
XD[14]
XA[13]
VSS
VDD
XA[14]
VDDIO
EMU1
XD[15]
XA[15]
XINT1_XBIO
XA[16]
VDD
SCITXDA
XA[17]
SCIRXDA
XA[18]
XHOLD
XRS
XREADY
VDD1
VSS1
VSSA2
VDDA2
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCLO
VSSAIO
45
89
88
132
133
XZCS6AND7
XF_XPLLDIS
XNMI_XINT13
XINT2_ADCSOC
ADCBGREFIN
PWM7
131
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2.4 Pin Assignments
The SM320F2812 172-pin HFG ceramic quad flatpack (CQFP) pin assignments are shown in Figure 2-2.
See Table 2-3 for a description of each pin’s function(s).
Figure 2-2. SM320F2812 172-Pin HFG CQFP (Top View)
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2.5 Signal Descriptions
Table 2-3 specifies the signals on the F2812 device. All digital inputs are TTL-compatible. All outputs are
3.3 V with CMOS levels. Inputs are not 5 V tolerant. A 100 μA (or 20 μA) pullup/pulldown is used.
Table 2-3. Signal Descriptions(1)
PIN NO. DIE PAD DIE PAD
DIE PAD
NAME X-CENTER Y-CENTER I/O/Z(2) PU/PD(3) DESCRIPTION
172-PIN NO. (μm) (μm)
HFG
XINTF SIGNALS
XA[18] 154 173 42.6 2281.5 O/Z –
XA[17] 152 171 42.6 2485.3 O/Z –
XA[16] 149 167 42.6 2819.6 O/Z –
XA[15] 145 163 42.6 3182.9 O/Z –
XA[14] 141 157 42.6 3774.9 O/Z –
XA[13] 138 154 42.6 4029.4 O/Z –
XA[12] 135 151 42.6 4401.3 O/Z –
XA[11] 129 145 255.7 5057.5 O/Z
XA[10] 127 143 474.4 5057.5 O/Z –
XA[9] 122 138 996.5 5057.5 O/Z –19-bit XINTF Address Bus
XA[8] 118 134 1492.4 5057.5 O/Z –
XA[7] 116 131 1825.2 5057.5 O/Z –
XA[6] 109 124 2566.0 5057.5 O/Z –
XA[5] 106 121 2937.9 5057.5 O/Z –
XA[4] 101 116 3518.7 5057.5 O/Z –
XA[3] 83 96 5361.5 4471.5 O/Z –
XA[2] 78 91 5361.5 3927.2 O/Z –
XA[1] 42 49 5024.5 42.6 O/Z –
XA[0] 18 24 2403.5 42.6 O/Z
XD[15] 144 162 42.6 3306.9 I/O/Z PU
XD[14] 136 152 42.6 4277.3 I/O/Z PU
XD[13] 95 110 4194.1 5057.5 I/O/Z PU
XD[12] 94 109 4318.1 5057.5 I/O/Z PU
XD[11] 72 85 5361.5 3382.2 I/O/Z PU
XD[10] 71 84 5361.5 3258.3 I/O/Z PU
XD[9] 67 77 5361.5 2608.4 I/O/Z PU
XD[8] 64 74 5361.5 2312.1 I/O/Z PU 16-bit XINTF Data Bus
XD[7] 53 60 5361.5 1045.9 I/O/Z PU
XD[6] 38 45 4586.0 42.6 I/O/Z PU
XD[5] 35 42 4281.2 42.6 I/O/Z PU
XD[4] 32 39 3966.6 42.6 I/O/Z PU
XD[3] 29 36 3652.0 42.6 I/O/Z PU
XD[2] 26 33 3337.5 42.6 I/O/Z PU
XD[1] 23 30 3022.9 42.6 I/O/Z PU
XD[0] 20 27 2708.3 42.6 I/O/Z PU
(1) Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are
8 mA.
(2) I = Input, O = Output, Z = High impedance
(3) PU = pin has internal pullup; PD = pin has internal pulldown
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Table 2-3. Signal Descriptions(1) (continued)
PIN NO. DIE PAD DIE PAD
DIE PAD
NAME X-CENTER Y-CENTER I/O/Z(2) PU/PD(3) DESCRIPTION
172-PIN NO. (μm) (μm)
HFG
Microprocessor/Microcomputer Mode
Select. Switches between microprocessor
and microcomputer mode. When high,
Zone 7 is enabled on the external interface.
When low, Zone 7 is disabled from the
XMP/MC 17 23 2308.2 42.6 I PD external interface and on-chip boot ROM
may be accessed instead. This signal is
latched into the XINTCNF2 register on a
reset and the user can modify this bit in
software. The state of the XMP/MC pin is
ignored after reset.
External Hold Request. XHOLD, when
active (low), requests the XINTF to release
the external bus and place all buses and
XHOLD 155 174 42.6 2157.6 I PU strobes into a high-impedance state. The
XINTF releases the bus when any current
access is complete and there are no
pending accesses on the XINTF.
External Hold Acknowledge. XHOLDA is
driven active (low) when the XINTF has
granted a XHOLD request. All XINTF buses
and strobe signals are in a high-impedance
XHOLDA 80 93 5361.5 4137.4 O/Z –state. XHOLDA is released when the
XHOLD signal is released. External devices
should only drive the external bus when
XHOLDA is active (low).
XINTF Zone 0 and Zone 1 Chip Select.
XZCS0AND1 is active (low) when an
XZCS0AND1 43 50 5148.5 42.6 O/Z –access to the XINTF Zone 0 or Zone 1 is
performed.
XINTF Zone 2 Chip Select. XZCS2 is active
XZCS2 86 100 5361.5 4844.2 O/Z –(low) when an access to the XINTF Zone 2
is performed.
XINTF Zone 6 and Zone 7 Chip Select.
XZCS6AND7 is active (low) when an
XZCS6AND7 130 146 42.6 4888.6 O/Z –access to the XINTF Zone 6 or Zone 7 is
performed.
Write Enable. Active-low write strobe. The
write strobe waveform is specified, per zone
XWE 82 95 5361.5 4347.5 O/Z –basis, by the Lead, Active, and Trail periods
in the XTIMINGx registers.
Read Enable. Active-low read strobe. The
read strobe waveform is specified, per zone
basis, by the Lead, Active, and Trail periods
XRD 41 48 4900.6 42.6 O/Z –in the XTIMINGx registers.
NOTE: The XRD and XWE signals are
mutually exclusive.
Read Not Write Strobe. Normally held high.
When low, XR/W indicates write cycle is
XR/W 50 57 5361.5 755.0 O/Z –active; when high, XR/W indicates read
cycle is active.
Ready Signal. Indicates peripheral is ready
to complete the access when asserted to 1.
XREADY 157 176 42.6 1972.4 I PU XREADY can be configured to be a
synchronous or an asynchronous input.
See the timing diagrams for more details.
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Table 2-3. Signal Descriptions(1) (continued)
PIN NO. DIE PAD DIE PAD
DIE PAD
NAME X-CENTER Y-CENTER I/O/Z(2) PU/PD(3) DESCRIPTION
172-PIN NO. (μm) (μm)
HFG
JTAG AND MISCELLANEOUS SIGNALS
Oscillator Input –input to the internal
oscillator. This pin is also used to feed an
external clock. The 28×can be operated
with an external clock source, provided that
the proper voltage levels be driven on the
X1/XCLKIN pin. It should be noted that the
X1/XCLKIN pin is referenced to the 1.8-V
X1/XCLKIN 75 88 5361.5 3668.7 I (or 1.9-V) core digital power supply (VDD),
rather than the 3.3-V I/O supply (VDDIO). A
clamping diode may be used to clamp a
buffered clock signal to ensure that the
logic-high level does not exceed VDD
(1.8 V or 1.9 V) or a 1.8-V oscillator may be
used.
X2 74 87 5361.5 3582.6 O Oscillator Output
Output clock derived from SYSCLKOUT to
be used for external wait-state generation
and as a general-purpose clock source.
XCLKOUT is either the same frequency,
XCLKOUT 117 132 1701.2 5057.5 O –1/2 the frequency, or 1/4 the frequency of
SYSCLKOUT. At reset, XCLKOUT =
SYSCLKOUT/4. The XCLKOUT signal can
be turned off by setting bit 3 (CLKOFF) of
the XINTCNF2 register to 1.
Test Pin. Reserved for TI. Must be
TESTSEL 131 147 42.6 4764.6 I PD connected to ground.
Device Reset (in) and Watchdog Reset
(out).
Device reset. XRS causes the device to
terminate execution. The PC points to the
address contained at the location
0x3FFFC0. When XRS is brought to a high
level, execution begins at the location
pointed to by the PC. This pin is driven low
XRS 156 175 42.6 2077.8 I/O PU by the DSP when a watchdog reset occurs.
During watchdog reset, the XRS pin is
driven low for the watchdog reset duration
of 512 XCLKIN cycles.
The output buffer of this pin is an
open-drain with an internal pullup (100 μA,
typical). It is recommended that this pin be
driven by an open-drain device.
Test Pin. Reserved for TI. On F281x
TEST1 66 76 5361.5 2522.3 I/O –devices, TEST1 must be left unconnected.
Test Pin. Reserved for TI. On F281x
TEST2 65 75 5361.5 2436.1 I/O –devices, TEST2 must be left unconnected.
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Table 2-3. Signal Descriptions(1) (continued)
PIN NO. DIE PAD DIE PAD
DIE PAD
NAME X-CENTER Y-CENTER I/O/Z(2) PU/PD(3) DESCRIPTION
172-PIN NO. (μm) (μm)
HFG
JTAG test reset with internal pulldown.
TRST, when driven high, gives the scan
system control of the operations of the
device. If this signal is not connected or
driven low, the device operates in its
functional mode, and the test reset signals
are ignored.
NOTE: Do not use pullup resistors on
TRST; it has an internal pulldown device. In
a low-noise environment, TRST can be left
TRST 132 148 42.6 4684.8 I PD floating. In a high-noise environment, an
additional pulldown resistor may be
needed. The value of this resistor should be
based on drive strength of the debugger
pods applicable to the design. A 2.2-kΩ
resistor generally offers adequate
protection. Since this is application specific,
it is recommended that each target board is
validated for proper operation of the
debugger and the application.
TCK 133 149 42.6 4605.1 I PU JTAG test clock with internal pullup
JTAG test-mode select (TMS) with internal
pullup. This serial control input is clocked
TMS 123 139 872.5 5057.5 I PU into the TAP controller on the rising edge of
TCK.
JTAG test data input (TDI) with internal
pullup. TDI is clocked into the selected
TDI 128 144 350.4 5057.5 I PU register (instruction or data) on a rising
edge of TCK.
JTAG scan out, test data output (TDO). The
contents of the selected register (instruction
TDO 124 140 777.9 5057.5 O/Z –or data) is shifted out of TDO on the falling
edge of TCK.
Emulator pin 0. When TRST is driven high,
this pin is used as an interrupt to or from
EMU0 133 150 42.6 4525.3 I/O/Z PU the emulator system and is defined as
input/output through the JTAG scan.
Emulator pin 1. When TRST is driven high,
this pin is used as an interrupt to or from
EMU1 143 161 42.6 3430.9 I/O/Z PU the emulator system and is defined as
input/output through the JTAG scan.
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Table 2-3. Signal Descriptions(1) (continued)
PIN NO. DIE PAD DIE PAD
DIE PAD
NAME X-CENTER Y-CENTER I/O/Z(2) PU/PD(3) DESCRIPTION
172-PIN NO. (μm) (μm)
HFG
ADC ANALOG INPUT SIGNALS
ADCINA7 163 186 42.6 1253.9 I
ADCINA6 164 188 42.6 1094.3 I
ADCINA5 165 190 42.6 954.0 I Eight-channel analog inputs for
ADCINA4 166 192 42.6 794.4 I Sample-and-Hold A. The ADC pins should
not be driven before VDDA1, VDDA2, and
ADCINA3 167 194 42.6 654.1 I VDDAIO pins have been fully powered up.
ADCINA2 168 196 42.6 513.9 I
ADCINA1 169 197 42.6 434.1 I
ADCINA0 170 198 42.6 354.3 I
ADCINB7 9 13 1355.2 42.6 I
ADCINB6 8 11 1164.6 42.6 I
ADCINB5 7 10 1069.2 42.6 I Eight-channel analog inputs for
ADCINB4 6 8 878.6 42.6 I Sample-and-Hold B. The ADC pins should
not be driven before the VDDA1, VDDA2, and
ADCINB3 5 6 688.0 42.6 I VDDAIO pins have been fully powered up.
ADCINB2 4 4 497.4 42.6 I
ADCINB1 3 3 402.1 42.6 I
ADCINB0 2 2 306.8 42.6 I ADC Voltage Reference Output (2 V).
Requires a low ESR (50 mΩ – 1.5 Ω)
ceramic bypass capacitor of 10 μF to
analog ground. (Can accept external
ADCREFP 11 15 1545.8 42.6 O reference input
(2 V) if the software bit is enabled for this
mode. 1-μF to 10-μF low ESR capacitor
can be used in the external reference
mode.)
ADC Voltage Reference Output (1 V).
Requires a low ESR (50 mΩ – 1.5 Ω)
ceramic bypass capacitor of 10 μF to
analog ground. (Can accept external
ADCREFM 10 14 1450.5 42.6 O reference input
(1 V) if the software bit is enabled for this
mode. 1-μF to 10-μF low ESR capacitor
can be used in the external reference
mode.)
ADC External Current Bias Resistor
ADCRESEXT 16 22 2212.9 42.63 O (24.9 kΩ ±5%)
Test Pin. Reserved for TI. Must be left
ADCBGREFIN 160 180 42.6 1680.9 I unconnected.
AVSSREFBG 12 17 1831.7 42.6 I ADC Analog GND
AVDDREFBG 13 18 1736.4 42.6 I ADC Analog Power (3.3 V)
Common Low Side Analog Input. Connect
ADCLO 171 199 42.6 274.5 I to analog ground.
VSSA1 15 21 2117.6 42.6 I ADC Analog GND
VSSA2 161 182 42.6 1550.7 I ADC Analog GND
VDDA1 14 19 1927.0 42.6 I ADC Analog 3.3-V Supply
VDDA2 162 184 42.6 1394.2 I ADC Analog 3.3-V Supply
VSS1 159 178 42.6 1830.8 I ADC Digital GND
VDD1 158 177 42.6 1901.0 I ADC Digital 1.8-V (or 1.9-V) Supply
VDDAIO 1 1 211.5 42.6 3.3-V Analog I/O Power Pin
VSSAIO 172 200 42.6 204.3 Analog I/O Ground Pin
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