Texas Instruments TMS320F2809 Data Installation and user guide

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
Digital Signal Processors
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SPRS230N
October 2003–Revised May 2012

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com SPRS230N –OCTOBER 2003–REVISED MAY 2012
Contents
1 F280x, F2801x, C280x DSPs .................................................................................................. 8
1.1 Features ...................................................................................................................... 8
1.2 Getting Started .............................................................................................................. 9
2 Introduction ...................................................................................................................... 10
2.1 Pin Assignments ........................................................................................................... 13
2.2 Signal Descriptions ........................................................................................................ 18
3 Functional Overview .......................................................................................................... 24
3.1 Memory Maps .............................................................................................................. 25
3.2 Brief Descriptions .......................................................................................................... 33
3.2.1 C28x CPU ....................................................................................................... 33
3.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 33
3.2.3 Peripheral Bus .................................................................................................. 33
3.2.4 Real-Time JTAG and Analysis ................................................................................ 34
3.2.5 Flash ............................................................................................................. 34
3.2.6 ROM .............................................................................................................. 34
3.2.7 M0, M1 SARAMs ............................................................................................... 34
3.2.8 L0, L1, H0 SARAMs ............................................................................................ 35
3.2.9 Boot ROM ....................................................................................................... 35
3.2.10 Security .......................................................................................................... 36
3.2.11 Peripheral Interrupt Expansion (PIE) Block ................................................................. 37
3.2.12 External Interrupts (XINT1, XINT2, XNMI) .................................................................. 37
3.2.13 Oscillator and PLL .............................................................................................. 37
3.2.14 Watchdog ........................................................................................................ 37
3.2.15 Peripheral Clocking ............................................................................................. 37
3.2.16 Low-Power Modes .............................................................................................. 37
3.2.17 Peripheral Frames 0, 1, 2 (PFn) .............................................................................. 38
3.2.18 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 38
3.2.19 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 38
3.2.20 Control Peripherals ............................................................................................. 38
3.2.21 Serial Port Peripherals ......................................................................................... 39
3.3 Register Map ............................................................................................................... 39
3.4 Device Emulation Registers .............................................................................................. 41
3.5 Interrupts .................................................................................................................... 41
3.5.1 External Interrupts .............................................................................................. 44
3.6 System Control ............................................................................................................ 45
3.6.1 OSC and PLL Block ............................................................................................ 46
3.6.1.1 External Reference Oscillator Clock Option .................................................... 47
3.6.1.2 PLL-Based Clock Module ......................................................................... 48
3.6.1.3 Loss of Input Clock ................................................................................ 49
3.6.2 Watchdog Block ................................................................................................. 50
3.7 Low-Power Modes Block ................................................................................................. 51
4 Peripherals ....................................................................................................................... 52
4.1 32-Bit CPU-Timers 0/1/2 ................................................................................................. 52
4.2 Enhanced PWM Modules (ePWM1/2/3/4/5/6) ......................................................................... 54
4.3 Hi-Resolution PWM (HRPWM) .......................................................................................... 57
4.4 Enhanced CAP Modules (eCAP1/2/3/4) ............................................................................... 57
4.5 Enhanced QEP Modules (eQEP1/2) .................................................................................... 60
4.6 Enhanced Analog-to-Digital Converter (ADC) Module ............................................................... 62
4.6.1 ADC Connections if the ADC Is Not Used .................................................................. 65
4.6.2 ADC Registers .................................................................................................. 66
4.7 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B) .................................... 67
2Contents Copyright © 2003–2012, Texas Instruments Incorporated

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com SPRS230N –OCTOBER 2003–REVISED MAY 2012
4.8 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B) ................................................... 72
4.9 Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D) .......................................... 75
4.10 Inter-Integrated Circuit (I2C) ............................................................................................. 79
4.11 GPIO MUX ................................................................................................................. 81
5 Device Support ................................................................................................................. 85
5.1 Device and Development Support Tool Nomenclature ............................................................... 85
5.2 Documentation Support .................................................................................................. 87
5.3 Community Resources .................................................................................................... 92
6 Electrical Specifications ..................................................................................................... 93
6.1 Absolute Maximum Ratings .............................................................................................. 93
6.2 Recommended Operating Conditions .................................................................................. 94
6.3 Electrical Characteristics ................................................................................................. 94
6.4 Current Consumption ..................................................................................................... 95
6.4.1 Reducing Current Consumption .............................................................................. 99
6.4.2 Current Consumption Graphs ............................................................................... 100
6.5 Emulator Connection Without Signal Buffering for the DSP ....................................................... 102
6.6 Timing Parameter Symbology .......................................................................................... 103
6.6.1 General Notes on Timing Parameters ...................................................................... 103
6.6.2 Test Load Circuit .............................................................................................. 103
6.6.3 Device Clock Table ........................................................................................... 104
6.7 Clock Requirements and Characteristics ............................................................................. 105
6.8 Power Sequencing ....................................................................................................... 106
6.8.1 Power Management and Supervisory Circuit Solutions .................................................. 106
6.9 General-Purpose Input/Output (GPIO) ................................................................................ 109
6.9.1 GPIO - Output Timing ........................................................................................ 109
6.9.2 GPIO - Input Timing .......................................................................................... 110
6.9.3 Sampling Window Width for Input Signals ................................................................. 111
6.9.4 Low-Power Mode Wakeup Timing .......................................................................... 112
6.10 Enhanced Control Peripherals ......................................................................................... 115
6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing ....................................................... 115
6.10.2 Trip-Zone Input Timing ....................................................................................... 115
6.10.3 External Interrupt Timing ..................................................................................... 117
6.10.4 I2C Electrical Specification and Timing .................................................................... 118
6.10.5 Serial Peripheral Interface (SPI) Master Mode Timing ................................................... 118
6.10.6 SPI Slave Mode Timing ...................................................................................... 123
6.10.7 On-Chip Analog-to-Digital Converter ....................................................................... 125
6.10.7.1 ADC Power-Up Control Bit Timing ............................................................. 126
6.10.7.2 Definitions ......................................................................................... 127
6.10.7.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0) ............................... 128
6.10.7.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) .............................. 129
6.11 Detailed Descriptions .................................................................................................... 130
6.12 Flash Timing .............................................................................................................. 131
6.13 ROM Timing (C280x only) .............................................................................................. 133
7 Migrating From F280x Devices to C280x Devices ................................................................. 134
7.1 Migration Issues .......................................................................................................... 134
8 Revision History .............................................................................................................. 135
9 Mechanical Data .............................................................................................................. 136
Copyright © 2003–2012, Texas Instruments Incorporated Contents 3

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230N –OCTOBER 2003–REVISED MAY 2012 www.ti.com
List of Figures
2-1 TMS320F2809, TMS320F2808 100-Pin PZ LQFP (Top View) ............................................................ 14
2-2 TMS320F2806 100-Pin PZ LQFP (Top View)................................................................................ 15
2-3 TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801 100-Pin PZ LQFP (Top View)..................... 16
2-4 TMS320F2801x 100-Pin PZ LQFP (Top View) .............................................................................. 17
2-5 TMS320F2809, TMS320F2808, TMS320F2806,TMS320F2802, TMS320F2801,
TMS320F28016, TMS320F28015, TMS320C2802, TMS320C2801
100-Ball GGM and ZGM MicroStar BGA™ (Bottom View) ................................................................. 17
3-1 Functional Block Diagram....................................................................................................... 25
3-2 F2809 Memory Map.............................................................................................................. 26
3-3 F2808 Memory Map.............................................................................................................. 27
3-4 F2806 Memory Map.............................................................................................................. 28
3-5 F2802, C2802 Memory Map.................................................................................................... 29
3-6 F2801, F28015, F28016, C2801 Memory Map............................................................................... 29
3-7 External and PIE Interrupt Sources............................................................................................ 43
3-8 Multiplexing of Interrupts Using the PIE Block ............................................................................... 43
3-9 Clock and Reset Domains ...................................................................................................... 45
3-10 OSC and PLL Block Diagram................................................................................................... 46
3-11 Using a 3.3-V External Oscillator............................................................................................... 47
3-12 Using a 1.8-V External Oscillator............................................................................................... 47
3-13 Using the Internal Oscillator .................................................................................................... 47
3-14 Watchdog Module................................................................................................................ 50
4-1 CPU-Timers....................................................................................................................... 52
4-2 CPU-Timer Interrupt Signals and Output Signal ............................................................................. 53
4-3 Multiple PWM Modules in a 280x System .................................................................................... 54
4-4 ePWM Sub-Modules Showing Critical Internal Signal Interconnections.................................................. 56
4-5 eCAP Functional Block Diagram............................................................................................... 58
4-6 eQEP Functional Block Diagram............................................................................................... 60
4-7 Block Diagram of the ADC Module ............................................................................................ 63
4-8 ADC Pin Connections With Internal Reference .............................................................................. 64
4-9 ADC Pin Connections With External Reference ............................................................................. 65
4-10 eCAN Block Diagram and Interface Circuit ................................................................................... 68
4-11 eCAN-A Memory Map ........................................................................................................... 69
4-12 eCAN-B Memory Map ........................................................................................................... 70
4-13 Serial Communications Interface (SCI) Module Block Diagram............................................................ 74
4-14 SPI Module Block Diagram (Slave Mode) .................................................................................... 78
4-15 I2C Peripheral Module Interfaces .............................................................................................. 80
4-16 GPIO MUX Block Diagram...................................................................................................... 81
4-17 Qualification Using Sampling Window......................................................................................... 84
5-1 Example of TMS320x280x/2801x Device Nomenclature ................................................................... 86
6-1 Typical Operational Current Versus Frequency (F2808) .................................................................. 100
6-2 Typical Operational Power Versus Frequency (F2808).................................................................... 100
6-3 Typical Operational Current Versus Frequency (C280x).................................................................. 101
6-4 Typical Operational Power Versus Frequency (C280x) ................................................................... 101
6-5 Emulator Connection Without Signal Buffering for the DSP .............................................................. 102
6-6 3.3-V Test Load Circuit......................................................................................................... 103
6-7 Clock Timing..................................................................................................................... 106
6-8 Power-on Reset................................................................................................................. 107
4List of Figures Copyright © 2003–2012, Texas Instruments Incorporated

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com SPRS230N –OCTOBER 2003–REVISED MAY 2012
6-9 Warm Reset ..................................................................................................................... 108
6-10 Example of Effect of Writing Into PLLCR Register ......................................................................... 109
6-11 General-Purpose Output Timing.............................................................................................. 110
6-12 Sampling Mode ................................................................................................................. 110
6-13 General-Purpose Input Timing................................................................................................ 111
6-14 IDLE Entry and Exit Timing.................................................................................................... 112
6-15 STANDBY Entry and Exit Timing Diagram.................................................................................. 113
6-16 HALT Wake-Up Using GPIOn................................................................................................. 114
6-17 PWM Hi-Z Characteristics ..................................................................................................... 115
6-18 ADCSOCAO or ADCSOCBO Timing ........................................................................................ 117
6-19 External Interrupt Timing....................................................................................................... 117
6-20 SPI Master Mode External Timing (Clock Phase = 0) ..................................................................... 120
6-21 SPI Master Mode External Timing (Clock Phase = 1) ..................................................................... 122
6-22 SPI Slave Mode External Timing (Clock Phase = 0)....................................................................... 124
6-23 SPI Slave Mode External Timing (Clock Phase = 1)....................................................................... 125
6-24 ADC Power-Up Control Bit Timing ........................................................................................... 126
6-25 ADC Analog Input Impedance Model ........................................................................................ 127
6-26 Sequential Sampling Mode (Single-Channel) Timing...................................................................... 128
6-27 Simultaneous Sampling Mode Timing ....................................................................................... 129
Copyright © 2003–2012, Texas Instruments Incorporated List of Figures 5

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230N –OCTOBER 2003–REVISED MAY 2012 www.ti.com
List of Tables
2-1 Hardware Features (100-MHz Devices)....................................................................................... 11
2-2 Hardware Features (60-MHz Devices) ........................................................................................ 12
2-3 Signal Descriptions............................................................................................................... 18
3-1 Addresses of Flash Sectors in F2809 ......................................................................................... 30
3-2 Addresses of Flash Sectors in F2808 ......................................................................................... 30
3-3 Addresses of Flash Sectors in F2806, F2802................................................................................ 30
3-4 Addresses of Flash Sectors in F2801, F28015, F28016.................................................................... 31
3-5 Impact of Using the Code Security Module................................................................................... 31
3-6 Wait-states ........................................................................................................................ 32
3-7 Boot Mode Selection............................................................................................................. 35
3-8 Peripheral Frame 0 Registers .................................................................................................. 40
3-9 Peripheral Frame 1 Registers .................................................................................................. 40
3-10 Peripheral Frame 2 Registers .................................................................................................. 41
3-11 Device Emulation Registers..................................................................................................... 41
3-12 PIE Peripheral Interrupts ....................................................................................................... 43
3-13 PIE Configuration and Control Registers...................................................................................... 44
3-14 External Interrupt Registers..................................................................................................... 44
3-15 PLL, Clocking, Watchdog, and Low-Power Mode Registers .............................................................. 46
3-16 PLLCR Register Bit Definitions................................................................................................. 48
3-17 Possible PLL Configuration Modes ............................................................................................ 49
3-18 Low-Power Modes ............................................................................................................... 51
4-1 CPU-Timers 0, 1, 2 Configuration and Control Registers................................................................... 53
4-2 ePWM Control and Status Registers .......................................................................................... 55
4-3 eCAP Control and Status Registers ........................................................................................... 59
4-4 eQEP Control and Status Registers........................................................................................... 61
4-5 ADC Registers ................................................................................................................... 66
4-6 3.3-V eCAN Transceivers ...................................................................................................... 68
4-7 CAN Register Map .............................................................................................................. 71
4-8 SCI-A Registers .................................................................................................................. 73
4-9 SCI-B Registers .................................................................................................................. 73
4-10 SPI-A Registers................................................................................................................... 76
4-11 SPI-B Registers................................................................................................................... 76
4-12 SPI-C Registers .................................................................................................................. 77
4-13 SPI-D Registers .................................................................................................................. 77
4-14 I2C-A Registers................................................................................................................... 80
4-15 GPIO Registers .................................................................................................................. 82
4-16 F2808 GPIO MUX Table ........................................................................................................ 83
5-1 TMS320x280x, 2801x Peripheral Selection Guide .......................................................................... 87
6-1 TMS320F2809, TMS320F2808 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT........... 95
6-2 TMS320F2806 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT ............................. 96
6-3 TMS320F2802, TMS320F2801 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT........... 97
6-4 TMS320C2802, TMS320C2801 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT .......... 98
6-5 Typical Current Consumption by Various Peripherals (at 100 MHz) ..................................................... 99
6-6 TMS320x280x Clock Table and Nomenclature (100-MHz Devices)..................................................... 104
6-7 TMS320x280x/2801x Clock Table and Nomenclature (60-MHz Devices) .............................................. 104
6-8 Input Clock Frequency ......................................................................................................... 105
6-9 XCLKIN Timing Requirements - PLL Enabled ............................................................................. 105
6List of Tables Copyright © 2003–2012, Texas Instruments Incorporated

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com SPRS230N –OCTOBER 2003–REVISED MAY 2012
6-10 XCLKIN Timing Requirements - PLL Disabled ............................................................................. 105
6-11 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ...................................................... 105
6-12 Power Management and Supervisory Circuit Solutions ................................................................... 106
6-13 Reset (XRS) Timing Requirements .......................................................................................... 108
6-14 General-Purpose Output Switching Characteristics........................................................................ 109
6-15 General-Purpose Input Timing Requirements .............................................................................. 110
6-16 IDLE Mode Timing Requirements ........................................................................................... 112
6-17 IDLE Mode Switching Characteristics ....................................................................................... 112
6-18 STANDBY Mode Timing Requirements ..................................................................................... 113
6-19 STANDBY Mode Switching Characteristics ................................................................................ 113
6-20 HALT Mode Timing Requirements ........................................................................................... 114
6-21 HALT Mode Switching Characteristics ...................................................................................... 114
6-22 ePWM Timing Requirements ................................................................................................. 115
6-23 ePWM Switching Characteristics ............................................................................................ 115
6-24 Trip-Zone input Timing Requirements ....................................................................................... 115
6-25 High-Resolution PWM Characteristics at SYSCLKOUT = 60–100 MHz ................................................ 116
6-26 Enhanced Capture (eCAP) Timing Requirement .......................................................................... 116
6-27 eCAP Switching Characteristics ............................................................................................. 116
6-28 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements .................................................. 116
6-29 eQEP Switching Characteristics ............................................................................................. 116
6-30 External ADC Start-of-Conversion Switching Characteristics............................................................. 117
6-31 External Interrupt Timing Requirements .................................................................................... 117
6-32 External Interrupt Switching Characteristics ................................................................................ 117
6-33 I2C Timing ...................................................................................................................... 118
6-34 SPI Master Mode External Timing (Clock Phase = 0) .................................................................... 119
6-35 SPI Master Mode External Timing (Clock Phase = 1) .................................................................... 121
6-36 SPI Slave Mode External Timing (Clock Phase = 0) ...................................................................... 123
6-37 SPI Slave Mode External Timing (Clock Phase = 1) ...................................................................... 124
6-38 ADC Electrical Characteristics (over recommended operating conditions) ............................................ 125
6-39 ADC Power-Up Delays......................................................................................................... 126
6-40 Current Consumption for Different ADC Configurations (at 12.5-MHz ADCCLK) ..................................... 126
6-41 Sequential Sampling Mode Timing........................................................................................... 128
6-42 Simultaneous Sampling Mode Timing ....................................................................................... 129
6-43 Flash Endurance for A and S Temperature Material ...................................................................... 131
6-44 Flash Endurance for Q Temperature Material .............................................................................. 131
6-45 Flash Parameters at 100-MHz SYSCLKOUT............................................................................... 131
6-46 Flash/OTP Access Timing .................................................................................................... 132
6-47 Minimum Required Flash/OTP Wait-States at Different Frequencies ................................................... 132
6-48 ROM/OTP Access Timing .................................................................................................... 133
6-49 ROM/ROM (OTP area) Minimum Required Wait-States at Different Frequencies..................................... 133
9-1 F280x Thermal Model 100-pin GGM Results............................................................................... 136
9-2 F280x Thermal Model 100-pin PZ Results.................................................................................. 136
9-3 C280x Thermal Model 100-pin GGM Results............................................................................... 136
9-4 C280x Thermal Model 100-pin PZ Results.................................................................................. 136
9-5 F2809 Thermal Model 100-pin GGM Results .............................................................................. 136
9-6 F2809 Thermal Model 100-pin PZ Results ................................................................................. 137
Copyright © 2003–2012, Texas Instruments Incorporated List of Tables 7

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230N –OCTOBER 2003–REVISED MAY 2012 www.ti.com
Digital Signal Processors
Check for Samples: TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801,TMS320C2802,
TMS320C2801,TMS320F28016,TMS320F28015
1 F280x, F2801x, C280x DSPs
1.1 Features
1234
• High-Performance Static CMOS Technology • 128-Bit Security Key/Lock
– 100 MHz (10-ns Cycle Time) – Protects Flash/OTP/L0/L1 Blocks
– 60 MHz (16.67-ns Cycle Time) – Prevents Firmware Reverse Engineering
– Low-Power (1.8-V Core, 3.3-V I/O) Design • Three 32-Bit CPU Timers
• JTAG Boundary Scan Support (1) • Enhanced Control Peripherals
• High-Performance 32-Bit CPU ( TMS320C28x™) – Up to 16 PWM Outputs
– 16 x 16 and 32 x 32 MAC Operations – Up to 6 HRPWM Outputs With 150-ps MEP
Resolution
– 16 x 16 Dual MAC – Up to Four Capture Inputs
– Harvard Bus Architecture – Up to Two Quadrature Encoder Interfaces
– Atomic Operations – Up to Six 32-bit/Six 16-bit Timers
– Fast Interrupt Response and Processing • Serial Port Peripherals
– Unified Memory Programming Model – Up to 4 SPI Modules
– Code-Efficient (in C/C++ and Assembly) – Up to 2 SCI (UART) Modules
• On-Chip Memory – Up to 2 CAN Modules
– F2809: 128K x 16 Flash, 18K x 16 SARAM
F2808: 64K x 16 Flash, 18K x 16 SARAM – One Inter-Integrated-Circuit (I2C) Bus
F2806: 32K x 16 Flash, 10K x 16 SARAM • 12-Bit ADC, 16 Channels
F2802: 32K x 16 Flash, 6K x 16 SARAM – 2 x 8 Channel Input Multiplexer
F2801: 16K x 16 Flash, 6K x 16 SARAM – Two Sample-and-Hold
F2801x: 16K x 16 Flash, 6K x 16 SARAM – Single/Simultaneous Conversions
– 1K x 16 OTP ROM (Flash Devices Only) – Fast Conversion Rate:
– C2802: 32K x 16 ROM, 6K x 16 SARAM 80 ns - 12.5 MSPS (F2809 only)
C2801: 16K x 16 ROM, 6K x 16 SARAM 160 ns - 6.25 MSPS (280x)
• Boot ROM (4K x 16) 267 ns - 3.75 MSPS (F2801x)
– With Software Boot Modes (via SCI, SPI, – Internal or External Reference
CAN, I2C, and Parallel I/O) • Up to 35 Individually Programmable,
– Standard Math Tables Multiplexed GPIO Pins With Input Filtering
• Clock and System Control • Advanced Emulation Features
– Dynamic PLL Ratio Changes Supported – Analysis and Breakpoint Functions
– On-Chip Oscillator – Real-Time Debug via Hardware
– Watchdog Timer Module • Development Support Includes
• Any GPIO A Pin Can Be Connected to One of – ANSI C/C++ Compiler/Assembler/Linker
the Three External Core Interrupts – Code Composer Studio™ IDE
• Peripheral Interrupt Expansion (PIE) Block That – DSP/BIOS™
Supports All 43 Peripheral Interrupts – Digital Motor Control and Digital Power
• Endianness: Little Endian Software Libraries
• Low-Power Modes and Power Savings
– IDLE, STANDBY, HALT Modes Supported
– Disable Individual Peripheral Clocks
(1) IEEE Standard 1149.1-1990 Standard Test Access Port and
Boundary Scan Architecture
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2TMS320C28x, Code Composer Studio, DSP/BIOS, MicroStar BGA, C28x, TI, TMS320C2000 are trademarks of Texas
Instruments.
3eZdsp is a trademark of Spectrum Digital.
4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to
Copyright © 2003–2012, Texas Instruments Incorporated specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com SPRS230N –OCTOBER 2003–REVISED MAY 2012
• Package Options • Temperature Options
– Thin Quad Flatpack (PZ) – A: –40°C to 85°C (PZ, GGM, ZGM)
– MicroStar BGA™ (GGM, ZGM) – S: –40°C to 125°C (PZ, GGM, ZGM)
– Q: –40°C to 125°C (PZ)
1.2 Getting Started
This section gives a brief overview of the steps to take when first developing for a C28x™ device. For
more detail on each of these steps, see the following:
•Getting Started With TMS320C28x Digital Signal Controllers (literature number SPRAAM0).
• C2000 Getting Started Website (http://www.ti.com/c2000getstarted)
Step 1. Acquire the appropriate development tools
The quickest way to begin working with a C28x device is to acquire an eZdsp™ kit for initial
development, which, in one package, includes:
• On-board JTAG emulation via USB or parallel port
• Appropriate emulation driver
• Code Composer Studio™ IDE for eZdsp
Once you have become familiar with the device and begin developing on your own
hardware, purchase Code Composer Studio™ IDE separately for software development and
a JTAG emulation tool to get started on your project.
Step 2. Download starter software
To simplify programming for C28x devices, it is recommended that users download and use
the C/C++ Header Files and Example(s) to begin developing software for the C28x devices
and their various peripherals.
After downloading the appropriate header file package for your device, refer to the following
resources for step-by-step instructions on how to run the peripheral examples and use the
header file structure for your own software
• The Quick Start Readme in the /doc directory to run your first application.
•Programming TMS320x28xx and 28xxx Peripherals in C/C++ Application Report
(literature number SPRAA85)
Step 3. Download flash programming software
Many C28x devices include on-chip flash memory and tools that allow you to program the
flash with your software IP.
• Flash Tools: C28x Flash Tools
•TMS320F281x™ Flash Programming Solutions (literature number SPRB169)
•Running an Application from Internal Flash Memory on the TMS320F28xxx DSP
(literature number SPRA958)
Step 4. Move on to more advanced topics
For more application software and other advanced topics, visit the TI™ website at
http://www.ti.com or http://www.ti.com/c2000getstarted.
Copyright © 2003–2012, Texas Instruments Incorporated F280x, F2801x, C280x DSPs 9
Submit Documentation Feedback
Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230N –OCTOBER 2003–REVISED MAY 2012 www.ti.com
2 Introduction
The TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320F28015,
TMS320F28016, TMS320C2802, and TMS320C2801 devices, members of the TMS320C28x™ DSP
generation, are highly integrated, high-performance solutions for demanding control applications.
Throughout this document, TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802,
TMS320F2801, TMS320C2802, TMS320C2801, TMS320F28015, and TMS320F28016 are abbreviated as
F2809, F2808, F2806, F2802, F2801, C2802, C2801, F28015, and F28016, respectively. TMS320F28015
and TMS320F28016 are abbreviated as F2801x. Table 2-1 provides a summary of features for each
device.
10 Introduction Copyright © 2003–2012, Texas Instruments Incorporated
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TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com SPRS230N –OCTOBER 2003–REVISED MAY 2012
Table 2-1. Hardware Features (100-MHz Devices)
FEATURE TYPE(1) F2809 F2808 F2806 F2802 F2801 C2802 C2801
Instruction cycle (at 100 MHz) – 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns
18K 18K 10K 6K 6K 6K 6K
Single-access RAM (SARAM) (16-bit word) – (L0, L1, M0, M1, (L0, L1, M0, M1, (L0, L1, M0, M1) (L0, M0, M1) (L0, M0, M1) (L0, M0, M1) (L0, M0, M1)
H0) H0)
3.3-V on-chip flash (16-bit word) – 128K 64K 32K 32K 16K – –
On-chip ROM (16-bit word) – – – – – – 32K 16K
Code security for on-chip flash/SARAM/OTP blocks – Yes Yes Yes Yes Yes Yes Yes
Boot ROM (4K x 16) – Yes Yes Yes Yes Yes Yes Yes
One-time programmable (OTP) ROM – 1K 1K 1K 1K 1K – –
(16-bit word)
PWM outputs 0 ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6 ePWM1/2/3 ePWM1/2/3 ePWM1/2/3 ePWM1/2/3
ePWM1A/2A/3A/ ePWM1A/2A/ ePWM1A/2A/
HRPWM channels 0 ePWM1A/2A/3A ePWM1A/2A/3A ePWM1A/2A/3A ePWM1A/2A/3A
4A/5A/6A 3A/4A 3A/4A
32-bit CAPTURE inputs or auxiliary PWM outputs 0 eCAP1/2/3/4 eCAP1/2/3/4 eCAP1/2/3/4 eCAP1/2 eCAP1/2 eCAP1/2 eCAP1/2
32-bit QEP channels (four inputs/channel) 0 eQEP1/2 eQEP1/2 eQEP1/2 eQEP1 eQEP1 eQEP1 eQEP1
Watchdog timer – Yes Yes Yes Yes Yes Yes Yes
12-Bit, 16-channel ADC conversion time 1 80 ns 160 ns 160 ns 160 ns 160 ns 160 ns 160 ns
32-Bit CPU timers – 3 3 3 3 3 3 3
Serial Peripheral Interface (SPI) 0 SPI-A/B/C/D SPI-A/B/C/D SPI-A/B/C/D SPI-A/B SPI-A/B SPI-A/B SPI-A/B
Serial Communications Interface (SCI) 0 SCI-A/B SCI-A/B SCI-A/B SCI-A SCI-A SCI-A SCI-A
Enhanced Controller Area Network (eCAN) 0 eCAN-A/B eCAN-A/B eCAN-A eCAN-A eCAN-A eCAN-A eCAN-A
Inter-Integrated Circuit (I2C) 0 I2C-A I2C-A I2C-A I2C-A I2C-A I2C-A I2C-A
Digital I/O pins (shared) – 35 35 35 35 35 35 35
External interrupts – 3 3 3 3 3 3 3
Supply voltage 1.8-V Core, 3.3-V I/O – Yes Yes Yes Yes Yes Yes Yes
100-Pin PZ – Yes Yes Yes Yes Yes Yes Yes
Packaging 100-Ball GGM, ZGM – Yes Yes Yes Yes Yes Yes Yes
A: –40°C to 85°C – (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM)
Temperature options S: –40°C to 125°C – (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM)
Q: –40°C to 125°C – (PZ) (PZ) (PZ) (PZ) (PZ) (PZ) (PZ)
Product status(2) – TMS TMS TMS TMS TMS TMS TMS
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the
basic functionality of the module. These device-specific differences are listed in the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) and in the
peripheral reference guides.
(2) See Section 5.1, Device and Development Support Tool Nomenclature, for descriptions of device stages.
Copyright © 2003–2012, Texas Instruments Incorporated Introduction 11
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TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230N –OCTOBER 2003–REVISED MAY 2012 www.ti.com
Table 2-2. Hardware Features (60-MHz Devices)
FEATURE TYPE(1) F2802-60 F2801-60 F28016 F28015
Instruction cycle (at 60 MHz) – 16.67 ns 16.67 ns 16.67 ns 16.67 ns
6K 6K 6K 6K
Single-access RAM (SARAM) (16-bit word) – (L0, M0, M1) (L0, M0, M1) (L0, M0, M1) (L0, M0, M1)
3.3-V on-chip flash (16-bit word) – 32K 16K 16K 16K
On-chip ROM (16-bit word) – – – – –
Code security for on-chip flash/SARAM/OTP blocks – Yes Yes Yes Yes
Boot ROM (4K x 16) – Yes Yes Yes Yes
One-time programmable (OTP) ROM – 1K 1K 1K 1K
(16-bit word)
PWM outputs 0 ePWM1/2/3 ePWM1/2/3 ePWM1/2/3/4 ePWM1/2/3/4
HRPWM channels 0 ePWM1A/2A/3A ePWM1A/2A/3A ePWM1A/2A/3A/4A ePWM1A/2A/3A/4A
32-bit CAPTURE inputs or auxiliary PWM outputs 0 eCAP1/2 eCAP1/2 eCAP1/2 eCAP1/2
32-bit QEP channels (four inputs/channel) 0 eQEP1 eQEP1 - -
Watchdog timer – Yes Yes Yes Yes
No. of channels 16 16 16 16
12-Bit ADC MSPS 1 3.75 3.75 3.75 3.75
Conversion time 267 ns 267 ns 267 ns 267 ns
32-Bit CPU timers – 3 3 3 3
Serial Peripheral Interface (SPI) 0 SPI-A/B SPI-A/B SPI-A SPI-A
Serial Communications Interface (SCI) 0 SCI-A SCI-A SCI-A SCI-A
Enhanced Controller Area Network (eCAN) 0 eCAN-A eCAN-A eCAN-A -
Inter-Integrated Circuit (I2C) 0 I2C-A I2C-A I2C-A I2C-A
Digital I/O pins (shared) – 35 35 35 35
External interrupts – 3 3 3 3
1.8-V Core, 1.8-V Core, 1.8-V Core, 1.8-V Core,
Supply voltage – 3.3-V I/O 3.3-V I/O 3.3-V I/O 3.3-V I/O
100-Pin PZ – Yes Yes Yes Yes
Packaging 100-Ball GGM, ZGM – Yes Yes Yes Yes
A: –40°C to 85°C – (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM)
Temperature options S: –40°C to 125°C – (PZ GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM)
Q: –40°C to 125°C – (PZ) (PZ) (PZ) (PZ)
Product status(2) – TMS TMS TMS TMS
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the
basic functionality of the module. These device-specific differences are listed in the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) and in the
peripheral reference guides.
(2) See Section 5.1, Device and Development Support Tool Nomenclature, for descriptions of device stages.
12 Introduction Copyright © 2003–2012, Texas Instruments Incorporated
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Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015

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GPIO0/EPWM1A
XRS
TRST
VDD2A18
VSS2AGND
VDDAIO
GPIO13/ /CANRXB/SPISOMIBTZ2
VDD3VFL
VDD
VDD
VDDIO
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
GPIO26/ECAP3/EQEP2I/SPICLKB
TEST2
TEST1
GPIO25/ECAP2/EQEP2B/SPISOMIB
XCLKIN
X1
X2
EMU1
EMU0
GPIO24/ECAP1/EQEP2A/SPISIMOB
GPIO27/ECAP4/EQEP2S/SPISTEB
TDO
TCK
GPIO12/ /CANTXB/SPISIMOBTZ1
GPIO14/ /SCITXDB/SPICLKBTZ3
GPIO15/ /SCIRXDB/SPISTEBTZ4
GPIO30/CANRXA
ADCINA3
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA2
ADCINA1
ADCINA0
ADCLO
GPIO31/CANTXA
GPIO29/SCITXDA//TZ6
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
GPIO4/EPWM3A
GPIO17/SPISOMIA/CANRXB/TZ6
GPIO5/EPWM3B/SPICLKD/ECAP1
GPIO18/SPICLKA/SCITXDB GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO
GPIO19/SPISTEA/SCIRXDB
GPIO7/EPWM4B/SPISTED/ECAP2 GPIO9/EPWM5B/SCITXDB/ECAP3 GPIO20/EQEP1A/SPISIMOC/CANTXB
GPIO10/EPWM6A/CANRXB/ADCSOCBO
GPIO8/EPWM5A/CANTXB/ADCSOCAO XCLKOUT
GPIO21/EQEP1B/SPISOMIC/CANRXB
VSS
VSS VSS
VSS VSS
VSS1AGND
VSSA2
VSSAIO
VDD
VDDA2
VDD1A18
VDDIO
VDD VDD VDDIO
GPIO11/EPWM6B/SCIRXDB/ECAP4
GPIO22/EQEP1S/SPICLKC/SCITXDB TMS
TDI
GPIO23/EQEP1I/SPISTEC/SCIRXDB
ADCINB0
ADCINB1
ADCINB2
ADCINB3
ADCINB7
ADCINB6
ADCINB5
ADCINB4
ADCREFIN
ADCREFM
ADCREFP
ADCRESEXT
GPIO34
GPIO1/EPWM1B/SPISIMOD
GPIO2/EPWM2A
GPIO3/EPWM2B/SPISOMID
GPIO16/SPISIMOA/CANTXB/TZ5
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
GPIO28/SCIRXDA/TZ5
TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com SPRS230N –OCTOBER 2003–REVISED MAY 2012
2.1 Pin Assignments
The TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28015, and TMS320F28016 100-pin PZ low-profile quad flatpack (LQFP) pin
assignments are shown in Figure 2-1,Figure 2-2,Figure 2-3, and Figure 2-4. The 100-ball GGM and ZGM
ball grid array (BGA) terminal assignments are shown in Figure 2-5.Table 2-3 describes the function(s) of
each pin.
Figure 2-1. TMS320F2809, TMS320F2808 100-Pin PZ LQFP (Top View)
Copyright © 2003–2012, Texas Instruments Incorporated Introduction 13
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TMS320C2801 TMS320F28016 TMS320F28015

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GPIO0/EPWM1A
XRS
TRST
VDD2A18
VSS2AGND
VDDAIO
GPIO13/ /SPISOMIBTZ2
VDD3VFL
VDD
VDD
VDDIO
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
GPIO26/ECAP3/EQEP2I/SPICLKB
TEST2
TEST1
GPIO25/ECAP2/EQEP2B/SPISOMIB
XCLKIN
X1
X2
EMU1
EMU0
GPIO24/ECAP1/EQEP2A/SPISIMOB
GPIO27/ECAP4/EQEP2S/SPISTEB
TDO
TCK
GPIO12/ /SPISIMOBTZ1
GPIO14/ /SCITXDB/SPICLKBTZ3
GPIO15/ /SCIRXDB/SPISTEBTZ4
GPIO30/CANRXA
ADCINA3
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA2
ADCINA1
ADCINA0
ADCLO
GPIO31/CANTXA
GPIO29/SCITXDA//TZ6
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
GPIO4/EPWM3A
GPIO17/SPISOMIA/TZ6
GPIO5/EPWM3B/SPICLKD/ECAP1
GPIO18/SPICLKA/SCITXDB GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO
GPIO19/SPISTEA/SCIRXDB
GPIO7/EPWM4B/SPISTED/ECAP2 GPIO9/EPWM5B/SCITXDB/ECAP3 GPIO20/EQEP1A/SPISIMOC
GPIO10/EPWM6A/ADCSOCBO
GPIO8/EPWM5A/ADCSOCAO XCLKOUT
GPIO21/EQEP1B/SPISOMIC
VSS
VSS VSS
VSS VSS
VSS1AGND
VSSA2
VSSAIO
VDD
VDDA2
VDD1A18
VDDIO
VDD VDD VDDIO
GPIO11/EPWM6B/SCIRXDB/ECAP4
GPIO22/EQEP1S/SPICLKC/SCITXDB TMS
TDI
GPIO23/EQEP1I/SPISTEC/SCIRXDB
ADCINB0
ADCINB1
ADCINB2
ADCINB3
ADCINB7
ADCINB6
ADCINB5
ADCINB4
ADCREFIN
ADCREFM
ADCREFP
ADCRESEXT
GPIO34
GPIO1/EPWM1B/SPISIMOD
GPIO2/EPWM2A
GPIO3/EPWM2B/SPISOMID
GPIO16/SPISIMOA/TZ5
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
GPIO28/SCIRXDA/TZ5
TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230N –OCTOBER 2003–REVISED MAY 2012 www.ti.com
Figure 2-2. TMS320F2806 100-Pin PZ LQFP (Top View)
14 Introduction Copyright © 2003–2012, Texas Instruments Incorporated
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TMS320C2801 TMS320F28016 TMS320F28015

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GPIO0/EPWM1A
XRS
TRST
VDD2A18
VSS2AGND
VDDAIO
SPISOMIB/GPIO13/TZ2
VDD3VFL
(A)
VDD
VDD
VDDIO
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
SPICLKB/GPIO26
TEST2
TEST1
GPIO25/ECAP2/SPISOMIB
XCLKIN
X1
X2
EMU1
EMU0
SPISIMOB/GPIO24/ECAP1
SPISTEB/GPIO27
TDO
TCK
SPISIMOB/GPIO12/TZ1
SPICLKB/GPIO14/TZ3
SPISTEB/GPIO15/TZ4
GPIO30/CANRXA
ADCINA3
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA2
ADCINA1
ADCINA0
ADCLO
GPIO31/CANTXA
GPIO29/SCITXDA//TZ6
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
GPIO4/EPWM3A
GPIO17/SPISOMIA/TZ6
GPIO5/EPWM3B/ECAP1
GPIO18/SPICLKA GPIO6/EPWMSYNCI/EPWMSYNCO
GPIO19/SPISTEA
GPIO7/ECAP2 GPIO9 GPIO20/EQEP1A
GPIO10/ADCSOCBO
GPIO8/ADCSOCAO XCLKOUT
GPIO21/EQEP1B
VSS
VSS VSS
VSS VSS
VSS1AGND
VSSA2
VSSAIO
VDD
VDDA2
VDD1A18
VDDIO
VDD VDD VDDIO
GPIO11
GPIO22/EQEP1S TMS
TDI
GPIO23/EQEP1I
ADCINB0
ADCINB1
ADCINB2
ADCINB3
ADCINB7
ADCINB6
ADCINB5
ADCINB4
ADCREFIN
ADCREFM
ADCREFP
ADCRESEXT
GPIO34
GPIO1/EPWM1B
GPIO2/EPWM2A
GPIO3/EPWM2B
GPIO16/SPISIMOA/TZ5
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
GPIO28/SCIRXDA/TZ5
TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com SPRS230N –OCTOBER 2003–REVISED MAY 2012
A. On the C280x devices, the VDD3VFL pin is VDDIO.
Figure 2-3. TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801 100-Pin PZ LQFP (Top View)
Copyright © 2003–2012, Texas Instruments Incorporated Introduction 15
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TMS320C2801 TMS320F28016 TMS320F28015

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GPIO0/EPWM1A
XRS
TRST
VDD2A18
VSS2AGND
VDDAIO
GPIO13/TZ2
VDD3VFL
VDD
VDD
VDDIO
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
GPIO26
TEST2
TEST1
GPIO25/ECAP2
XCLKIN
X1
X2
EMU1
EMU0
GPIO24/ECAP1
GPIO27
TDO
TCK
GPIO12/TZ1 GPIO14/TZ3 GPIO15/TZ4
GPIO30/CANRXA(A)
ADCINA3
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA2
ADCINA1
ADCINA0
ADCLO
GPIO31/CANTXA(A)
GPIO29/SCITXDA//TZ6
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
GPIO4/EPWM3A
GPIO17/SPISOMIA/TZ6
GPIO5/EPWM3B/ECAP1
GPIO18/SPICLKA GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO
GPIO19/SPISTEA
GPIO7/EPWM4B/ECAP2 GPIO9 GPIO20
GPIO10/ADCSOCBO
GPIO8/ADCSOCAO XCLKOUT
GPIO21
VSS
VSS VSS
VSS VSS
VSS1AGND
VSSA2
VSSAIO
VDD
VDDA2
VDD1A18
VDDIO
VDD VDD VDDIO
GPIO11
GPIO22 TMS
TDI
GPIO23
ADCINB0
ADCINB1
ADCINB2
ADCINB3
ADCINB7
ADCINB6
ADCINB5
ADCINB4
ADCREFIN
ADCREFM
ADCREFP
ADCRESEXT
GPIO34
GPIO1/EPWM1B
GPIO2/EPWM2A
GPIO3/EPWM2B
GPIO16/SPISIMOA/TZ5
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
GPIO28/SCIRXDA/TZ5
TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230N –OCTOBER 2003–REVISED MAY 2012 www.ti.com
A. CANTXA (pin 7) and CANRXA (pin 6) pins are not applicable for the TMS320F28015.
Figure 2-4. TMS320F2801x 100-Pin PZ LQFP (Top View)
16 Introduction Copyright © 2003–2012, Texas Instruments Incorporated
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TMS320C2801 TMS320F28016 TMS320F28015

4
C
B
A
D
E
21 3
K
F
G
H
J
57 698 10
Bottom View
TRST TCK
TDI
TDO TMS
EMU0
EMU1
VDD3VFL
TEST1
TEST2
XCLKOUT
XCLKIN
X1
X2
XRS
GPIO0GPIO1
GPIO2 GPIO3 GPIO4
GPIO5
GPIO6GPIO7
GPIO9 GPIO8
GPIO10
GPIO11
GPIO12 GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23GPIO24GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30GPIO31
GPIO32
GPIO33
GPIO34
VDDA2
VDD1A18 VSS1AGND
VSSAIO
VDDAIO
VSSA2 ADCINA7
VSS2AGND
VDD2A18
VDD
VDD
VDD
VDD
VDD VDD
VDDIO
VDDIO
VDDIO
VDDIO
VSS VSS
VSS
VSS VSS VSS
VSS
VSS VSS
VSS
VSS
ADCINB2
ADCINA6
ADCINA5ADCINA4 ADCINA3 ADCINA2
ADCINA1 ADCINA0
ADCINB7
ADCINB1
ADCINB0
ADCLO
ADCRESEXT
ADCREFIN
ADCREFP
ADCREFM
ADCINB3 ADCINB5
ADCINB4
ADCINB6
TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com SPRS230N –OCTOBER 2003–REVISED MAY 2012
Figure 2-5. TMS320F2809, TMS320F2808, TMS320F2806,TMS320F2802, TMS320F2801,
TMS320F28016, TMS320F28015, TMS320C2802, TMS320C2801
100-Ball GGM and ZGM MicroStar BGA™ (Bottom View)
Copyright © 2003–2012, Texas Instruments Incorporated Introduction 17
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Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230N –OCTOBER 2003–REVISED MAY 2012 www.ti.com
2.2 Signal Descriptions
Table 2-3 describes the signals on the 280x devices. All digital inputs are TTL-compatible. All outputs are
3.3 V with CMOS levels. Inputs are not 5-V tolerant.
Table 2-3. Signal Descriptions
PIN NO.
GGM/
NAME DESCRIPTION (1)
PZ ZGM
PIN # BALL #
JTAG
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of
the operations of the device. If this signal is not connected or driven low, the device operates in its
functional mode, and the test reset signals are ignored.
NOTE: Do not use pullup resistors on TRST; it has an internal pull-down device. TRST is an active
TRST 84 A6 high test pin and must be maintained low at all times during normal device operation. An external
pulldown resistor is required on this pin. The value of this resistor should be based on drive strength
of the debugger pods applicable to the design. A 2.2-kΩresistor generally offers adequate
protection. Since this is application-specific, it is recommended that each target board be validated
for proper operation of the debugger and the application. (I, ↓)
TCK 75 A10 JTAG test clock with internal pullup (I, ↑)
JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP
TMS 74 B10 controller on the rising edge of TCK. (I, ↑)
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction
TDI 73 C9 or data) on a rising edge of TCK. (I, ↑)
JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data)
TDO 76 B9 are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)
Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
EMU0 80 A8 (I/O/Z, 8 mA drive ↑)
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩto 4.7-kΩ
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.
Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
EMU1 81 B7 (I/O/Z, 8 mA drive ↑)
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩto 4.7-kΩ
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.
FLASH
3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times. On the ROM
VDD3VFL 96 C4 parts (C280x), this pin should be connected to VDDIO.
TEST1 97 A3 Test Pin. Reserved for TI. Must be left unconnected. (I/O)
TEST2 98 B3 Test Pin. Reserved for TI. Must be left unconnected. (I/O)
CLOCK
Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the
frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by the bits 1, 0
XCLKOUT 66 E8 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal
can be turned off by setting XCLKOUTDIV to 3. Unlike other GPIO pins, the XCLKOUT pin is not
placed in high-impedance state during a reset. (O/Z, 8 mA drive).
External Oscillator Input. This pin is used to feed a clock from an external 3.3-V oscillator. In this
XCLKIN 90 B5 case, tie the X1 pin to GND. Alternately, when a crystal/resonator is used (or if an external 1.8-V
oscillator is fed into the X1 pin), tie the XCLKIN pin to GND. (I)
(1) I = Input, O = Output, Z = High impedance, OD = Open drain, ↑= Pullup, ↓= Pulldown
18 Introduction Copyright © 2003–2012, Texas Instruments Incorporated
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TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com SPRS230N –OCTOBER 2003–REVISED MAY 2012
Table 2-3. Signal Descriptions (continued)
PIN NO.
GGM/
NAME DESCRIPTION (1)
PZ ZGM
PIN # BALL #
Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramic
resonator may be connected across X1 and X2. The X1 pin is referenced to the 1.8-V core digital
X1 88 E6 power supply. A 1.8-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN
pin must be connected to ground. If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must
be tied to GND. (I)
Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 and
X2 86 C6 X2. If X2 is not used it must be left unconnected. (O)
RESET
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the address
contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the
location pointed to by the PC. This pin is driven low by the DSP when a watchdog reset occurs.
XRS 78 B8 During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK
cycles. (I/OD, ↑)
The output buffer of this pin is an open-drain with an internal pullup. It is recommended that this pin
be driven by an open-drain device.
ADC SIGNALS
ADCINA7 16 F3 ADC Group A, Channel 7 input (I)
ADCINA6 17 F4 ADC Group A, Channel 6 input (I)
ADCINA5 18 G4 ADC Group A, Channel 5 input (I)
ADCINA4 19 G1 ADC Group A, Channel 4 input (I)
ADCINA3 20 G2 ADC Group A, Channel 3 input (I)
ADCINA2 21 G3 ADC Group A, Channel 2 input (I)
ADCINA1 22 H1 ADC Group A, Channel 1 input (I)
ADCINA0 23 H2 ADC Group A, Channel 0 input (I)
ADCINB7 34 K5 ADC Group B, Channel 7 input (I)
ADCINB6 33 H4 ADC Group B, Channel 6 input (I)
ADCINB5 32 K4 ADC Group B, Channel 5 input (I)
ADCINB4 31 J4 ADC Group B, Channel 4 input (I)
ADCINB3 30 K3 ADC Group B, Channel 3 input (I)
ADCINB2 29 H3 ADC Group B, Channel 2 input (I)
ADCINB1 28 J3 ADC Group B, Channel 1 input (I)
ADCINB0 27 K2 ADC Group B, Channel 0 input (I)
ADCLO 24 J1 Low Reference (connect to analog ground) (I)
ADCRESEXT 38 F5 ADC External Current Bias Resistor. Connect a 22-kΩresistor to analog ground.
ADCREFIN 35 J5 External reference input (I)
Internal Reference Positive Output. Requires a low ESR (under 1.5 Ω) ceramic bypass capacitor of
2.2 μF to analog ground. (O)
ADCREFP 37 G5 NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data sheet that is
used in the system.
Internal Reference Medium Output. Requires a low ESR (under 1.5 Ω) ceramic bypass capacitor of
2.2 μF to analog ground. (O)
ADCREFM 36 H5 NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data sheet that is
used in the system.
Copyright © 2003–2012, Texas Instruments Incorporated Introduction 19
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TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230N –OCTOBER 2003–REVISED MAY 2012 www.ti.com
Table 2-3. Signal Descriptions (continued)
PIN NO.
GGM/
NAME DESCRIPTION (1)
PZ ZGM
PIN # BALL #
CPU AND I/O POWER PINS
VDDA2 15 F2 ADC Analog Power Pin (3.3 V)
VSSA2 14 F1 ADC Analog Ground Pin
VDDAIO 26 J2 ADC Analog I/O Power Pin (3.3 V)
VSSAIO 25 K1 ADC Analog I/O Ground Pin
VDD1A18 12 E4 ADC Analog Power Pin (1.8 V)
VSS1AGND 13 E5 ADC Analog Ground Pin
VDD2A18 40 J6 ADC Analog Power Pin (1.8 V)
VSS2AGND 39 K6 ADC Analog Ground Pin
VDD 10 E2
VDD 42 G6
VDD 59 F10 CPU and Logic Digital Power Pins (1.8 V)
VDD 68 D7
VDD 85 B6
VDD 93 D4
VDDIO 3 C2
VDDIO 46 H7 Digital I/O Power Pin (3.3 V)
VDDIO 65 E9
VDDIO 82 A7
VSS 2 B1
VSS 11 E3
VSS 41 H6
VSS 49 K9
VSS 55 H10
VSS 62 F7 Digital Ground Pins
VSS 69 D10
VSS 77 A9
VSS 87 D6
VSS 89 A5
VSS 94 A4
GPIOA AND PERIPHERAL SIGNALS(1) (2)
GPIO0 General-purpose input/output 0 (I/O/Z) (3)
EPWM1A Enhanced PWM1 Output A and HRPWM channel (O)
47 K8
- -
- -
GPIO1 General-purpose input/output 1 (I/O/Z)(3)
EPWM1B Enhanced PWM1 Output B (O)
44 K7
SPISIMOD SPI-D slave in, master out (I/O) (not available on 2801, 2802)
- -
GPIO2 General-purpose input/output 2 (I/O/Z)(3)
EPWM2A Enhanced PWM2 Output A and HRPWM channel (O)
45 J7
- -
- -
(1) Some peripheral functions may not be available in TMS320F2801x devices. See Table 2-2 for details.
(2) All GPIO pins are I/O/Z, 4-mA drive typical (unless otherwise indicated), and have an internal pullup, which can be selectively
enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The GPIO function (shown in Italics) is the default at
reset. The peripheral signals that are listed under them are alternate functions.
(3) The pullups on GPIO0-GPIO11 pins are not enabled at reset.
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Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015