Texas Instruments TMS320C6000 Series User manual

TMS320C6000
CPU and Instruction Set
Reference Guide
Literature Number: SPRU189D
March 1999
Printed on Recycled Paper

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Copyright 1999, Texas Instruments Incorporated

iii Contents
Preface
Read This First
About This Manual
ThisreferenceguidedescribestheCPUarchitecture,pipeline,instructionset,
andinterruptsfortheTMS320C6000digitalsignalprocessors(DSPs).Unless
otherwise specified, all references to the ’C6000 refer to the TMS320C6000
platform of DSPs, ’C62x refers to the TMS320C62x fixed-point DSPs in the
’C6000 platform, and ’C67x refers to the TMS320C67x floating-point DSPs in
the ’C6000 platform.
How to Use This Manual
UsethismanualasareferenceforthearchitectureoftheTMS320C6000CPU.
First-time readers should read Chapter 1 for general information about TI
DSPs, the features of the ’C6000, and the applications for which the ’C6000
is best suited.
Read chapters 2, 5, 6, and 7 to grasp the concepts of the architecture. Chap-
ter 3 and Chapter 4 contain detailed information about each instruction and is
best used as reference material; however, you may want to read sections 3.1
through 3.9 and sections 4.1 through 4.6 for general information about the
instruction set and to understand the instruction descriptions, then browse
through Chapter 3 and Chapter 4 to familiarize yourself with the instructions.

iv
The following table gives chapter references for specific information:
If you are looking for in-
formation about: Turn to these chapters:
Addressing modes Chapter 3, TMS320C62x/C67x Fixed-Point
Instruction Set
Chapter 4, TMS320C67x Floating-Point
Instruction Set
Conditional operations Chapter 3, TMS320C62x/C67x Fixed-Point
Instruction Set
Chapter 4, TMS320C67x Floating-Point
Instruction Set
Control registers Chapter 2, CPU Data Paths and Control
CPU architecture and data
paths Chapter 2,
CPU Data Paths and Control
Delay slots Chapter 3, TMS320C62x/C67x Fixed-Point
Instruction Set
Chapter 4, TMS320C67x Floating-Point
Instruction Set
Chapter 5, TMS320C62x Pipeline
Chapter 6, TMS320C67x Pipeline
General-purpose register files Chapter 2, CPU Data Paths and Control
Instruction set Chapter 3, TMS320C62x/C67x Fixed-Point
Instruction Set
Chapter 4, TMS320C67x Floating-Point
Instruction Set
Interrupts and control registers Chapter 7, Interrupts
Parallel operations Chapter 3, TMS320C62x/C67x Fixed-Point
Instruction Set
Chapter 4, TMS320C67x Floating-Point
Instruction Set
Pipeline phases and operation Chapter 5, TMS320C62x Pipeline
Chapter 6, TMS320C67x Pipeline
Reset Chapter 7, Interrupts
Ifyouareinterestedintopicsthatarenotlistedhere,check RelatedDocumen-
tation From Texas Instruments
, on page vi, for brief descriptions of other
’C6x-related books that are available.
Read This First

v
Notational Conventions
This document uses the following conventions:
-Program listings and program examples are shown in a special font.
Here is a sample program listing:
LDW .D1 *A0,A1
ADD .L1 A1,A2,A3
NOP 3
MPY .M1 A1,A4,A5
-To help you easily recognize instructions and parameters throughout the
book, instructions are in bold face and parameters are in italics (except
in program listings).
-Ininstruction syntaxes, portions of a syntax that are in bold should be en-
tered as shown; portions of a syntax that are in italics describe the type of
information that should be entered. Here is an example of an instruction:
MPY
src1,src2,dst
MPY is the instruction mnemonic. When you use MPY, you must supply
two source operands ( src1 and src2 ) and a destination operand ( dst ) of
appropriate types as defined in Chapter 3,
TMS320C62x/C67x Fixed-
Point Instruction Set .
Although the instruction mnemonic (MPY in this example) is in capital let-
ters,the’C6xassembler isnotcasesensitive —itcanassemblemnemon-
ics entered in either upper or lower case.
-Squarebrackets,[and ], and parentheses,(and), are used to identifyop-
tional items. If you use an optional item, you must specify the information
withinbrackets or parentheses;however, youdo not enterthe brackets or
parenthesesthemselves.Hereisanexampleofaninstructionthathasop-
tional items.
[ label ] EXTU ( .unit ) src2, csta, cstb, dst
The EXTU instruction is shown with a label and several parameters. The
[ label ] and the parameter ( .unit ) are optional. The parameters src2, csta,
cstb, and dst are not optional.
-Throughout this book MSB means most significant bit and LSB means
least significant bit .
-A special icon is used to indicate material that applies only to the floating-
point (’C67x) DSP:
Notational Conventions
Read This First

vi
Related Documentation From Texas Instruments
ThefollowingbooksdescribetheTMS320C6xgenerationandrelatedsupport
tools. To obtain a copy of any of these TI documents, call the Texas Instru-
mentsLiteratureResponseCenterat(800)477–8924.Whenordering,please
identify the book by its title and literature number.
TMS320C62x/C67x Technical Brief (literature number SPRU197) gives an
introduction to the ’C62x/C67x digital signal processors, development
tools, and third-party support.
TMS320C6201 Digital Signal Processor Data Sheet (literature number
SPRS051) describes the features of the TMS320C6201 and provides
pinouts, electrical specifications, and timings for the device.
TMs320C6202 Digital Signal Processor Data Sheet (literature number
SPRS072)describesthefeaturesoftheTMS320C6202fixed-pointDSP
and provides pinouts, electrical specifications, and timings for the de-
vice.
TMS320C6211 Digital Signal Processor Data Sheet (literature number
SPRS073)describesthefeaturesoftheTMS320C6211fixed-pointDSP
and provides pinouts, electrical specifications, and timings for the de-
vice.
TMS320C6701 Digital Signal Processor Data Sheet (literature number
SPRS067) describes the features of the TMS320C6701 floating-point
DSP and provides pinouts, electrical specifications, and timings for the
device.
TMS320C6000 Peripherals Reference Guide (literature number SPRU190)
describes common peripherals available on the TMS320C6000 digital
signal processors. This book includes information on the internal data
and program memories, the external memory interface (EMIF), the host
port, serial ports, direct memory access (DMA), clocking and phase-
locked loop (PLL), and the power-down modes.
TMS320C62x/C67x Programmer’s Guide (literature number SPRU198)
describes ways to optimize C and assembly code for the
TMS320C62x/C67x DSPs and includes application program examples.
TMS320C6000AssemblyLanguageToolsUser’sGuide (literaturenumber
SPRU186) describes the assembly language tools (assembler, linker,
and other tools used to develop assembly language code), assembler
directives, macros, common object file format, and symbolic debugging
directives for the ’C6000 generation of devices.
Related Documentation From Texas Instruments

vii
TMS320C6000 Optimizing C Compiler User’s Guide (literature number
SPRU187)describesthe’C6000Ccompilerandtheassemblyoptimizer.
ThisCcompileracceptsANSIstandardCsourcecodeandproducesas-
semblylanguagesourcecodeforthe’C6000 generation of devices. The
assembly optimizer helps you optimize your assembly code.
TMS320 Third-Party Support Reference Guide (literature number
SPRU052)alphabetically listsover 100 third partiesthat provide various
products that serve the family of TMS320 digital signal processors. A
myriadofproductsandapplicationsareoffered—softwareandhardware
development tools, speech recognition, image processing, noise can-
cellation, modems, etc.
Trademarks
TI,XDS510,VelociTI, and320HotlineOn-linearetrademarks ofTexasInstru-
ments Incorporated.
Windows and Windows NT are registered trademarks of Microsoft Corpora-
tion.
Related Documentation From Texas Instruments / Trademarks
Read This First

viii
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book.
If You Need Assistance

Contents
ix
Contents
Summarizes the features of the TMS320 family of products and presents typical applications.
Describes the TMS320C62x/C67x DSPs and lists their key features.
1 Introduction 1Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summarizes the features of the TMS320 family of products and presents typical applications.
Describes the TMS320C62xx DSP and lists its key features.
1.1 TMS320 Family Overview 1Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.1 History of TMS320 DSPs 1Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.2 Typical Applications for the TMS320 Family 1Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Overview of the TMS320C6x Generation of Digital Signal Processors 1Ć4. . . . . . . . . . . . .
1.3 Features and Options of the TMS320C62x/C67x 1Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 TMS320C62x/C67x Architecture 1Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.1 Central Processing Unit (CPU) 1Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.2 Internal Memory 1Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.3 Peripherals 1Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 CPU Data Paths and Control 2Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summarizes the TMS320C62x/C67x architecture and describes the primary components of
the CPU.
2.1 General-Purpose Register Files 2Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Functional Units 2Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Register File Cross Paths 2Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Memory, Load, and Store Paths 2Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Data Address Paths 2Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 TMS320C62x/C67x Control Register File 2Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.1 Addressing Mode Register (AMR) 2Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.2 Control Status Register (CSR) 2Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.3 E1 Phase Program Counter (PCE1) 2Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 TMS320C67x Extensions to the Control Register File 2Ć13. . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.1 Floating-Point Adder Configuration Register (FADCR) 2Ć14. . . . . . . . . . . . . . . . . . .
2.7.2 Floating-Point Auxiliary Configuration Register (FAUCR) 2Ć16. . . . . . . . . . . . . . . . .
2.7.3 Floating-Point Multiplier Configuration Register (FMCR) 2Ć18. . . . . . . . . . . . . . . . .

Contents
x
3 TMS320C62x/C67x Fixed-Point Instruction Set 3Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the assembly language instructions that are common to both the TMS320C62x and
TMS320C67x, including examples of each instruction. Provides information about addressing
modes, resource constraints, parallel operations, and conditional operations.
3.1 Instruction Operation and Execution Notations 3Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Mapping Between Instructions and Functional Units 3Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 TMS320C62x/C67x Opcode Map 3Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Delay Slots 3Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Parallel Operations 3Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 Example Parallel Code 3Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.2 Branching Into the Middle of an Execute Packet 3Ć15. . . . . . . . . . . . . . . . . . . . . . . .
3.6 Conditional Operations 3Ć16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 Resource Constraints 3Ć17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1 Constraints on Instructions Using the Same Functional Unit 3Ć17. . . . . . . . . . . . . .
3.7.2 Constraints on Cross Paths (1X and 2X) 3Ć17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.3 Constraints on Loads and Stores 3Ć18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.4 Constraints on Long (40-Bit) Data 3Ć18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.5 Constraints on Register Reads 3Ć19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.6 Constraints on Register Writes 3Ć19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 Addressing Modes 3Ć21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.1 Linear Addressing Mode 3Ć21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.2 Circular Addressing Mode 3Ć21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.3 Syntax for Load/Store Address Generation 3Ć23. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9 Individual Instruction Descriptions 3Ć24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 TMS320C67x Floating-Point Instruction Set 4Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the TMS320C67x floating-point instruction set, including examples of each
instruction. Provides information about addressing modes and resource constraints.
4.1 Instruction Operation and Execution Notations 4Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Mapping Between Instructions and Functional Units 4Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Overview of IEEE Standard Single- and Double-Precision Formats 4Ć6. . . . . . . . . . . . . . . .
4.4 Delay Slots 4Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 TMS320C67x Instruction Constraints 4Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Individual Instruction Descriptions 4Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 TMS320C62x Pipeline 5Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes phases, operation, and discontinuities for the TMS320C62x CPU pipeline.
5.1 Pipeline Operation Overview 5Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.1 Fetch 5Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.2 Decode 5Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.3 Execute 5Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.4 Summary of Pipeline Operation 5Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Pipeline Execution of Instruction Types 5Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.1 Single-Cycle Instructions 5Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .