Texas Instruments TMS320C6000 Series User manual

TMS320C6000
CPU and Instruction Set
Reference Guide
Literature Number: SPRU189D
March 1999
Printed on Recycled Paper

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Copyright 1999, Texas Instruments Incorporated

iii Contents
Preface
Read This First
About This Manual
ThisreferenceguidedescribestheCPUarchitecture,pipeline,instructionset,
andinterruptsfortheTMS320C6000digitalsignalprocessors(DSPs).Unless
otherwise specified, all references to the ’C6000 refer to the TMS320C6000
platform of DSPs, ’C62x refers to the TMS320C62x fixed-point DSPs in the
’C6000 platform, and ’C67x refers to the TMS320C67x floating-point DSPs in
the ’C6000 platform.
How to Use This Manual
UsethismanualasareferenceforthearchitectureoftheTMS320C6000CPU.
First-time readers should read Chapter 1 for general information about TI
DSPs, the features of the ’C6000, and the applications for which the ’C6000
is best suited.
Read chapters 2, 5, 6, and 7 to grasp the concepts of the architecture. Chap-
ter 3 and Chapter 4 contain detailed information about each instruction and is
best used as reference material; however, you may want to read sections 3.1
through 3.9 and sections 4.1 through 4.6 for general information about the
instruction set and to understand the instruction descriptions, then browse
through Chapter 3 and Chapter 4 to familiarize yourself with the instructions.

iv
The following table gives chapter references for specific information:
If you are looking for in-
formation about: Turn to these chapters:
Addressing modes Chapter 3, TMS320C62x/C67x Fixed-Point
Instruction Set
Chapter 4, TMS320C67x Floating-Point
Instruction Set
Conditional operations Chapter 3, TMS320C62x/C67x Fixed-Point
Instruction Set
Chapter 4, TMS320C67x Floating-Point
Instruction Set
Control registers Chapter 2, CPU Data Paths and Control
CPU architecture and data
paths Chapter 2,
CPU Data Paths and Control
Delay slots Chapter 3, TMS320C62x/C67x Fixed-Point
Instruction Set
Chapter 4, TMS320C67x Floating-Point
Instruction Set
Chapter 5, TMS320C62x Pipeline
Chapter 6, TMS320C67x Pipeline
General-purpose register files Chapter 2, CPU Data Paths and Control
Instruction set Chapter 3, TMS320C62x/C67x Fixed-Point
Instruction Set
Chapter 4, TMS320C67x Floating-Point
Instruction Set
Interrupts and control registers Chapter 7, Interrupts
Parallel operations Chapter 3, TMS320C62x/C67x Fixed-Point
Instruction Set
Chapter 4, TMS320C67x Floating-Point
Instruction Set
Pipeline phases and operation Chapter 5, TMS320C62x Pipeline
Chapter 6, TMS320C67x Pipeline
Reset Chapter 7, Interrupts
Ifyouareinterestedintopicsthatarenotlistedhere,check RelatedDocumen-
tation From Texas Instruments
, on page vi, for brief descriptions of other
’C6x-related books that are available.
Read This First

v
Notational Conventions
This document uses the following conventions:
-Program listings and program examples are shown in a special font.
Here is a sample program listing:
LDW .D1 *A0,A1
ADD .L1 A1,A2,A3
NOP 3
MPY .M1 A1,A4,A5
-To help you easily recognize instructions and parameters throughout the
book, instructions are in bold face and parameters are in italics (except
in program listings).
-Ininstruction syntaxes, portions of a syntax that are in bold should be en-
tered as shown; portions of a syntax that are in italics describe the type of
information that should be entered. Here is an example of an instruction:
MPY
src1,src2,dst
MPY is the instruction mnemonic. When you use MPY, you must supply
two source operands ( src1 and src2 ) and a destination operand ( dst ) of
appropriate types as defined in Chapter 3,
TMS320C62x/C67x Fixed-
Point Instruction Set .
Although the instruction mnemonic (MPY in this example) is in capital let-
ters,the’C6xassembler isnotcasesensitive —itcanassemblemnemon-
ics entered in either upper or lower case.
-Squarebrackets,[and ], and parentheses,(and), are used to identifyop-
tional items. If you use an optional item, you must specify the information
withinbrackets or parentheses;however, youdo not enterthe brackets or
parenthesesthemselves.Hereisanexampleofaninstructionthathasop-
tional items.
[ label ] EXTU ( .unit ) src2, csta, cstb, dst
The EXTU instruction is shown with a label and several parameters. The
[ label ] and the parameter ( .unit ) are optional. The parameters src2, csta,
cstb, and dst are not optional.
-Throughout this book MSB means most significant bit and LSB means
least significant bit .
-A special icon is used to indicate material that applies only to the floating-
point (’C67x) DSP:
Notational Conventions
Read This First

vi
Related Documentation From Texas Instruments
ThefollowingbooksdescribetheTMS320C6xgenerationandrelatedsupport
tools. To obtain a copy of any of these TI documents, call the Texas Instru-
mentsLiteratureResponseCenterat(800)477–8924.Whenordering,please
identify the book by its title and literature number.
TMS320C62x/C67x Technical Brief (literature number SPRU197) gives an
introduction to the ’C62x/C67x digital signal processors, development
tools, and third-party support.
TMS320C6201 Digital Signal Processor Data Sheet (literature number
SPRS051) describes the features of the TMS320C6201 and provides
pinouts, electrical specifications, and timings for the device.
TMs320C6202 Digital Signal Processor Data Sheet (literature number
SPRS072)describesthefeaturesoftheTMS320C6202fixed-pointDSP
and provides pinouts, electrical specifications, and timings for the de-
vice.
TMS320C6211 Digital Signal Processor Data Sheet (literature number
SPRS073)describesthefeaturesoftheTMS320C6211fixed-pointDSP
and provides pinouts, electrical specifications, and timings for the de-
vice.
TMS320C6701 Digital Signal Processor Data Sheet (literature number
SPRS067) describes the features of the TMS320C6701 floating-point
DSP and provides pinouts, electrical specifications, and timings for the
device.
TMS320C6000 Peripherals Reference Guide (literature number SPRU190)
describes common peripherals available on the TMS320C6000 digital
signal processors. This book includes information on the internal data
and program memories, the external memory interface (EMIF), the host
port, serial ports, direct memory access (DMA), clocking and phase-
locked loop (PLL), and the power-down modes.
TMS320C62x/C67x Programmer’s Guide (literature number SPRU198)
describes ways to optimize C and assembly code for the
TMS320C62x/C67x DSPs and includes application program examples.
TMS320C6000AssemblyLanguageToolsUser’sGuide (literaturenumber
SPRU186) describes the assembly language tools (assembler, linker,
and other tools used to develop assembly language code), assembler
directives, macros, common object file format, and symbolic debugging
directives for the ’C6000 generation of devices.
Related Documentation From Texas Instruments

vii
TMS320C6000 Optimizing C Compiler User’s Guide (literature number
SPRU187)describesthe’C6000Ccompilerandtheassemblyoptimizer.
ThisCcompileracceptsANSIstandardCsourcecodeandproducesas-
semblylanguagesourcecodeforthe’C6000 generation of devices. The
assembly optimizer helps you optimize your assembly code.
TMS320 Third-Party Support Reference Guide (literature number
SPRU052)alphabetically listsover 100 third partiesthat provide various
products that serve the family of TMS320 digital signal processors. A
myriadofproductsandapplicationsareoffered—softwareandhardware
development tools, speech recognition, image processing, noise can-
cellation, modems, etc.
Trademarks
TI,XDS510,VelociTI, and320HotlineOn-linearetrademarks ofTexasInstru-
ments Incorporated.
Windows and Windows NT are registered trademarks of Microsoft Corpora-
tion.
Related Documentation From Texas Instruments / Trademarks
Read This First

viii
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Note: When calling a Literature Response Center to order documentation, please specify the literature number of the
book.
If You Need Assistance

Contents
ix
Contents
Summarizes the features of the TMS320 family of products and presents typical applications.
Describes the TMS320C62x/C67x DSPs and lists their key features.
1 Introduction 1Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summarizes the features of the TMS320 family of products and presents typical applications.
Describes the TMS320C62xx DSP and lists its key features.
1.1 TMS320 Family Overview 1Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.1 History of TMS320 DSPs 1Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.2 Typical Applications for the TMS320 Family 1Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Overview of the TMS320C6x Generation of Digital Signal Processors 1Ć4. . . . . . . . . . . . .
1.3 Features and Options of the TMS320C62x/C67x 1Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 TMS320C62x/C67x Architecture 1Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.1 Central Processing Unit (CPU) 1Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.2 Internal Memory 1Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.3 Peripherals 1Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 CPU Data Paths and Control 2Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summarizes the TMS320C62x/C67x architecture and describes the primary components of
the CPU.
2.1 General-Purpose Register Files 2Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Functional Units 2Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Register File Cross Paths 2Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Memory, Load, and Store Paths 2Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Data Address Paths 2Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 TMS320C62x/C67x Control Register File 2Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.1 Addressing Mode Register (AMR) 2Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.2 Control Status Register (CSR) 2Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.3 E1 Phase Program Counter (PCE1) 2Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 TMS320C67x Extensions to the Control Register File 2Ć13. . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.1 Floating-Point Adder Configuration Register (FADCR) 2Ć14. . . . . . . . . . . . . . . . . . .
2.7.2 Floating-Point Auxiliary Configuration Register (FAUCR) 2Ć16. . . . . . . . . . . . . . . . .
2.7.3 Floating-Point Multiplier Configuration Register (FMCR) 2Ć18. . . . . . . . . . . . . . . . .

Contents
x
3 TMS320C62x/C67x Fixed-Point Instruction Set 3Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the assembly language instructions that are common to both the TMS320C62x and
TMS320C67x, including examples of each instruction. Provides information about addressing
modes, resource constraints, parallel operations, and conditional operations.
3.1 Instruction Operation and Execution Notations 3Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Mapping Between Instructions and Functional Units 3Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 TMS320C62x/C67x Opcode Map 3Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Delay Slots 3Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Parallel Operations 3Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 Example Parallel Code 3Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.2 Branching Into the Middle of an Execute Packet 3Ć15. . . . . . . . . . . . . . . . . . . . . . . .
3.6 Conditional Operations 3Ć16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 Resource Constraints 3Ć17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1 Constraints on Instructions Using the Same Functional Unit 3Ć17. . . . . . . . . . . . . .
3.7.2 Constraints on Cross Paths (1X and 2X) 3Ć17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.3 Constraints on Loads and Stores 3Ć18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.4 Constraints on Long (40-Bit) Data 3Ć18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.5 Constraints on Register Reads 3Ć19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.6 Constraints on Register Writes 3Ć19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 Addressing Modes 3Ć21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.1 Linear Addressing Mode 3Ć21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.2 Circular Addressing Mode 3Ć21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.3 Syntax for Load/Store Address Generation 3Ć23. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9 Individual Instruction Descriptions 3Ć24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 TMS320C67x Floating-Point Instruction Set 4Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the TMS320C67x floating-point instruction set, including examples of each
instruction. Provides information about addressing modes and resource constraints.
4.1 Instruction Operation and Execution Notations 4Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Mapping Between Instructions and Functional Units 4Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Overview of IEEE Standard Single- and Double-Precision Formats 4Ć6. . . . . . . . . . . . . . . .
4.4 Delay Slots 4Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 TMS320C67x Instruction Constraints 4Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Individual Instruction Descriptions 4Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 TMS320C62x Pipeline 5Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes phases, operation, and discontinuities for the TMS320C62x CPU pipeline.
5.1 Pipeline Operation Overview 5Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.1 Fetch 5Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.2 Decode 5Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.3 Execute 5Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.4 Summary of Pipeline Operation 5Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Pipeline Execution of Instruction Types 5Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.1 Single-Cycle Instructions 5Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
xi Contents
5.2.2 Multiply Instructions 5Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.3 Store Instructions 5Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.4 Load Instructions 5Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.5 Branch Instructions 5Ć16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Performance Considerations 5Ć18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.1 Pipeline Operation With Multiple Execute Packets in a Fetch Packet 5Ć18. . . . . .
5.3.2 Multicycle NOPs 5Ć20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.3 Memory Considerations 5Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 TMS320C67x Pipeline 6Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes phases, operation, and discontinuities for the TMS320C67x CPU pipeline.
6.1 Pipeline Operation Overview 6Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.1 Fetch 6Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.2 Decode 6Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.3 Execute 6Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.4 Summary of Pipeline Operation 6Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Pipeline Execution of Instruction Types 6Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Functional Unit Hazards 6Ć20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.1 .S-Unit Hazards 6Ć21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.2 .M-Unit Hazards 6Ć25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.3 .L-Unit Hazards 6Ć30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.4 D-Unit Instruction Hazards 6Ć34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.5 Single-Cycle Instructions 6Ć38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.6 16 ×16-Bit Multiply Instructions 6Ć39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.7 Store Instructions 6Ć40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.8 Load Instructions 6Ć42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.9 Branch Instructions 6Ć44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.10 2-Cycle DP Instructions 6Ć46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.11 4-Cycle Instructions 6Ć47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.12 INTDP Instruction 6Ć47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.13 DP Compare Instructions 6Ć48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.14 ADDDP/SUBDP Instructions 6Ć49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.15 MPYI Instructions 6Ć50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.16 MPYID Instructions 6Ć50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.17 MPYDP Instructions 6Ć51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 Performance Considerations 6Ć52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.1 Pipeline Operation With Multiple Execute Packets in a Fetch Packet 6Ć52. . . . . .
6.4.2 Multicycle NOPs 6Ć54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.3 Memory Considerations 6Ć56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
xii
7 Interrupts 7Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the TMS320C62x/C67x interrupts, including reset and nonmaskable interrupts
(NMI), and explains interrupt control, detection, and processing.
7.1 Overview of Interrupts 7Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.1 Types of Interrupts and Signals Used 7Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.2 Interrupt Service Table (IST) 7Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.3 Summary of Interrupt Control Registers 7Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Globally Enabling and Disabling Interrupts
(Control Status Register–CSR) 7Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Individual Interrupt Control 7Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.1 Enabling and Disabling Interrupts (Interrupt Enable Register–IER) 7Ć13. . . . . . . .
7.3.2 Status of, Setting, and Clearing Interrupts
(Interrupt Flag, Set, and Clear Registers–IFR, ISR, ICR) 7Ć14. . . . . . . . . . . . . . . . .
7.3.3 Returning From Interrupt Servicing 7Ć16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4 Interrupt Detection and Processing 7Ć18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4.1 Setting the Nonreset Interrupt Flag 7Ć18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4.2 Conditions for Processing a Nonreset Interrupt 7Ć18. . . . . . . . . . . . . . . . . . . . . . . . .
7.4.3 Actions Taken During Nonreset Interrupt Processing 7Ć21. . . . . . . . . . . . . . . . . . . .
7.4.4 Setting the RESET Interrupt Flag for the TMS320C62x/C67x 7Ć22. . . . . . . . . . . . .
7.4.5 Actions Taken During RESET Interrupt Processing 7Ć23. . . . . . . . . . . . . . . . . . . . . .
7.5 Performance Considerations 7Ć24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.1 General Performance 7Ć24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.2 Pipeline Interaction 7Ć24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6 Programming Considerations 7Ć25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.1 Single Assignment Programming 7Ć25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.2 Nested Interrupts 7Ć26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.3 Manual Interrupt Processing 7Ć26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.4 Traps 7Ć27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A Glossary AĆ1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Defines terms and abbreviations used throughout this book.

Figures
xiii Contents
Figures
1–1 TMS320C62x/C67x Block Diagram 1Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 TMS320C62x CPU Data Paths 2Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 TMS320C67x CPU Data Paths 2Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 Storage Scheme for 40-Bit Data in a Register Pair 2Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 Addressing Mode Register (AMR) 2Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 Control Status Register (CSR) 2Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 E1 Phase Program Counter (PCE1) 2Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–7 Floating-Point Adder Configuration Register (FADCR) 2Ć14. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–8 Floating-Point Auxiliary Configuration Register (FAUCR) 2Ć16. . . . . . . . . . . . . . . . . . . . . . . . . .
2–9 Floating-Point Multiplier Configuration Register (FMCR) 2Ć18. . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 TMS320C62x/C67x Opcode Map 3Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 Basic Format of a Fetch Packet 3Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Examples of the Detectability of Write Conflicts by the Assembler 3Ć20. . . . . . . . . . . . . . . . . .
4–1 Single-Precision Floating-Point Fields 4Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 Double-Precision Floating-Point Fields 4Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 Fixed-Point Pipeline Stages 5Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Fetch Phases of the Pipeline 5Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–3 Decode Phases of the Pipeline 5Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–4 Execute Phases of the Pipeline and Functional Block Diagram
of the TMS320C62x 5Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–5 Fixed-Point Pipeline Phases 5Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–6 Pipeline Operation: One Execute Packet per Fetch Packet 5Ć6. . . . . . . . . . . . . . . . . . . . . . . . .
5–7 Functional Block Diagram of TMS320C62x Based on Pipeline Phases 5Ć8. . . . . . . . . . . . . . .
5–8 Single-Cycle Instruction Phases 5Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–9 Single-Cycle Execution Block Diagram 5Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–10 Multiply Instruction Phases 5Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–11 Multiply Execution Block Diagram 5Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–12 Store Instruction Phases 5Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–13 Store Execution Block Diagram 5Ć14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–14 Load Instruction Phases 5Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–15 Load Execution Block Diagram 5Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–16 Branch Instruction Phases 5Ć16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–17 Branch Execution Block Diagram 5Ć17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–18 Pipeline Operation: Fetch Packets With Different Numbers of Execute Packets 5Ć19. . . . . . .
5–19 Multicycle NOP in an Execute Packet 5Ć20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–20 Branching and Multicycle NOPs 5Ć21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures
xiv
5–21 Pipeline Phases Used During Memory Accesses 5Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–22 Program and Data Memory Stalls 5Ć23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–23 4-Bank Interleaved Memory 5Ć24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–24 4-Bank Interleaved Memory With Two Memory Spaces 5Ć25. . . . . . . . . . . . . . . . . . . . . . . . . . .
6–1 Floating-Point Pipeline Stages 6Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–2 Fetch Phases of the Pipeline 6Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–3 Decode Phases of the Pipeline 6Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–4 Execute Phases of the Pipeline and Functional Block Diagram
of the TMS320C67x 6Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–5 Floating-Point Pipeline Phases 6Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–6 Pipeline Operation: One Execute Packet per Fetch Packet 6Ć6. . . . . . . . . . . . . . . . . . . . . . . . .
6–7 Functional Block Diagram of TMS320C67x Based on Pipeline Phases 6Ć10. . . . . . . . . . . . . .
6–8 Single-Cycle Instruction Phases 6Ć38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–9 Single-Cycle Execution Block Diagram 6Ć38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–10 Multiply Instruction Phases 6Ć39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–11 Multiply Execution Block Diagram 6Ć39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–12 Store Instruction Phases 6Ć40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–13 Store Execution Block Diagram 6Ć41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–14 Load Instruction Phases 6Ć42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–15 Load Execution Block Diagram 6Ć43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–16 Branch Instruction Phases 6Ć44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–17 Branch Execution Block Diagram 6Ć45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–18 2-Cycle DP Instruction Phases 6Ć46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–19 4-Cycle Instruction Phases 6Ć47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–20 INTDP Instruction Phases 6Ć48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–21 DP Compare Instruction Phases 6Ć48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–22 ADDDP/SUBDP Instruction Phases 6Ć49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–23 MPYI Instruction Phases 6Ć50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–24 MPYID Instruction Phases 6Ć51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–25 MPYDP Instruction Phases 6Ć51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–26 Pipeline Operation: Fetch Packets With Different Numbers of Execute Packets 6Ć53. . . . . . .
6–27 Multicycle NOP in an Execute Packet 6Ć54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–28 Branching and Multicycle NOPs 6Ć55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–29 Pipeline Phases Used During Memory Accesses 6Ć56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–30 Program and Data Memory Stalls 6Ć57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–31 8-Bank Interleaved Memory 6Ć58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–32 8-Bank Interleaved Memory With Two Memory Spaces 6Ć59. . . . . . . . . . . . . . . . . . . . . . . . . . .
7–1 Interrupt Service Table 7Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–2 Interrupt Service Fetch Packet 7Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–3 IST With Branch to Additional Interrupt Service Code Located Outside the IST 7Ć7. . . . . . . .
7–4 Interrupt Service Table Pointer (ISTP) 7Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–5 Control Status Register (CSR) 7Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–6 Interrupt Enable Register (IER) 7Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–7 Interrupt Flag Register (IFR) 7Ć14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures
xv Contents
7–8 Interrupt Set Register (ISR) 7Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–9 Interrupt Clear Register (ICR) 7Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–10 NMI Return Pointer (NRP) 7Ć16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–11 Interrupt Return Pointer (IRP) 7Ć17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–12 TMS320C62x Nonreset Interrupt Detection and Processing: Pipeline Operation 7Ć19. . . . . .
7–13 TMS320C67x Nonreset Interrupt Detection and Processing: Pipeline Operation 7Ć20. . . . . .
7–14 RESET Interrupt Detection and Processing: Pipeline Operation 7Ć22. . . . . . . . . . . . . . . . . . . .

Tables
xvi
Tables
1–1 Typical Applications for the TMS320 DSPs 1Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 40-Bit/64-Bit Register Pairs 2Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 Functional Units and Operations Performed 2Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 Control Registers 2Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 Addressing Mode Register (AMR) Mode Select Field Encoding 2Ć9. . . . . . . . . . . . . . . . . . . . .
2–5 Block Size Calculations 2Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 Control Status Register Field Descriptions 2Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–7 Control Register File Extensions 2Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–8 Floating-Point Adder Configuration Register Field Descriptions 2Ć15. . . . . . . . . . . . . . . . . . . . .
2–9 Floating-Point Auxiliary Configuration Register Field Descriptions 2Ć17. . . . . . . . . . . . . . . . . .
2–10 Floating-Point Multiplier Configuration Register Field Descriptions 2Ć19. . . . . . . . . . . . . . . . . .
3–1 Fixed-Point Instruction Operation and Execution Notations 3Ć2. . . . . . . . . . . . . . . . . . . . . . . . .
3–2 Instruction to Functional Unit Mapping 3Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Functional Unit to Instruction Mapping 3Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 TMS320C62x/C67x Opcode Map Symbol Definitions 3Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 Delay Slot and Functional Unit Latency Summary 3Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–6 Registers That Can Be Tested by Conditional Operations 3Ć16. . . . . . . . . . . . . . . . . . . . . . . . .
3–7 Indirect Address Generation for Load/Store 3Ć23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–8 Relationships Between Operands, Operand Size, Signed/Unsigned, Functional
Units, and Opfields for Example Instruction (ADD) 3Ć26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–9 Program Counter Values for Example Branch Using a Displacement 3Ć41. . . . . . . . . . . . . . . .
3–10 Program Counter Values for Example Branch Using a Register 3Ć43. . . . . . . . . . . . . . . . . . . .
3–11 Program Counter Values for B IRP 3Ć45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–12 Program Counter Values for B NRP 3Ć47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–13 Data Types Supported by Loads 3Ć67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–14 Address Generator Options 3Ć67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–15 Data Types Supported by Loads 3Ć72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–16 Register Addresses for Accessing the Control Registers 3Ć87. . . . . . . . . . . . . . . . . . . . . . . . . .
3–17 Data Types Supported by Stores 3Ć123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–18 Address Generator Options 3Ć123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–19 Data Types Supported by Stores 3Ć127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 Floating-Point Instruction Operation and Execution Notations 4Ć2. . . . . . . . . . . . . . . . . . . . . . .
4–2 Instruction to Functional Unit Mapping 4Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–3 Functional Unit to Instruction Mapping 4Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 IEEE Floating-Point Notations 4Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–5 Special Single-Precision Values 4Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables
xvii Contents
4–6 Hex and Decimal Representation for Selected Single-Precision Values 4Ć9. . . . . . . . . . . . . . .
4–7 Special Double-Precision Values 4Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–8 Hex and Decimal Representation for Selected Double-Precision Values 4Ć10. . . . . . . . . . . . .
4–9 Delay Slot and Functional Unit Latency Summary 4Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–10 Address Generator Options 4Ć52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 Operations Occurring During Fixed-Point Pipeline Phases 5Ć7. . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Execution Stage Length Description for Each Instruction Type 5Ć11. . . . . . . . . . . . . . . . . . . . .
5–3 Program Memory Accesses Versus Data Load Accesses 5Ć22. . . . . . . . . . . . . . . . . . . . . . . . . .
5–4 Loads in Pipeline From Example 5–2 5Ć25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–1 Operations Occurring During Floating-Point Pipeline Phases 6Ć7. . . . . . . . . . . . . . . . . . . . . . .
6–2 Execution Stage Length Description for Each Instruction Type 6Ć13. . . . . . . . . . . . . . . . . . . . .
6–3 Single-Cycle .S-Unit Instruction Hazards 6Ć21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–4 DP Compare .S-Unit Instruction Hazards 6Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–5 2-Cycle DP .S-Unit Instruction Hazards 6Ć23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–6 Branch .S-Unit Instruction Hazards 6Ć24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–7 16 ×16 Multiply .M-Unit Instruction Hazards 6Ć25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–8 4-Cycle .M-Unit Instruction Hazards 6Ć26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–9 MPYI .M-Unit Instruction Hazards 6Ć27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–10 MPYID .M-Unit Instruction Hazards 6Ć28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–11 MPYDP .M-Unit Instruction Hazards 6Ć29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–12 Single-Cycle .L-Unit Instruction Hazards 6Ć30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–13 4-Cycle .L-Unit Instruction Hazards 6Ć31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–14 INTDP .L-Unit Instruction Hazards 6Ć32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–15 ADDDP/SUBDP .L-Unit Instruction Hazards 6Ć33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–16 Load .D-Unit Instruction Hazards 6Ć34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–17 Store .D-Unit Instruction Hazards 6Ć35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–18 Single-Cycle .D-Unit Instruction Hazards 6Ć36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–19 LDDW Instruction With Long Write Instruction Hazards 6Ć37. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–20 Single-Cycle Execution 6Ć38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–21 16 ×16-Bit Multiply Execution 6Ć39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–22 Store Execution 6Ć40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–23 Load Execution 6Ć42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–24 Branch Execution 6Ć44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–25 2-Cycle DP Execution 6Ć46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–26 4-Cycle Execution 6Ć47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–27 INTDP Execution 6Ć48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–28 DP Compare Execution 6Ć48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–29 ADDDP/SUBDP Execution 6Ć49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–30 MPYI Execution 6Ć50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–31 MPYID Execution 6Ć50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–32 MPYDP Execution 6Ć51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–33 Program Memory Accesses Versus Data Load Accesses 6Ć56. . . . . . . . . . . . . . . . . . . . . . . . . .
6–34 Loads in Pipeline From Example 6–2 6Ć59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables
xviii
7–1 Interrupt Priorities 7Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–2 Interrupt Service Table Pointer (ISTP) Field Descriptions 7Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . .
7–3 Interrupt Control Registers 7Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–4 Control Status Register (CSR) Interrupt Control Field Descriptions 7Ć11. . . . . . . . . . . . . . . . .

Examples
xix Contents
Examples
3–1 Fully Serial p-Bit Pattern in a Fetch Packet 3Ć14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 Fully Parallel p-Bit Pattern in a Fetch Packet 3Ć14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Partially Serial p-Bit Pattern in a Fetch Packet 3Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 LDW in Circular Mode 3Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 ADDAH in Circular Mode 3Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 Execute Packet in Figure 5–7 5Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Load From Memory Banks 5Ć24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–1 Execute Packet in Figure 6–7 6Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–2 Load From Memory Banks 6Ć58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–1 Relocation of Interrupt Service Table 7Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–2 Code Sequence to Disable Maskable Interrupts Globally 7Ć12. . . . . . . . . . . . . . . . . . . . . . . . . .
7–3 Code Sequence to Enable Maskable Interrupts Globally 7Ć12. . . . . . . . . . . . . . . . . . . . . . . . . .
7–4 Code Sequence to Enable an Individual Interrupt (INT9) 7Ć14. . . . . . . . . . . . . . . . . . . . . . . . . .
7–5 Code Sequence to Disable an Individual Interrupt (INT9) 7Ć14. . . . . . . . . . . . . . . . . . . . . . . . . .
7–6 Code to Set an Individual Interrupt (INT6) and Read the Flag Register 7Ć15. . . . . . . . . . . . . .
7–7 Code to Clear an Individual Interrupt (INT6) and Read the Flag Register 7Ć15. . . . . . . . . . . .
7–8 Code to Return From NMI 7Ć16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–9 Code to Return from a Maskable Interrupt 7Ć17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–10 Code Without Single Assignment: Multiple Assignment of A1 7Ć25. . . . . . . . . . . . . . . . . . . . . .
7–11 Code Using Single Assignment 7Ć25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–12 Manual Interrupt Processing 7Ć26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–13 Code Sequence to Invoke a Trap 7Ć27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–14 Code Sequence for Trap Return 7Ć27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1
a
Introduction
TheTMS320C6x generationofdigitalsignalprocessors ispartoftheTMS320
family of digital signal processors (DSPs). The TMS320C62x devices are
fixed-point DSPs in the TMS320C6x generation, and the TMS320C67x
devices are floating-point DSPs in the TMS320C6x generation. The
TMS320C62x and TMS320C67x are code compatible and both use the
VelociTIarchitecture, a high-performance, advanced VLIW (very long
instructionword)architecture,makingtheseDSPsexcellentchoicesformulti-
channel and multifunction applications.
The VelociTI architecture of the ’C62x and ’C67x make them the first off-the-
shelf DSPs to use advanced VLIW to achieve high performance through
increased instruction-level parallelism. A traditional VLIW architecture
consists of multiple execution units running in parallel, performing multiple
instructionsduringasingleclockcycle.Parallelismisthekeytoextremelyhigh
performance, taking these DSPs well beyond the performance capabilities of
traditional superscalar designs. VelociTI is a highly deterministic architecture,
having few restrictions on how or when instructions are fetched, executed, or
stored.Itisthisarchitecturalflexibilitythatiskeytothebreakthroughefficiency
levels of the ’C6x compiler. VelociTI’s advanced features include:
-Instruction packing: reduced code size
-All instructions can operate conditionally: flexibility of code
-Variable-width instructions: flexibility of data types
-Fully pipelined branches: zero-overhead branching
Topic Page
1.1 TMS320 Family Overview 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Overview of the TMS320C6x Generation of
Digital Signal Processors 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Features and Options of the TMS320C62x/C67x 1-5. . . . . . . . . . . . . . . . .
1.4 TMS320C62x/C67x Architecture 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1