Texas Instruments TMS320VC5509A User manual

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TMS320VC5509A
Digital Signal Processor
Silicon Errata
SPRZ200E
June 2003 − Revised April 2008
Copyright 2005, Texas Instruments Incorporated

SPRZ200E
TMS320VC5509A Silicon Errata
2
REVISION HISTORY
This revision history highlights the technical changes made to SPRZ200D to generate SPRZ200E.
Scope: Changes to Advisory PM_1 Repeated Interrupts Durring CLKGEN Domain Idle
PAGE(S)
NO. ADDITIONS/CHANGES/DELETIONS
28 Updated Section 3.12 Power Management Advisories, Advisory PM_1. Changed the Title from
“Repeated Interrupts During CPU Idle” to
“Repeated Interrupts During CLKGEN Domain Idle”.
Details:
− Changed instances of CPU in idle state from “CPU” to “CLKGEN”
Workaround:
− Changed instances of CPU in idle state from “CPU” to “CLKGEN”

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TMS320VC5509A Silicon Errata
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Contents
1 Introduction 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Device and Development-Support Tool Nomenclature 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Revision Identification 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Usage Notes 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTC: Seconds Alarm Functionality 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Known Design Marginality/Exceptions to Functional Specifications 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Summary of Advisories 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Device-Level Advisories 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL_2 Software Modification of MPNMC Bit is Not Pipeline-Protected 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL_7 RETI Instruction may Affect the XF State 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL_10 First Word of Data on Consecutive DMA Transmissions Using McBSP is Lost 11. . . . . . . . . . . . . . . . .
3.3 Bootloader Advisories 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BL_3 USB Bootloader Returns Incorrect DescriptorType Value When String Descriptors are
Requested by the Host 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BL_4 USB Bootloader Returns Incorrect PID During Enumeration Phase 12. . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Direct Memory Access (DMA) Advisories 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA_1 Early Sync Event Stops Block Transfer 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA_2 DMA Does Not Support Burst Transfers From EMIF to EMIF 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 External Memory Interface (EMIF) Advisories 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMIF_8 ARDY Pin Requires Strong Pullup Resistor 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMIF_9 External Memory Write After Read Reversal 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMIF_10 Block Write Immediately Following a Block Read May Cause Data Corruption 15. . . . . . . . . . . . . . . . .
EMIF_11 EMIF Asynchronous Access Hold = 0 is Not Valid for Strobe > 3 15. . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMIF_12 8-Bit Asynchronous Writes on 5509A EMIF Not Supported 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMIF_13 After Changing CE Control Registers and Disabling SDRAM Clock in Divide-by-8 and
Divide-by-16 Modes, Asynchronous Access Followed by SDRAM Access Will Not
Supply a Ready Signal to CPU 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMIF_14 SETUP = 2 Configuration is not Valid for Asynchronous Memory 17. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Enhanced Host Port Interface (EHPI) Advisories 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EHPI_5 HPID Read Following a HPID Write While HRDY Low Corrupts the Read 18. . . . . . . . . . . . . . . . . . . . .
EHPI_6 HPIC/HPIA Access Following an Autoincremented HPID Write Causes Next HPID
Address to Increment to the Incorrect Address 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EHPI_7 HRDY is Always Driven 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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TMS320VC5509A Silicon Errata
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3.7 Real-Time Clock (RTC) Advisories 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTC_3 RTC Interrupts are Perceived by the User as Happening One Second Before 20. . . . . . . . . . . . . . . . .
RTC_4 Any Year Ending in 00 Will Appear as a Leap Year 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTC_5 Midnight and Noon Transitions Do Not Function Correctly in 12h Mode 21. . . . . . . . . . . . . . . . . . . . . . .
3.8 Universal Serial Bus (USB) Advisories 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB_2 CPU Might Miss Back-to-Back USB Interrupts When CPU Speed is Less Than or
Equal to 24 MHz 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB_5 USB Input Cell Does Not Power Down When USB is Placed in IDLE 22. . . . . . . . . . . . . . . . . . . . . . . . .
USB_6 CPU Read/Write to USB Module may Return Incorrect Result if the USB Clock is
Running Slower Than Recommended Speed (48 MHz) 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9 Inter-Integrated Circuit (I2C) Advisories 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C_3 ARDY Interrupt is not Generated Properly in Non-Repeat Mode if STOP Bit is Set 23. . . . . . . . . . . . .
I2C_5 Repeated Start Mode Does Not Work 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C_6 Bus Busy Bit Does Not Reflect the State of the I2C Bus When the I2C is in Reset 24. . . . . . . . . . . . .
I2C_8 DMA Receive Synchronization Pulse Gets Generated Falsely 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10 Multichannel Buffered Serial Port (McBSP) Advisories 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCBSP_1McBSP May Not Generate a Receive Event to DMA When Data Gets Copied
From RSR to DRR 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11 Emulation Advisories 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMU_1 Emulation Prone to Failure Under Certain Situations 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12 Power Management Advisories 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PM_1 Repeated Interrupts During CPU Idle 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13 Hardware Accelerator Advisories 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HWA_1 Pixel Interpolation Hardware Accelerator 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Documentation Support 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SPRZ200E
TMS320VC5509A Silicon Errata
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1 Introduction
This document describes the silicon updates to the functional specifications for the TMS320VC5509A. The updates
are applicable to:
•TMS320VC5509A (144-pin LQFP, PGE suffix)
•TMS320VC5509A (179-pin MicroStar BGA, GHH suffix)
The advisory numbers in this document are not always sequential. Some advisory numbers have been removed as
they do not apply to the device revisions specified in this document. When items are moved or deleted, the remaining
numbers remain the same and are not resequenced.
Issues related to CPU operation are documented in the TMS320C55x DSP CPU Programmer’s Reference
Supplement (literature number SPRU652).
1.1 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP
devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS
(e.g., TMS320VC5509A). Texas Instruments recommends two of three possible prefix designators for its support
tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering
prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device’s electrical specifications
TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality and
reliability verification
TMS Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the
device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
MicroStar BGA is a trademark of Texas Instruments.
Other trademarks are the property of their respective owners.

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1.2 Revision Identification
The device revision can be determined by the lot trace code marked on the top of the package. The locations for
the lot trace codes for the PGE and the GHH packages are shown in Figure 1 and Figure 2, respectively. The
location of other markings may vary per device.
Qualified devices in the PGE and GHH packages are marked with the letters “TMS” at the beginning of the device
name, while nonqualified devices are marked with the letters “TMX” or “TMP” at the beginning of the device name.
TMX320
4−XXXXXXX
VC5509APGE
Lot Trace Code Revision 1.0
TMS320
4A−XXXXXXX
VC5509APGE
Lot Trace Code Revision 1.1
Figure 1. Example Markings for VC5509A, PGE Package, Revisions 1.0 and 1.1
NOTE: Early revisions may have a letter “D” in front of “VC5509A” in the GHH package.
TMX320
4−XXXXXXX
VC5509AGHH
Lot Trace Code Revision 1.0
TMS320
4A−XXXXXXX
VC5509AGHH
Lot Trace Code Revision 1.1
Figure 2. Example Markings for VC5509A, GHH Package, Revisions 1.0 and 1.1
Table 1. Determining Silicon Revision From Lot Trace Code
Lot Trace Code Silicon Revision
Blank
(no second letter in prefix) Indicates Original Silicon (1.0)
A
(second letter in prefix is A) Indicates Silicon Revision A (1.1)

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2 Usage Notes
Usage Notes highlight and describe particular situations where the device’s behavior may not match the presumed
or documented behavior. This may include behaviors that affect device performance or functional correctness.
These notes will be incorporated into future documentation updates for the device (such as the device-specific
data sheet), and the behaviors they describe will not be altered in future silicon revisions.
RTC: Seconds Alarm Functionality
On the 5509A device, the Seconds Alarm Register (RTCSECA) cannot be used to generate an alarm every
second, but the update-ended interrupt can.
The Real-Time Clock (RTC) executes an update cycle once per second to update the current time in the
time/calendar registers:
•Seconds Register (RTCSEC)
•Minutes Register (RTCMIN)
•Hours Register (RTCHOUR)
•Day of the Week and Day Alarm Register (RTCDAYW)
•Day of the Month (Date) Register (RTCDAYM)
•Month Register (RTCMONTH)
•Year Register (RTCYEAR)
At the end of every update cycle, the RTC sets the update-ended interrupt flag (UF) in the Interrupt Flag Register
(RTCINTFL). If the update-ended interrupt enable bit (UIE) in the Interrupt Enable Register (RTCINTEN) is set to 1,
an interrupt request is sent to the CPU.

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TMS320VC5509A Silicon Errata
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3 Known Design Marginality/Exceptions to Functional Specifications
3.1 Summary of Advisories
Table 2 provides a quick reference of all advisories by number, silicon revision affected, and lists their respective
page location.
Table 2. Quick Reference Table
Advisory
Number Advisory Revision(s) Affected Page
Device-Level Advisories
DL_2 Software Modification of MPNMC Bit is Not Pipeline-Protected 1.0 and 1.1 10
DL_7 RETI Instruction may Affect the XF State 1.0 and 1.1 10
DL_10 First Word of Data on Consecutive DMA Transmissions Using McBSP is Lost 1.0 and 1.1 11
Bootloader Advisories
BL_3 USB Bootloader Returns Incorrect DescriptorType Value When String Descriptors are Requested
by the Host 1.0 and 1.1 12
BL_4 USB Bootloader Returns Incorrect PID During Enumeration Phase 1.0 and 1.1 12
Direct Memory Access (DMA) Advisories
DMA_1 Early Sync Event Stops Block Transfer 1.0 and 1.1 13
DMA_2 DMA Does Not Support Burst Transfers From EMIF to EMIF 1.0 and 1.1 13
External Memory Interface (EMIF) Advisories
EMIF_8 ARDY Pin Requires Strong Pullup Resistor 1.0 and 1.1 14
EMIF_9 External Memory Write After Read Reversal 1.0 and 1.1 14
EMIF_10 Block Write Immediately Following a Block Read May Cause Data Corruption 1.0 and 1.1 15
EMIF_11 EMIF Asynchronous Access Hold = 0 is Not Valid for Strobe > 3 1.0 and 1.1 15
EMIF_12 8-Bit Asynchronous Writes on 5509A EMIF Not Supported 1.0 and 1.1 16
EMIF_13 After Changing CE Control Registers and Disabling SDRAM Clock in Divide-by-8 and Divide-by-16
Modes, Asynchronous Access Followed by SDRAM Access Will Not Supply a Ready Signal to CPU 1.0 and 1.1 16
EMIF_14 SETUP = 2 Configuration is not Valid for Asynchronous Memory 1.0 and 1.1 17
Enhanced Host Port Interface (EHPI) Advisories
EHPI_5 HPID Read Following a HPID Write While HRDY Low Corrupts the Read 1.0 and 1.1 18
EHPI_6 HPIC/HPIA Access Following an Autoincremented HPID Write Causes Next HPID Address to Increment
to the Incorrect Address 1.0 and 1.1 18
EHPI_7 HRDY is Always Driven 1.0 and 1.1 19
Real-Time Clock (RTC) Advisories
RTC_3 RTC Interrupts are Perceived by the User as Happening One Second Before 1.0 and 1.1 20
RTC_4 Any Year Ending in 00 Will Appear as a Leap Year 1.0 and 1.1 20
RTC_5 Midnight and Noon Transitions Do Not Function Correctly in 12h Mode 1.0 and 1.1 21
Universal Serial Bus (USB) Advisories
USB_2 CPU Might Miss Back-to-Back USB Interrupts When CPU Speed is Less Than or Equal to 24 MHz 1.0 and 1.1 22
USB_5 USB Input Cell Does Not Power Down When USB is Placed in IDLE 1.0 and 1.1 22
USB_6 CPU Read/Write to USB Module may Return Incorrect Result if the USB Clock is Running Slower Than
Recommended Speed (48 MHz) 1.0 and 1.1 22

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Table 2. Quick Reference Table (Continued)
Advisory
Number Page
Revision(s)
Affected
Advisory
Inter-Integrated Circuit (I2C) Advisories
I2C_3 ARDY Interrupt is not Generated Properly in Non-Repeat Mode if STOP Bit is Set 1.0 and 1.1 23
I2C_5 Repeated Start Mode Does Not Work 1.0 and 1.1 23
I2C_6 Bus Busy Bit Does Not Reflect the State of the I2C Bus When the I2C is in Reset 1.0 and 1.1 24
I2C_8 DMA Receive Synchronization Pulse Gets Generated Falsely 1.0 and 1.1 24
Multichannel Buffered Serial Port (McBSP) Advisories
MCBSP_1 McBSP May Not Generate a Receive Event to DMA When Data Gets Copied From RSR to DRR 1.0 and 1.1 25
Emulation Advisories
EMU_1 Emulation Prone to Failure Under Certain Situations 1.0 and 1.1 26
Power Management Advisories
PM_1 Repeated Interrupts During CPU Idle 1.0 and 1.1 28
Hardware Accelerator Advisories
HWA_1 Pixel Interpolation Hardware Accelerator 1.0 and 1.1 29

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3.2 Device-Level Advisories
Software Modification of MPNMC Bit is Not Pipeline-Protected
Advisory DL_2
Revision(s) Affected: 1.0 and 1.1
Details: Software modification of the MPNMC bit in status register 3 (ST3_55) is not pipeline-protected
so changes to the device memory map may not become valid before the instructions that
immediately follow the modification.
Assembler Notification: None
Workaround: Insert six NOPs after the MPNMC modification.
RETI Instruction may Affect the XF State
Advisory DL_7
Revision(s) Affected: 1.0 and 1.1
Details: The XF pin state is saved on the stack as a part of the ST1 context saving during interrupts
servicing. If the XF pin state is changed inside the ISR, upon execution of the RETI, the XF bit
will be restored to the value prior to entering the ISR. If XF state is not changed inside the ISR,
then there is no issue.
Assembler Notification: None
Workaround: BIOS takes care of this problem with software workaround, which is transparent to the users.
Non-BIOS users who are changing XF pin state in an ISR should also modify the ST1 value
on the stack to maintain the correct XF pin state upon exiting the ISR.

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First Word of Data on Consecutive DMA Transmissions Using McBSP is Lost
Advisory DL_10
Revision(s) Affected: 1.0 and 1.1
Details: When executing multiple DMA transfers consecutively using the same DMA Transmit Channel
and McBSP, an extra DMA TX request generated by the McBSP at the end of the first transfer
will not be serviced by the DMA until the next DMA transfer is initiated by the McBSP. At the
next DMA transfer, this DMA TX request will be serviced as soon as the DMA TX channel is
enabled.
This transmitted data will remain valid on the bus as long as the McBSP is disabled. However,
once the McBSP is enabled, it sends out another DMA TX request, and the DMA transmits the
second word. This results in the loss of the first word of data on consecutive DMA
transmissions.
Assembler Notification: None
Workaround: Only the systems where McBSP is turned off following each block of DMA transfer are
affected. In such case, a dummy DMA transfer with the DMA synchronization event set to no
sync event will flush out the pending TX request from the McBSP before programming the
DMA to send the next block of data to the McBSP.

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3.3 Bootloader Advisories
USB Bootloader Returns Incorrect DescriptorType Value When String Descriptors are
Requested by the Host
Advisory BL_3
Revision(s) Affected: 1.0 and 1.1
Details: When the host requests for the string descriptor, the USB bootloader returns 0x00 for
DescriptorType value instead of 0x03.
Assembler Notification: None
Workaround: Ignore the DescriptorType returned by the DSP. String Descriptor is not necessary for
successfully bootloading the device through the USB.
USB Bootloader Returns Incorrect PID During Enumeration Phase
Advisory BL_4
Revision(s) Affected: 1.0 and 1.1
Details: The correct PID is 0x9003; however, the bootloader reports 0x9001 to the host.
Assembler Notification: None
Workaround: PID 0x9001 belongs to 5509. Both 5509 and 5509A USB bootloader work the same way;
hence, the incorrect PID does not affect the functionality of the USB bootmode.

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3.4 Direct Memory Access (DMA) Advisories
Early Sync Event Stops Block Transfer
Advisory DMA_1
Revision(s) Affected: 1.0 and 1.1
Details: When a DMA block transfer is initiated by a sync event, if the same sync event occurs before
the last element of the block transfer has been completed, an event drop occurs and the
channel becomes disabled.
Assembler Notification: None
Workaround: Ensure that the duration between the sync events is long enough to allow the block transfer to
complete. The DMA end-of-block interrupt can be used as an indicator.
DMA Does Not Support Burst Transfers From EMIF to EMIF
Advisory DMA_2
Revision(s) Affected: 1.0 and 1.1
Details: The DMA controller does not support burst mode transfers with the EMIF as both the source
and the destination port.
Assembler Notification: None
Workaround: Do not use burst mode for EMIF-to-EMIF transfers.

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3.5 External Memory Interface (EMIF) Advisories
ARDY Pin Requires Strong Pullup Resistor
Advisory EMIF_8
Revision(s) Affected: 1.0 and 1.1
Details: When the parallel bus is used to access external memory, a strong pullup resistor is required
for the ARDY pin for the asynchronous memory interface.
Assembler Notification: None
Workaround: Pull up ARDY with a 2.2-kΩresistor.
External Memory Write After Read Reversal
Advisory EMIF_9
Revision(s) Affected: 1.0 and 1.1
Details: If an external memory write is followed immediately by an external memory read, the external
memory read will occur first, followed by the write. See the example below.
Example:
MOV #1770h, *(100001h) ; External Memory Write
MOV *(#100000h), AR1 ; External Memory Read
Assembler Notification: None
Workaround: Insert two NOPs between the memory write/read pair.
Example:
MOV #1770h, *(100001h) ; External Memory Write
NOP
NOP
MOV *(#100000h), AR1 ; External Memory Read

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Block Write Immediately Following a Block Read May Cause Data Corruption
Advisory EMIF_10
Revision(s) Affected: 1.0 and 1.1
Details: When performing a block write immediately following a block read, data may get corrupted.
See the example below.
Example:
Write 0x55 to addr1
Write 0xAA to addr2
Read addr1
Read addr2
When executed, the above code will follow this order:
Write 0x55 to addr1
Read addr1
Write 0xAA to addr2
Read addr2
Assembler Notification: None
Workaround: Insert two NOPs between write and read. Since reads occur before writes in the pipeline, the
read must be delayed after the write so that the read does not occur before the write.
EMIF Asynchronous Access Hold = 0 is Not Valid for Strobe > 3
Advisory EMIF_11
Revision(s) Affected: 1.0 and 1.1
Details: For asynchronous EMIF accesses, a hold time of 0 is not valid for strobe lengths greater than
3 cycles if the ARDY_OFF bit is not set. If the above configuration is used but the ARDY_OFF
bit is clear, then the EMIF automatically gives a hold time of 1 cycle.
Assembler Notification: None
Workaround: None

SPRZ200E
TMS320VC5509A Silicon Errata
16
8-Bit Asynchronous Writes on 5509A EMIF Not Supported
Advisory EMIF_12
Revision(s) Affected: 1.0 and 1.1
Details: 8-bit asynchronous writes are not supported; however, 8-bit asynchronous reads are
supported.
Assembler Notification: None
Workaround: None
After Changing CE Control Registers and Disabling SDRAM Clock in Divide-by-8 and
Divide-by-16 Modes, Asynchronous Access Followed by SDRAM Access Will Not Supply
a Ready Signal to CPU
Advisory EMIF_13
Revision(s) Affected: 1.0 and 1.1
Details: If the SDRAM clock (EMIF.CLKMEM) is set to divide-by-8 and divide-by-16 of the CPU clock
and if the user disables the SDRAM clock before accessing asynchronous memory, the EMIF
will fail to supply the ready signal to the CPU under the following two conditions:
•Case 1:
SDRAM access
Switch off the SDRAM clock
Change CE Space Control Register to Asynchronous Mode
Perform an asynchronous access to the same CE space
•Case 2:
SDRAM access
Switch off the SDRAM clock
Change CE Space Control Register to Asynchronous Mode
Perform an asynchronous access to a different CE space
This failure of the ready signal will make the CPU wait indefinitely.
Assembler Notification: None
Workaround: Switch the SDRAM clock to divide-by-1 before programming the CE Space Control Register to
asynchronous memory.

SPRZ200E
TMS320VC5509A Silicon Errata
17
SETUP = 2 Configuration is not Valid for Asynchronous Memory
Advisory EMIF_14
Revision(s) Affected: 1.0 and 1.1
Details: When using the EMIF in asynchronous memory mode, a read or write SETUP time setting of
two clocks actually behaves like timing of one clock of setup time.
Assembler Notification: None
Workaround: If a read setup time of two clocks is required for asynchronous memory, a value of three clock
cycles must be used.

SPRZ200E
TMS320VC5509A Silicon Errata
18
3.6 Enhanced Host Port Interface (EHPI) Advisories
HPID Read Following a HPID Write While HRDY Low Corrupts the Read
Advisory EHPI_5
Revision(s) Affected: 1.0 and 1.1
Details: Whether in muxed or non-muxed mode, if a data read overlaps with a HRDY low from a
previous data write, the EHPI address used for the read access will be the same as the one
preceding the data write.
The only case not affected by this bus is the non-autoincremented write−>read from the same
address. In the case of autoincremented write followed by autoincremented read, normally, the
address will be incremented after the write, but if the read access is initiated while the HRDY
is low, it will not be incremented due to the problem. If one more autoincremented read is
performed after this, the EHPI address used will be twice the incremented version.
Assembler Notification: N/A
Workaround:
•Muxed Mode: Following a sequence of EHPI write(s), perform a HPIA update before
initiating an EHPI read access.
•Non-Muxed Mode: Following a sequence of EHPI write(s), add a dummy HPID read
before initiating the actual EHPI read access.
HPIC/HPIA Access Following an Autoincremented HPID Write Causes Next HPID
Address to Increment to the Incorrect Address
Advisory EHPI_6
Revision(s) Affected: 1.0 and 1.1
Details: If any HPIA/HPIC access is pipelined with a previous autoincremented write, the succeeding
autoincremented HPID access (whether write or read) will use the same address as the
previous write. In other words, the address will not be incremented. Only Muxed Mode is
affected.
Assembler Notification: None
Workaround: Muxed Mode: Following a sequence of EHPI write(s), perform an HPIA update before
initializing an EHPI read/write access.

SPRZ200E
TMS320VC5509A Silicon Errata
19
HRDY is Always Driven
Advisory EHPI_7
Revision(s) Affected: 1.0 and 1.1
Details: HRDY is always driven to the same value as its internal state. This is only a problem when a
single system has devices that have ready signals that are used in conjunction with the DSP’s
HRDY signal. This could include a single system with multiple DSPs using their HRDY signals
in conjunction to signal a master device of their ready status.
Workaround: Logically AND all ready signals with the DSP’s HRDY signal to generate a valid ready status.