Topway LMT070DICFWD-NJN User manual

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LMT070DICFWD-NJN
LCD Module User Manual
Prepared by:
Liutihou
Checked by: Approved by:
Date: 2016 11 23 Date: Date:
Rev. Descriptions Release Date
0.1 Preliminary 2016 06 27
0.2 Update 5.1 describe 2016 11 23

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Table o Content
1. General Speci ication .............................................................................................................. 3
2. Block Diagram .......................................................................................................................... 3
3. Terminal Functions .................................................................................................................. 4
3.1 Interface ................................................................................................................................. 4
4. Absolute Maximum Ratings .................................................................................................... 5
5. Electrical Characteristics ........................................................................................................ 5
5.1 DC Characteristics (MCU terminal) ........................................................................................ 5
6. AC Characteristics ................................................................................................................... 5
6.1 AC Timing .............................................................................................................................. 5
6.2 TFT Controller Reset Timing .................................................................................................. 6
6.3 Panel Setting of Timing .......................................................................................................... 7
7. Commands ............................................................................................................................... 8
8. Optical Characteristics .......................................................................................................... 31
9. Precautions o using LCD Modules ..................................................................................... 33

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1. General Speci ication
Note:
*1 Color tune may slightly changed by temperature and driving voltage.
*2. For saturated color display content (eg. pure red, pure green, pure blue, or pure colors combinations)
*3. For "color scales" display content
2. Block Diagram
Screen Size(Diagonal) : 7.0”
Outline Dimension : 190.0 x 112.0x 12.1max (mm)
(see attached drawing for details)
Active Area : 154.08 x 85.92 (mm)
Color Depth: 65k
Number of dots : 800 x 480
Pixel Pitch : 0.1296 x0.179 (mm)
Pixel Configuration : R.G.B. Vertical Stripe
Backlight : White LED
Surface Treatment : Anti Glare Treatment
Viewing Direction : 6 o’clock ( Gray scale Inversion )(*2)
12 o’clock (*3)
Operating Temperature : 20 ~ +70°C
Storage Temperature : 30 ~ +80°C
Backlight ON/OFF
Backlight brightness
800 x 480 pixels
TFT Panel
Backlight Circuit
DB0~DB15
VDD, VSS
/RST, /RD, /WR, RS, /CS, /WAIT, /INT
RA8875 or equivalent
PWM1(REG[8Ah],REG[8Bh])
PWM2(REG[8Ch])

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3. Terminal Functions
3.1 Inter ace
Pin No. Pin Name I/O Descriptions Note
1 VSS(0V) P Power Ground
2 VDD(5.0V) P Positive Power Supply
3 VDD(5.0V)
4 RS I
Register Select
RS = H, status read/command write
cycle is selected.
RS = L, data Read/Write cycle is
selected.
5 /WR I
/WR=L H, RD=H;
Data or Instruction latch into the LCD
module
6 /RD I
/WR=H, /RD=L;
Data or Status read form the LCD
module
7 /CS I
Chip Select
/CS=L, enable access to the LCD
interface
/CS=H, disable access to the LCD
interface
8 VSS(0V) P Power Ground
9 /WAIT O
Controller busy signal output,
MCU should poll this signal before
accessing the LCD module
10 /INT O Interrupt signal output
11 /RST I
Reset signal
/RST = L, Initialization is executed
/RST = H, Normal running.
12 DB0 I Data Input
: : : :
19 DB7 I Data Input
20 VSS(0V) P Power Ground
21 VDD(5.0V) P Positive Power Supply
22 VSS(0V) P Power Ground
23 DB8 I Data Input
: : : :
30 DB15 I Data Input

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4. Absolute Maximum Ratings
Items Symbol Min. Max. Unit Condition
Supply Voltage VDD 0.3 +7.0 V GND = 0V
Operating Temperature TOP 20 +70 ℃ No Condensation
Storage Temperature TST 30 +80 ℃ No Condensation
Cautions:
Any Stresses exceeding the Absolute Maximum Ratings may cause substantial damage to the device. Functional
operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure
to extreme conditions may affect device reliability.
5. Electrical Characteristics
5.1 DC Characteristics (MCU terminal)
VDD=5.0V, VSS=0V, TOP =25℃
Items Symbol MIN. TYP. MAX. Unit Applicable Pin
Operating Voltage VDD 4.7 5.0 5.3 V VDD
Input High Voltage VIH 3.0V 3.3 V /RD, /WR, RS, /CS,
DB0~DB15, /RST
Input Low Voltage VIL VSS 0.5 V
Output Signal High Voltage VOH 3.3 V DB0~DB15, /WAIT, /INT
Output Signal Low Voltage VOL VSS V
Operating Current IDD 350 mA All black, Backlight ON(*1)
120 mA All black, Backlight OFF(*2)
Note:
*1.REG[8Ch]=40H For Backlight ON.
*2.REG[8Ch]=00H For Backlight OFF.
*3.REG[8Ah]=85H , REG[8Bh]=00H~FFH For Backlight brightness PWM Duty (3.7kHz PWM Freq.) .
6. AC Characteristics
6.1 AC Timing
VDD=5.0V, VSS=0V, TOP =25
℃
Parameter Symbol Spec. Unit Description
Min. Typ Max.
Cycle time tCYC8 71
ns
tc is one system
clock period:
tc = 1/SYS_CLK
Strobe Pulse width tCCC8 28
Address setup time tAS8 5
Address hold time tAH8 14
Data setup time tDS8 28
Data hold time tDH8 14
Data output access time tACC8 0 14
Data output hold time tOH8 0 14
Note:1. Refer to the RA8875 datasheet for more details.
2. SYS_CLK (System clock) = 30MHz

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Register Write/Read timing ( or CPU 16 Bit)
6.2 TFT Controller Reset Timing
VSS=0V, VDD=5.0V, TOP=25°C
Item Symbol MIN. TYP. MAX. Unit
Reset setup time trs 2 ms
Reset pulse trst 0.2 ms
Reset hold time trh 2 ms

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6.3 Panel Setting o Timing
Parameter Symbol Spec Unit Remark
MIN. TYP. MAX.
Horizontal Display Area thd 800 CLKIN
CLKIN Frequency(60HZ) fclk 30 50 MHZ
One Horizontal Line th 889 928 1143 CLKIN
HSD pulse width thpw 1 48 255 CLKIN
HSD Blanking thb 88 CLKIN
HSD Front Porch thfp 1 40 255 CLKIN
Vertical Display Area tvd 480 TH
VSD period time tv 513 525 767 TH
VSD pulse width tvpw 3 3 255 TH
VSD Blanking(tvb) tvb 32 TH
VSD Front Porch(tvfp) tvfp 1 13 255 TH

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7. Commands
REG[01h] Power and Display Control Register (PWRR)
Bit Description De ault Access
7
LCD Display Off
0:display off.
1:display on.
0 RW
6 2 NA 0 RO
1
Sleep Mode
0:Normal mode.
1:Sleep mode.
Note:
1.There are 3 ways to wake up from sleep mode:
Touch Panel wake up,Key Scan wake up,Software wake up.
2. When using IIC, this function is not supported.
3. When using SPI, it has its particular steps to use this
function, refer to section 6 1 2 3 please.
0 RW
0
So tware Reset
0 : No action.
1 : Software Reset.
Note:The bit must be set to 1 and then set to 0 to complete
a software reset
0 WO
REG[02h] Memory Read/Write Command (MRWC)
Bit Description De ault Access
7 0
Write Function : Memory Write Data
Data to write in memory corresponding to the setting of
MWCR1[3:2].Continuous data write cycle can be accepted in
bulk data write case.
Read Function : Memory Read Data
Data to read from memory corresponding to the setting of
MWCR1[3:2]. Continuous data read cycle can be accepted in
bulk data read case. Note that the first data read cycle is
dummy read and need to be ignored.
RW
REG[04h] Pixel Clock Setting Register (PCSR)
Bit Description De ault Access
7
PCLK Inversion
0 : PDAT is fetched at PCLK rising edge.
1 : PDAT is fetched at PCLK falling edge.
0 RW
6 2 NA 0 RO
1 0
PCLK Period Setting
pixel clock (PCLK) period setting.
00b: PCLK period = System Clock period.
01b: PCLK period = 2 times of System Clock period.
10b: PCLK period = 4 times of System Clock period.
11b: PCLK period = 8 times of System Clock period.
0 RW

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REG[05h] Serial Flash/ROM Con iguration Register (SROC)
Bit Description De ault Access
7
Serial Flash/ROM I/F # Select
0: Serial Flash/ROM 0 I/F is selected.
1: Serial Flash/ROM 1 I/F is selected.
0 RW
6
Serial Flash/ROM Address Mode
0: 24 bits address mode
This bit must set to 0 for serial flash .
0 RW
5
Serial Flash/ROM Wave orm Mode
Mode 0.
Mode 3.
0 RW
4 3
Serial Flash /ROM Read Cycle
00b: 4 bus no dummy cycle
01b: 5 bus 1 byte dummy cycle
1xb: 6 bus 2 byte dummy cycle
0 RW
2
Serial Flash /ROM Access Mode
0: Font mode
1: DMA mode
0 RW
1 0
Serial Flash /ROM I/F Data Latch Mode Select
0xb: Single Mode
10b: Dual Mode 0.
11b: Dual Mode 1.
0 RW
REG[06h] Serial Flash/ROM CLK Setting Register(SFCLR)
Bit Description De ault Access
7 2 NA 0 RO
1 0
Serial Flash/ROM Clock Frequency Setting
0xb: SFCL frequency = System clock frequency
(When DMA enable and Color depth = 256 color)
SFCL frequency = System clock frequency /2)
10b: SFCL frequency = System clock frequency / 2
11b: SFCL frequency = System clock frequency / 4
0 RW
REG[10h] System Con iguration Register (SYSR)
Bit Description De ault Access
7 4 N/A 0 RO
3 2
Color Depth Setting
00b : 8 bpp generic TFT, i.e. 256 colors.
1xb : 16 bpp generic TFT, i.e. 65K colors.
0 RW
1 0
MCUIF Selection
00b : 8 bit MCU Interface.
1xb : 16 bit MCU Interface.
0 RW
REG[12h] GPI
Bit Description De ault Access
7 5 NA 0 RO
4 0
GPI[4:0] : General Purpose Input.
KEY_EN = 0: General Purpose Input from pin KIN[4:0]
KEY_EN = 1: NC
NA RO
Note:KEY_EN : REG[C0h] bit 7
REG[13h] GPO
Bit Description De ault Access
7 4 NA 0 RO
3 0
GPO[3:0] : General Purpose Output
KEY_EN = 0: General Purpose Output to KOUT[3:0]
KEY_EN = 1: NC
0 RW
Note: KxY_EN : REG[C0h] bit 7

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REG[14h] LCD Horizontal Display Width Register (HDWR)
Bit Description De ault Access
7 NA 0 RO
6 0
Horizontal Display Width Setting Bit[6:0]
The register specifies the LCD panel horizontal display width
in the unit of 8 pixels resolution.
Horizontal display width(pixels) = (HDWR + 1)x8
0 RW
Not
e : HDWR must be set less than 64h because that the maximum horizontal display width is 800 pixels .
REG[15h] Horizontal Non-Display Period Fine Tuning Option Register (HNDFTR)
Bit Description De ault Access
7
DE Polarity
0 : high active.
1 : low active.
0 RW
6 4 NA 0 RO
3 0
Horizontal Non-Display Period Fine Tuning(HNDFT) [3:0]
This register specifies the fine tuning for horizontal non
display period; it is used to support the SYNC mode panel.
Each level of this modulation is 2 pixel.
0 RW
REG[16h] LCD Horizontal Non-Display Period Register (HNDR)
Bit Description De ault Access
7 5 NA 0 RO
4 0
Horizontal Non-Display Period(HNDP) Bit[4:0]
This register specifies the horizontal non display period.
Horizontal Non Display Period (pixels)
=(HNDR + 1)x8+(HNDFTR/2+1)x2 + 2
0 RW
REG[17h] HSYNC Start Position Register (HSTR)
Bit Description De ault Access
7 5 NA 0 RO
4 0
HSYNC Start Position[4:0]
The starting position from the end of display area to the
beginning of HSYNC. Each level of this modulation is 8 pixel.
HSYNC Start Position(pixels) = (HSTR + 1)x8
0 RW
REG[18h] HSYNC Pulse Width Resister (HPWR)
Bit Description De ault Access
7
HSYNC Polarity
0 : Low active.
1 : High active.
0 RW
6 5 NA 0 RO
4 0
HSYNC Pulse Width(HPW) [4:0]
The period width of HSYNC.
HSYNC Pulse Width(pixels) = (HPW + 1)x8
0 RW
REG[19h] LCD Vertical Display Height Register (VDHR0)
Bit Description De ault Access
7 0 Vertical Display Height Bit[7:0]
Vertical display Height(Line) = VDHR + 1 0 RW
REG[1Ah] LCD Vertical Display Height Register0 (VDHR1)
Bit Description De ault Access
7 1 NA 0 RO
0 Vertical Display Height bit[8]
Vertical Display Height(Line) = VDHR + 1 0 RW
Note
: The VDHR must be set less than 1E0h, because the maximum vertical display height is 480.

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REG[1Bh] LCD Vertical Non-Display Period Register (VNDR0)
Bit Description De ault Access
7 0 Vertical Non-Display Period Bit[7:0]
Vertical Non Display Period(Line) = (VNDR + 1) 0 RW
REG[1Ch] LCD Vertical Non-Display Period Register (VNDR1)
Bit Description De ault Access
7 1 NA 0 RO
0 Vertical Non-Display Period bit[8]
Vertical Non Display Period(Line) = (VNDR + 1) 0 RW
REG[1Dh] VSYNC Start Position Register (VSTR0)
Bit Description De ault Access
7 0
VSYNC Start Position[7:0]
The starting position from the end of display area to the
beginning of VSYNC.
VSYNC Start Position(Line) = (VSTR + 1)
0 RW
REG[1Eh] VSYNC Start Position Register (VSTR1)
Bit Description De ault Access
7 1 NA 0 RO
0
VSYNC Start Position[8]
The starting from the end of display area to the beginning of
VSYNC.
VSYNC Start Position(Line) = (VSTR + 1)
0 RW
REG[1Fh] VSYNC Pulse Width Register (VPWR)
Bit Description De ault Access
7
VSYNC Polarity
0 : Low active.
1 : High active.
0 RW
6 0
VSYNC Pulse Width[6:0]
The pulse width of VSYNC in lines.
VSYNC Pulse Width(Line) = (VPWR + 1)
0 RW
REG[20h] Display Con iguration Register (DPCR)
Bit Description De ault Access
7
Layer Setting Control
0 : One layer configuration is selected.
1 : Two layers configuration is selected.
0 RW
6 4 NA 0 RO
3
HDIR
Horizontal Scan Direction, for n = SEG number.
0 : SEG0 to SEG(n 1).
1 : SEG(n 1) to SEG0.
0 RW
2
VDIR
Vertical Scan direction, for n = COM number
0 : COM0 to COM(n 1).
1 : COM(n 1) to COM0.
0 RW
1 0 NA 0 RO

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REG[21h] Font Control Register 0 (FNCR0)
Bit Description De ault Access
7
CGRAM/CGROM Font Selection Bit in Text Mode
0 : CGROM font is selected.
1 : CGRAM font is selected.
Note:
1. The bit is used to select the bit map source when text mode
is active(REG[40h] bit 7 is 1), when CGRAM is
writing(REG[41h] bit 3 2 =01b), the bit must be set as “0”.
2. When CGRAM font is select, REG[21h] bit 5 must be set as
1.
0 RW
6 NA 0 RO
5
External/Internal CGROM Selection Bit
0 : Internal CGROM is selected.(REG[2Fh] must bx set 00h )
1 : External CGROM is selected. (REG[2Eh] bit6 &bit7 must
be set 0)
0 RW
4 2 NA 0 RO
1 0
Font Selection or internal CGROM
When FNCR0 B7 = 0 and B5 = 0, Internal CGROM supports
the 8x16 character sets with the standard coding of ISO/IEC
8859 1~4, which supports English and most of European
country languages.
00b : ISO/IEC 8859 1.
01b : ISO/IEC 8859 2.
10b : ISO/IEC 8859 3.
11b : ISO/IEC 8859 4.
0 RW
REG[22h] Font Control Register1 (FNCR1)
Bit Description De ault Access
7
Full Alignment Selection Bit
0 : Full alignment is disable.
1 : Full alignment is enable.
0 RW
6
Font Transparency
0 : Font with background color.
1 : Font with background transparency.
0 RW
5 NA 0 RO
4
Font Rotation
0 : Normal.
1 : 90 degree display.
0 RW
3 2
Horizontal Font Enlargement
00b : X1.
01b : X2.
10b : X3.
11b : X4.
0 RW
1 0
Vertical Font Enlargement
00b : X1.
01b : X2.
10b : X3.
11b : X4.
0 RW
REG[23h] CGRAM Select Register (CGSR)
Bit Description De ault Access
7 0
CGRAM No.
The setting of the number of the character in CGRAM. It’s
used to write the user defined character bitmap data into
CGRAM. 16 continuous data write cycles compete the bitmap
writing of a 8x16 character. Note that the MWCR1 bit 3 2 must
be set as 01b(CGRAM) first. And more than 16 data write
cycles will loop back to the 1st data and cover the bitmap.
0 RW

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REG[24h] Horizontal Scroll O set Register 0 (HOFS0)
Bit Description De ault Access
7 0
Horizontal Display Scroll O set [7:0]
The display offset of the horizontal direction, changing the
value will cause the effect of scrolling at horizontal direction.
0 RW
REG[25h] Horizontal Scroll O set Register 1 (HOFS1)
Bit Description De ault Access
7 3 NA 0 RO
2 0
Horizontal Display Scroll O set [10:8]
The display offset of the horizontal direction, changing the
value will cause the effect of scrolling at horizontal direction.
0 RW
REG[26h] Vertical Scroll O set Register 0 (VOFS0)
Bit Description De ault Access
7 0
Vertical Display Scroll O set [7:0]
The display offset of the vertical direction, changing the
value will cause the effect of scrolling at vertical direction.
0 RW
REG[27h] Vertical Scroll O set Register 1 (VOFS1)
Bit Description De ault Access
7 2 NA 0 RO
1 0
Vertical Display Scroll O set [9:8]
The display offset of the v ertical direction, changing the
value will cause the effect of scrolling at vertical direction.
0 RW
REG[29h] Font Line Distance Setting Register (FLDR)
Bit Description De ault Access
7 5 NA 0 RO
4 0
Font Line Distance Setting
Setting the font character line distance when setting
memory font write cursor auto move. (Unit: pixel)
0 RW
REG[2Ah] Font Write Cursor Horizontal Position Register 0 (F_CURXL)
Bit Description De ault Access
7 0 Font Write Cursor Horizontal Position[7:0]
The setting of the horizontal cursor position for font writing. 0 RW
REG[2Bh] Font Write Cursor Horizontal Position Register 1 (F_CURXH)
Bit Description De ault Access
7 2 NA 0 RO
1 0 Font Write Cursor Horizontal Position[9:8]
The setting of the horizontal cursor position for font writing. 0 RW
REG[2Ch] Font Write Cursor Vertical Position Register 0 (F_CURYL)
Bit Description De ault Access
7 0 Font Write Cursor Vertical Position[7:0]
The setting of the vertical cursor position for font writing. 0 RW
REG[2Dh] Font Write Cursor Vertical Position Register 1 (F_CURYH)
Bit Description De ault Access
7 1 NA 0 RO
0 Font Write Cursor Vertical Position[8]
The setting of the vertical cursor position for font writing. 0 RW

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REG[2Eh] Font Write Type Setting Resister
Bit Description De ault Access
7 6
Font Size Setting
Full Size Hal -Size Variable
Width
00b 16x16 8x16 NX16
01b 24x24 12x24 NX24
1Xb 32x32 16x32 NX32
Note: The font width indicated by “N” depends on the
character code of the FONT.
0 RW
5 0
Font to Font Width Setting
00h : Font width off
01h : Font to Font width = 1 pixel
02h : Font to Font width = 2 pixels
:
:
3Fh : Font to Font width = 63 pixels
0 RW
REG[2Fh] Serial Font ROM Setting
Bit Description De ault Access
7 5
GT Serial Font ROM Select
000b: GT21L16TW / GT21H16T1W
001b: GT30L16U2W
010b: GT30L24T3Y / GT30H24T3Y
011b: GT30L24M1Z
100b: GT30L32S4W / GT30H32S4W
0 RW
4 2
FONT ROM Coding Setting
For specific GT serial Font ROM, the coding method must
be set for decoding.
000b: GB2312
001b: GB12345/GB18030
010b: BIG5
011b: UNICODE
100b: ASCII
101b: UNI Japanese
110b: JIS0208
111b: Latin/Greek/ Cyrillic / Arabic
0 RW
1 0
ASCII / Latin/Greek/ Cyrillic / Arabic Latin
ASCII Latin/Greek/
Cyrillic
Arabic
Latin
00b Normal Normal NA
01b Arial Variable
Width
Presentation
forms A
10b Roman NA Forms B
11b Bold NA NA
0 RW
REG[30h] Horizontal Start Point 0 o Active Window (HSAW0)
Bit Description De ault Access
7 0 Horizontal Start Print o active Window [7:0] 0 RW
REG[31h] Horizontal Start Point 1 o active Window (HSAW1)
Bit Description De ault Access
7 2 NA 0 RO
1 0 Horizontal Start Point o Active Window [9:8] 0 RW
REG[32h] Vertical Start Point 0 o Active Window (VSAW0)
Bit Description De ault Access
7 0 Vertical Start Point o Active Window [7:0] 0 RW

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REG[33h] Vertical Start Point 1 o Active Window (VSAW1)
Bit Description De ault Access
7 1 NA 0 RO
0 Vertical Start Point o Active Window [8] 0 RW
REG[34h] Horizontal End Point 0 o Active Window (HEAW0)
Bit Description De ault Access
7 0 Horizontal End Point o Active Window [7:0] 0 RW
REG[35h] Horizontal End Point 1 o Active Window (HEAW1)
Bit Description De ault Access
7 2 NA 0 RO
1 0 Horizontal End Point o Active Window [9:8] 0 RW
REG[36h] Vertical End Point o Active Window 0 (VEAW0)
Bit Description De ault Access
7 0 Vertical End Point o Active Window [7:0] 0 RW
REG[37h] Vertical End Point o Active Window 1 (VEAW1)
Bit Description De ault Access
7 1 NA 0 RO
0 Vertical End Point o Active Window [8] 0 RW
REG[38h] Horizontal Start Point 0 o Scroll Window (HSSW0)
Bit Description De ault Access
7 0 Horizontal Start Point o Scroll Window [7:0] 0 RW
REG[39h] Horizontal Start Point 1 o Scroll Window (HSSW1)
Bit Description De ault Access
7 2 NA 0 RO
1 0 Horizontal Start Point o Scroll Window [9:8] 0 RW
REG[3Ah] Vertical Start Point 0 o Scroll Window (VSSW0)
Bit Description De ault Access
7 0 Vertical Start Point o Scroll Window [7:0] 0 RW
REG[3Bh] Vertical Start Point 1 o Scroll Window (VSSW1)
Bit Description De ault Access
7 1 NA 0 RO
0 Vertical Start Point o Scroll Window [8] 0 RW
REG[3Ch] Horizontal End Point 0 o Scroll Window (HESW0)
Bit Description De ault Access
7 0 Horizontal End Point o Scroll Window [7:0] 0 RW
REG[3Dh] Horizontal End Point 1 o Scroll Window (HESW1)
Bit Description De ault Access
7 2 NA 0 RO
1 0 Horizontal End Point o Scroll Window [9:8] 0 RW
REG[3Eh] Vertical End Point 0 o Scroll Window (VESW0)
Bit Description De ault Access
7 0 Vertical End Point o Scroll Window [7:0] 0 RW
REG[3Fh] Vertical End Point 1 o Scroll Window (VESW1)
Bit Description De ault Access
7 1 NA 0 RO
0 Vertical End Point o Scroll Window [8] 0 RW

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REG[40h] Memory Write Control Register 0 (MWCR0)
Bit Description De ault Access
7
Text Mode enable
0 : Graphic mode.
1 : Text mode.
0 RW
6
Font Write Cursor/ Memory Write Cursor Enable
0 : Font write cursor/ Memory Write Cursor is not visible.
1 : Font write cursor/ Memory Write Cursor is visible.
0 RW
5
Font Write Cursor/ Memory Write Cursor Blink Enable
0 : Normal display.
1 : Blink display.
0 RW
4 NA 0 RO
3 2
Memory Write Direction (Only or Graphic Mode)
00b : Left Right then Top Down.
01b : Right Left then Top Down.
10b : Top Down then Left Right.
11b : Down Top then Left Right.
0 RW
1
Memory Write Cursor Auto-Increase Disable
0 : Cursor auto increases when memory write.
1 : Cursor doesn’t auto increases when memory write.
0 RW
0
Memory Read Cursor Auto-Increase Disable
0 : Cursor auto increases when memory read.
1 : Cursor doesn’t auto increases when memory read.
0 RW
REG[41h] Memory Write Control Register 1 (MWCR1)
Bit Description De ault Access
7
Graphic Cursor Enable
0 : Graphic Cursor disable.
1 : Graphic Cursor enable.
0 RW
6 4
Graphic Cursor Selection Bit
Select one from eight graphic cursor types.(000b to 111b)
000b : Graphic Cursor Set 1.
001b : Graphic Cursor Set 2.
010b : Graphic Cursor Set 3.
: :
111b : Graphic Cursor Set 8.
0 RW
3 2
Write Destination Selection
00b : Layer 1~2.
01b : CGRAM.
10b : Graphic Cursor.
11b : Pattern.
Note : When CGRAM is selected (01b), REG[21h] bit 7 must
be set as “0”.
0 RW
1 NA 0 RO
0
Layer No. or Read/Write Selection
When resolution =< 480x400 or color depth = 8bpp:
0 : Layer 1.
1 : Layer 2.
When resolution > 480x400 and color depth > 8bpp:
NA, always writing to Layer 1.
0 RW
REG[44h] Blink Time Control Register (BTCR)
Bit Description De ault Access
7 0
Text Blink Time Setting (Unit: Frame)
00h : 1 frame time.
01h : 2 frames time.
02h : 3 frames time.
:
:
:
FFh : 256 frames time.
0 RW

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REG[45h] Memory Read Cursor Direction (MRCD)
Bit Description De ault Access
7 2 NA 0 RO
1 0
Memory Read Direction (Only or Graphic Mode)
00b : Left Right then Top Down.
01b : Right Left then Top Down.
10b : Top Down then Left Right.
11b : Down Top then Left Right.
0 RW
REG[46h] Memory Write Cursor Horizontal Position Register 0 (CURH0)
Bit Description De ault Access
7 0 Memory Write Cursor Horizontal Location[7:0] 0 RW
REG[47h] Memory Write Cursor Horizontal Position Register 1 (CURH1)
Bit Description De ault Access
7 2 NA 0 RO
1 0 Memory Write Cursor Horizontal Location[9:8] 0 RW
REG[48h] Memory Write Cursor Vertical Position Register 0 (CURV0)
Bit Description De ault Access
7 0 Memory Write Cursor Vertical Location[7:0] 0 RW
REG[49h] Memory Write Cursor Vertical Position Register 1 (CURV1)
Bit Description De ault Access
7 1 NA 0 RO
0 Memory Write Cursor Vertical Location[8] 0 RW
REG[4Ah] Memory Read Cursor Horizontal Position Register 0 (RCURH0)
Bit Description De ault Access
7 0 Memory Read Cursor Horizontal Location[7:0] 0 RW
REG[4Bh] Memory Read Cursor Horizontal Position Register 1 (RCURH01)
Bit Description De ault Access
7 2 NA 0 RO
1 0 Memory Read Cursor Horizontal Location[9:8] 0 RW
REG[4Ch] Memory Read Cursor Vertical Position Register 0 (RCURV0)
Bit Description De ault Access
7 0 Memory Read Cursor Vertical Location[7:0] 0 RW
REG[4Dh] Memory Read Cursor Vertical Position Register 1 (RCURV1)
Bit Description De ault Access
7 1 NA 0 RO
0 Memory Read Cursor Vertical Location[8] 0 RW
REG[4Eh] Font Write Cursor and Memory Write Cursor Horizontal Size Register (CURHS)
Bit Description De ault Access
7 5 NA 0 RO
4 0
Font Write Cursor Horizontal Size Setting[4:0]
Unit : Pixel
Note : When font is enlarged, the cursor setting will multiply
the same times as the font enlargement.
7h RW

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REG[4Fh] Font Write Cursor Vertical Size Register (CURVS)
Bit Description De ault Access
7 5 NA 0 RO
4 0
Font Write Cursor Vertical Size Setting[4:0]
Unit : Pixel
Note : When font is enlarged, the cursor setting will multiply
the same times as the font enlargement.
0 RW
REG[50h] BTE Function Control Register 0 (BECR0)
Bit Description De ault Access
7
BTE Function Enable / Status
Write
0 : No action.
1 : BTE function enable.
Read
0 : BTE function is idle.
1 : BTE function is busy.
0 RW
6
BTE Source Data Select
0 : Block mode,the Source BTE is stored as a rectangular
region of memory.
1 : Linear mode, the Source BTE is stored as a continuous
block of memory.
0 RW
5
BTE Destination Data Type Select
0 : Block mode, the Destination BTE is stored as a rectangular
region of memory.
1 : Linear mode, the Destination BTE is stored as a
continuous block of memory.
0 RW
4 0 NA 0 RO
REG[51h] BTE Function Control Register1 (BECR1)
Bit Description De ault Access
7 5
BTE ROP Code Bit[3:0]
ROP is the acronym for Raster Operation. Some of BTE
operation code has to collocate with ROP for the detailed
function. (Please refer to the Section 7 6)
0 RW
4 0
BTE Operation Code Bit[3:0]
RA8875 includes a 2D BTE Engine, it can execute 13 BTE
functions, the operation code range is from 1100b to 0000b
and 1111b to 1101b are not used. Some of BTE Operation
Code has to collocate with the ROP code for the advance
function. (Please refer to the Section 7 6)
0 RW
REG[68h] Background Color Register or Transparent 1 (BGTR1)
Bit Description De ault Access
7 6 NA 0 RO
5 0
Foreground Color Green[5:0]
If REG[10h] Bit[3:2] is set to 256 colors, the register only uses
Bit[2:0].
If REG[10h] Bit[3:2] is set to 65K colors, the register uses
Bit[5:0].
0 RW
REG[69h] Background Color Register or Transparent 2 (BGTR2)
Bit Description De ault Access
7 5 NA 0 RO
4 0
Foreground Color Blue[4:0]
If REG[10h] Bit[3:2] is set to 256 colors, the register only uses
Bit[1:0].
If REG[10h] Bit[3:2] is set to 65K colors, the register uses
Bit[4:0].
0 RW

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REG[70h] Touch Panel Control Register 0 (TPCR0)
Bit Description De ault Access
7
Touch Panel Enable Bit
0 : Disable
1 : Enable
0 RW
6 4
TP Sample Time Adjusting
000b : Wait 512 system clocks period for ADC data ready.
001b : Wait 1024 system clocks period for ADC data ready.
010b : Wait 2048 system clocks period for ADC data ready.
011b : Wait 4096 system clocks period for ADC data ready.
100b : Wait 8192 system clocks period for ADC data ready.
101b : Wait 16384 system clocks period for ADC data ready.
110b : Wait 32768 system clocks period for ADC data ready.
111b : Wait 65536 system clocks period for ADC data ready.
0 RW
3
Touch Panel Wakeup Enable
0 : Disable the Touch Panel wake up function.
1 : Touch Panel can wake up the sleep mode.
0 RW
2 0
ADC Clock Setting
000b : System CLK
001b : (System CLK) / 2.
010b : (System CLK) x 4.
011b : (System CLK) / 8.
100b : (System CLK) x 16.
101b : (System CLK) / 32.
110b : (System CLK) / x64.
111b : (System CLK) / 128.
0 RW
REG[71h] Touch Panel Control Register 1 (TPCR1)
Bit Description De ault Access
7 N/A 0 RO
6
TP Manual Mode Enable
0 : Auto mode.
1 : Using the manual mode.
0 RW
5
TP ADC Re erence Voltage Source
0 : Vref generated from internal circuit. No external voltage is
needed.
1 : Vref from external source, 1/2 VDD is needed for ADC.
0 RW
4 3 NA 0 RO
2
De-bounce Circuit Enable or Touch Panel Interrupt
0: De bounce circuit disable.
1: De bounce circuit enable.
0 RW
1 0
Mode Selection or TP Manual Mode
00b : IDLE mode: Touch Panel in idle mode.
01b : Wait for TP event, Touch Panel event could cause the
interrupt or be read from REG[F1h] Bit2.
10b : Latch X data, in the phase, X Data can be latched in
REG[72h] and REG[74h].
11b : Latch Y data, in the phase, Y Data can be latched in
REG[73h] and REG[74h].
0 RW
REG[72h] Touch Panel X High Byte Data Register (TPXH)
Bit Description De ault Access
7 0 Touch Panel X Data Bit[9:2] 0 RW
REG[73h] Touch Panel Y High Byte Data Register (TPYH)
Bit Description De ault Access
7 0 Touch Panel Y Data Bit[9:2] 0 RW

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REG[74h] Touch Panel X/Y Low Byte Data Register (TPXYL)
Bit Description De ault Access
7
ADET
Touch Event Detector
0 : Touch Panel is touched.
1 : Touch Panel is not touched.
1 RO
6 4 NA 0 RO
3 2 Touch Panel Y Data Bit[1:0] 0 RW
1 0 Touch Panel X Data Bit[1:0] 0 RW
REG[80h] Graphic Cursor Horizontal Position Register 0 (GCHP0)
Bit Description De ault Access
7 0 Graphic Cursor Horizontal Location[7:0] 0 RW
REG[81h] Graphic Cursor Horizontal Position Register 1 (GCHP1)
Bit Description De ault Access
7 2 NA 0 RO
1 0 Graphic Cursor Horizontal Location[9:8] 0 RW
REG[82h] Graphic Cursor Vertical Position Register 0 (GCVP0)
Bit Description De ault Access
7 0 Graphic Cursor Vertical Location[7:0] 0 RW
REG[83h] Graphic Cursor Vertical Position Register 1 (GCVP1)
Bit Description De ault Access
7 1 NA 0 RO
0 Graphic Cursor Vertical Location[8] 0 RW
REG[84h] Graphic Cursor Color 0 (GCC0)
Bit Description De ault Access
7 0 Graphic Cursor Color 0 with 256 colors
RGB Format [7:0] = RRRGGGBB. 0 RW
REG[85h] Graphic Cursor Color 1 (GCC1)
Bit Description De ault Access
7 0 Graphic Cursor Color 1 with 256 Colors
RGB Format [7:0] = RRRGGGBB. 0 RW
REG[88h] PLL Control Register 1 (PLLC1)
Bit Description De ault Access
7
PLLDIVM
PLL Pre driver parameter.
0 : divided by 1.
1 : divided by 2.
0 RW
6 5 NA 0 RO
4 0
PLLDIVN[4:0]
PLL input parameter, the value should be 1~31. (i.e. value 0
is forbidden).
0 RW