Ublox EVA-7M User manual

EVA-7M
u-blox 7 GNSS module
Hardware Integration Manual
Abstract
This document describes the hardware features and specifications of
the cost effective EVA-7M GNSS module featuring the u-
blox 7
positioning engine.
The EVA-7M module boasts the industry’s smallest form factor and
is a fully tested standalone solution th
at requires no host
integration.
This module combines exceptional GNSS performance with highly
flexible power, design, and serial communication options.
www.u
-blox.com
UBX
-12003235 - R05

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Document Information
Title EVA-7M
Subtitle u-blox 7 GNSS module
Document type Hardware Integration Manual
Document number UBX-12003235
Revision and date R05 30-Jan-2015
Document status Production Information
Document status explanation
Objective Specification Document contains target values. Revised and supplementary data will be published later.
Advance Information Document contains data based on early testing. Revised and supplementary data will be published later.
Early Production Information Document contains data from product verification. Revised and supplementary data may be published later.
Production Information Document contains the final product specification.
This document applies to the following products:
Product name Type number ROM/FLASH version PCN reference
EVA-7M EVA-7M-0-000 ROM1.00 n/a
u-blox reserves all rights to this document and the information contained herein. Products, names, logos and designs described herein may in
whole or in part be subject to intellectual property rights. Reproduction, use, modification or disclosure to third parties of this document or
any part thereof without the express permission of u-blox is strictly prohibited.
The information contained herein is provided “as is” and u-blox assumes no liability for the use of the information. No warranty, either
express or implied, is given, including but not limited, with respect to the accuracy, correctness, reliability and fitness for a particular purpose
of the information. This document may be revised by u-blox at any time. For most recent documents, visit www.u-blox.com.
Copyright © 2014, u-blox AG.
u-blox® is a registered trademark of u-blox Holding AG in the EU and other countries. ARM® is the registered trademark of ARM Limited in
the EU and other countries.

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Contents
Contents..............................................................................................................................3
1Hardware description ..................................................................................................6
1.1 Overview .............................................................................................................................................. 6
2Design-in.......................................................................................................................7
2.1 Power management ............................................................................................................................. 7
2.1.1 Overview ....................................................................................................................................... 7
2.1.2 Power management configuration ................................................................................................ 8
2.2 Interfaces.............................................................................................................................................. 9
2.2.1 UART interface .............................................................................................................................. 9
2.2.2 Display Data Channel (DDC) Interface ........................................................................................... 9
2.2.3 SPI Interface .................................................................................................................................. 9
2.2.4 USB interface............................................................................................................................... 10
2.3 I/O Pins ............................................................................................................................................... 11
2.3.1 Time pulse................................................................................................................................... 11
2.3.2 External interrupt ........................................................................................................................ 11
2.3.3 Active antenna supervisor............................................................................................................ 11
2.3.4 Electromagnetic interference on I/O lines..................................................................................... 12
2.4 Real-Time Clock (RTC) ........................................................................................................................ 12
2.4.1 RTC using a crystal ...................................................................................................................... 12
2.4.2 RTC derived from the system clock .............................................................................................. 13
2.4.3 RTC using an external clock......................................................................................................... 13
2.4.4 Time aiding ................................................................................................................................. 13
2.5 RF input.............................................................................................................................................. 13
2.5.1 Active Antenna............................................................................................................................ 13
2.5.2 Passive Antenna .......................................................................................................................... 14
2.5.3 Improved Jamming Immunity ...................................................................................................... 14
2.6 RESET_N ............................................................................................................................................. 14
2.7 Design-in checklist .............................................................................................................................. 15
2.7.1 General considerations ................................................................................................................ 15
2.7.2Schematic design-in for EVA-7M ................................................................................................. 15
2.8 Pin description .................................................................................................................................... 16
2.9 Layout design-in checklist ................................................................................................................... 17
2.10 Layout............................................................................................................................................. 17
2.10.1 Footprint ..................................................................................................................................... 18
2.10.2 Paste mask .................................................................................................................................. 19
2.10.3 Placement ................................................................................................................................... 19
2.11 Migration considerations................................................................................................................. 19
2.11.1 C88-7M - Evaluating EVA-7M on existing NEO-xM sockets ......................................................... 19
2.12 EOS/ESD/EMI precautions................................................................................................................ 21

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2.12.1 Abbreviations .............................................................................................................................. 21
2.12.2 Electrostatic Discharge (ESD)........................................................................................................ 21
2.12.3 ESD protection measures............................................................................................................. 22
2.12.4 Electrical Overstress (EOS)............................................................................................................ 22
2.12.5 EOS protection measures............................................................................................................. 22
2.12.6 Applications with cellular modules .............................................................................................. 23
3Product handling & soldering....................................................................................25
3.1 Packaging, shipping, storage and moisture preconditioning ............................................................... 25
3.2 ESD handling precautions ................................................................................................................... 25
3.3 Soldering ............................................................................................................................................ 25
3.3.1 Soldering paste............................................................................................................................ 25
3.3.2 Reflow soldering ......................................................................................................................... 26
3.3.3 Optical inspection........................................................................................................................ 26
3.3.4 Repeated reflow soldering........................................................................................................... 26
3.3.5 Wave soldering............................................................................................................................ 26
3.3.6 Rework........................................................................................................................................ 26
3.3.7 Use of ultrasonic processes.......................................................................................................... 26
4Product testing ...........................................................................................................27
4.1 Test parameters for OEM manufacturer.............................................................................................. 27
4.2 System sensitivity test ......................................................................................................................... 27
4.2.1 Guidelines for sensitivity tests ...................................................................................................... 27
4.2.2 ‘Go/No go’ tests for integrated devices........................................................................................ 27
Appendix ..........................................................................................................................28
AReference schematics .................................................................................................28
A.1 Cost optimized circuit ......................................................................................................................... 28
A.2 Best performance circuit with passive antenna.................................................................................... 29
A.3 Improved jamming immunity with passive antenna............................................................................. 30
A.4 Circuit using active antenna................................................................................................................ 31
A.5 USB self-powered circuit with passive antenna ................................................................................... 32
A.6 USB bus-powered circuit with passive antenna ................................................................................... 33
A.7 Circuit using 2-pin antenna supervisor ................................................................................................ 34
A.8 Circuit using 3-pin antenna supervisor ................................................................................................ 35
A.9 Design-in Recommendations in combination with cellular operation................................................... 36
BComponent selection .................................................................................................37
B.1 External RTC (Y1)................................................................................................................................ 37
B.2 RF band-pass filter (F1) ....................................................................................................................... 37
B.3 External LNA protection filter (F2) ....................................................................................................... 38
B.4 USB line protection (D1) ..................................................................................................................... 38
B.5 USB LDO (U2) ..................................................................................................................................... 38
B.6 External LNA (U1) ............................................................................................................................... 38

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B.7 RF ESD protection diode (D2).............................................................................................................. 39
B.8 Operational amplifier (U6) .................................................................................................................. 39
B.9 Open-drain buffer (U4, U7 and U8) .................................................................................................... 39
B.10 Antenna supervisor switch transistor (T1) ........................................................................................ 39
B.11 Ferrite beads (FB1) .......................................................................................................................... 39
B.12 Feed-thru capacitors ....................................................................................................................... 39
B.13 Inductor (L) ..................................................................................................................................... 39
B.14 Standard capacitors ........................................................................................................................ 40
B.15 Standard resistors ........................................................................................................................... 40
Related documents...........................................................................................................41
Revision history................................................................................................................41
Contact..............................................................................................................................42

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1Hardware description
1.1 Overview
The EVA-7M standalone GNSS module features the reliable performance of the u-blox 7 positioning engine
(receiving GPS, GLONASS, QZSS and SBAS signals). The EVA-7M delivers high sensitivity and minimal acquisition
times in the ultra compact EVA form factor.
The EVA-7M is an ideal solution for cost and space-sensitive applications. It is easy to design-in, only requiring an
external GNSS antenna in most applications. The layout of the EVA‑7M is especially designed to ease the
customer’s design and limit near field interferences since RF and digital domains are kept separated.
EVA-7M uses a crystal oscillator for lower system costs. Like other u-blox GNSS modules, the EVA-7M uses
components selected for functioning reliably in the field over the full operating temperature range.
The EVA-7M is easily integrated in manufacturing, thanks to its QFN-like package and low moisture sensitivity
level. The modules are available in 500 pcs/reel, ideal for small production batches. The EVA-7M module
combines a high level of integration capability with flexible connectivity options in a miniature package. This
makes it perfectly suited for industrial and mass-market end products with strict size and cost requirements. The
DDC (I2C compliant) interface provides connectivity and enables synergies with u-blox cellular modules.
The EVA-7M module is manufactured in ISO/TS 16949 certified sites and qualified as stipulated in the JESD47
standard.
For product features see the EVA-7M Data Sheet [1].
To determine which u-blox product best meets your needs, see the product selector tables on the u-blox
website www.u-blox.com.

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2Design-in
In order to obtain good performance with a GNSS receiver module, there are a number of points that require
careful attention during the design-in. These include:
•Power Supply: Good performance requires a clean and stable power supply.
•Interfaces: Ensure correct wiring, rate and message setup on the module and your host system.
•Antenna interface: For optimal performance, seek short routing, matched impedance and no stubs.
•External LNA: With EVA-7M an additional external LNA is mandatory if a passive antenna is used to
achieve the performance values as written in the EVA-7M Data Sheet [1].
2.1 Power management
2.1.1 Overview
The EVA-7M provides 4 supply pins: VCC, VCC_IO, V_BCKP and V_USB. They can be supplied independently or
tied together to adapt various concepts, depending on the intended application. The different supply voltages
are explained in the following subsections.
Figure 1 shows an example to supply the EVA-7M module when not using the USB interface. In this case, the
V_USB pin is connected to ground.
Figure 1: EVA-7M power supply example

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2.1.1.1 Main supply voltage (VCC)
During operation, the EVA-7M module is supplied through the VCC pin. It makes use of an internal DC/DC
converter for improved power efficiency. In a following step, built-in LDOs generate stabilized voltages for the
Core and RF domains of the chip respectively. The current at VCC depends heavily on the current state of the
system and is in general very dynamic.
Do not add any series resistance (< 0.2 Ω) to the VCC supply, as it will generate input voltage noise due
to the dynamic current conditions.
2.1.1.2 I/O supply voltage (VCC_IO)
The digital I/Os of the EVA-7M can be supplied with a separate voltage from the host system connected to the
VCC_IO pin of the module. The wide range of VCC_IO allows seamless interfacing to standard logic voltage
levels. However, in most applications VCC_IO and VCC share the same voltage level and are tied together.
VCC_IO supplies also the RTC and the backup RAM (BBR) during normal operation.
VCC_IO must be supplied in order for the system to boot.
2.1.1.3 Backup power supply (V_BCKP)
In the event of a power failure at VCC_IO, the backup domain is supplied by V_BCKP.
If no backup supply is available, connect V_BCKP to VCC_IO.
Avoid high resistance on the V_BCKP line: During the switch from main supply to backup supply, a
short current adjustment peak can cause high voltage drop on the pin with possible malfunctions.
If the RTC frequency is derived from the main clock, the V_BCKP pin also supplies the clock domain if
there is a power failure at VCC_IO, meaning that the V_BCKP current will also be higher. Ensure that
the capacity of the backup battery chosen meets your requirements.
2.1.1.4 USB interface power supply
V_USB supplies I/Os of the USB interface. If the USB interface is being used, the system can be either self-
powered, i.e. powered independently from the USB bus, or it can be bus-powered, i.e. powered through the
USB connection. In bus-powered mode, the system supply voltages need to be generated from the USB supply
voltage VBUS.
If the USB interface is not used, the V_USB pin must be connected to GND.
2.1.2 Power management configuration
Depending on the application, the power supply schematic will differ. Some examples are shown in the
following sections:
•Single supply voltage for VCC and VCC_IO, no backup supply see Appendix, Figure 12
•Separate supply voltages for VCC, VCC_IO and V_BCKP see Appendix, Figure 13
•Single supply voltage for VCC and VCC_IO, use of a backup supply see Appendix, Figure 15
For description of the different operating modes see the EVA-7M Data Sheet [1].

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2.2 Interfaces
The EVA-7M provides UART, SPI and DDC (I2C compatible) interfaces for communication with a host CPU. A USB
interface is also available on dedicated pins (see section 2.2.4).
The UART, SPI and DDC pins are supplied by VCC_IO and operate at this voltage level.
Four dedicated pins can be configured as either 1 x UART and 1 x DDC or a single SPI interface selectable by
D_SEL pin. Table 1 below provides the port mapping details.
Pin 32 (D_SEL) = “high” (left open) Pin 32 (D_SEL) = “Low” (connected to GND)
UART TX SPI MISO
UART RX SPI MOSI
DDC SCL SPI CLK
DDC SDA SPI CS
Table 1: Communication Interfaces overview
It is not possible to use the SPI interface simultaneously with the DDC or UART interface.
For debugging purposes, it is recommended to have a second interface e.g. USB available that is
independent from the application and accessible via test-points.
For each interface, a dedicated pin can be defined to indicate that data is ready to be transmitted. The TX Ready
signal indicates that the receiver has data to transmit. A listener can wait on the TX Ready signal instead of
polling the DDC or SPI interfaces. The UBX-CFG-PRT message lets you configure the polarity and the number of
bytes in the buffer before the TX Ready signal goes active. The TX Ready function is disabled by default.
The TX Ready functionality can be enabled and configured by proper AT commands sent to the involved
u-blox wireless module supporting the feature. For more information see GPS Implementation and
Aiding Features in u-blox wireless modules [5].
The TX Ready feature is supported on version LEON FW 7.xx and LISA-U2 01S and above.
2.2.1 UART interface
A UART interface is available for serial communication to a host CPU. The UART interface supports configurable
data rates with the default at 9600 baud. Signal levels are related to the VCC_IO supply voltage. An interface
based on RS232 standard levels (+/- 7 V) can be realized using level shifter ICs such as the Maxim MAX3232.
Hardware handshake signals and synchronous operation are not supported.
A signal change on the UART RX pin can also be used to wake up the receiver in Power Save Mode (see the
u-blox 7 Receiver Description including Protocol Specification [2].).
2.2.2 Display Data Channel (DDC) Interface
An I2C compatible Display Data Channel (DDC) interface is available for serial communication with a host CPU.
The SCL and SDA pins have internal pull-up resistors sufficient for most applications. However, depending on the
speed of the host and the load on the DDC lines additional external pull-up resistors might be necessary. For
speed and clock frequency see the EVA-7M Data Sheet [1].
To make use of DDC interface the D_SEL pin has to be left open.
The EVA-7M DDC interface provides serial communication with u-blox wireless modules. See the
specification of the applicable wireless module to confirm compatibility.
For more information about DDC implementation refer to the u-blox 7 Receiver Description including Protocol
Specification [2].
2.2.3 SPI Interface
The SPI interface can be used to provide a serial communication with a host CPU. If the SPI interface is used,
UART and DDC are deactivated, because they share the same pins.

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To make use of the SPI interface, the D_SEL pin has to be connected to GND.
Connecting the D_SEL pin to GND will slightly increase the power consumption in Power Save Mode
ON/OFF operation and SW backup mode because of its internal pull-up resistor.
2.2.4 USB interface
The USB interface of the EVA-7M supports the full-speed data rate of 12 Mbit/s. It is compatible to the USB 2.0
FS standard. The interface requires some external components in order to implement the physical characteristics
required by the USB 2.0 specification. Figure 2 shows the interface pins and additional external components. In
order to comply with USB specifications, VBUS must be connected through a LDO (U2) to pin V_USB of the
EVA-7M. This ensures that the internal 1.5 kΩpull-up resistor on USB_DP gets disconnected when the USB host
shuts down VBUS.
Depending on the characteristics of the LDO (U2), for a self-powered design it is recommended to add a pull-
down resistor (R8) at its output to ensure V_USB does not float if a USB cable is not connected, i.e. when VBUS
is not present.
The interface can be used either in “self powered” or “bus powered” mode. The required mode can be
configured using the UBX-CFG-USB message. Also, the vendor ID, vendor string, product ID and product string
can be changed.
In order to get the 90 Ωdifferential impedance in between the USB_DM and USB_DP data line a 27Ωseries
resistor (R1,R2) must be placed into each data line (USB_DM and USB_DP).
Figure 2: USB interface
Name Component Function Comments
U2 LDO Regulates VBUS (4.4 …5.25 V)
down to a voltage of 3.3 V).
Almost no current requirement (~1 mA) if the GNSS receiver is operated as a
USB self-powered device, but if bus-powered LDO (U2) must be able to deliver
the maximum current of ~100 mA.
C2,C3 Capacitors Required according to the specification of LDO U2
D1 Protection
diodes
Protect circuit from overvoltage
/ ESD when connecting.
Use low capacitance ESD protection such as ST Microelectronics USBLC6-2.
R1, R2 Serial
termination
resistors
Establish a full-speed driver
impedance of 28…44 Ω
A value of 27
Ω
is recommended.
R8 Resistor Ensures defined signal at
V_USB when VBUS is not
connected / powered
100 k
Ω
is recommended for USB self-powered setup. For bus-powered setup
R8 is not required.
Table 2: Summary of USB external components
See Appendix A.5 and Appendix A.6 for reference schematics for self- and bus-powered operation.
If the USB interface is not used, connect V_USB to GND.