Ublox LEA-M8F Quick setup guide

LEA-M8F
u-blox M8 time and frequency reference
GNSS module
Hardware Integration Manual
Abstract
This document describes the hardware features and design-
in
aspects for the LEA-M8F time and frequency reference module. This
device incorporates the u-blox M8 concurrent GNSS IC
that can
receive GPS, GLONASS, BeiDou and QZSS signals.
It provides a low
phase noise 30.72MHz system reference oscillator disciplined by
GNSS, a precise and jitter-free time-
pulse and features high
sensitivity signal acquisition and single satelli
te timing with
automatic hold over during signal outage.
www.u
-blox.com
UBX
-14000034 - R03

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Document Information
Title LEA-M8F
Subtitle u-blox M8 time and frequency reference GNSS module
Document type Hardware Integration Manual
Document number UBX-14000034
Revision and Date R03 19-Aug-2014
Document status Early Production Information
Document status explanation
Objective Specification Document contains target values. Revised and supplementary data will be published later.
Advance Information Document contains data based on early testing. Revised and supplementary data will be published later.
Early Production Information Document contains data from product verification. Revised and supplementary data may be published later.
Production Information Document contains the final product specification.
This document applies to the following products:
Product name Type number ROM/FLASH version PCN reference
LEA-M8F LEA-M8F-0-00 FLASH FW2.20 FTS1.01 N/A
u-blox reserves all rights to this document and the information contained herein. Products, names, logos and designs described herein may in
whole or in part be subject to intellectual property rights. Reproduction, use, modification or disclosure to third parties of this document or
any part thereof without the express permission of u-blox is strictly prohibited.
The information contained herein is provided “as is” and u-blox assumes no liability for the use of the information. No warranty, either
express or implied, is given, including but not limited, with respect to the accuracy, correctness, reliability and fitness for a particular purpose
of the information. This document may be revised by u-blox at any time. For most recent documents, visit www.u-blox.com.
Copyright © 2014, u-blox AG.
u-blox®is a registered trademark of u-blox Holding AG in the EU and other countries. ARM®is the registered trademark of ARM Limited in
the EU and other countries.

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Contents
Contents..............................................................................................................................3
1Hardware description ..................................................................................................5
1.1 Overview .............................................................................................................................................. 5
1.2 Architecture.......................................................................................................................................... 6
1.3 Pin description for LEA-M8F designs ..................................................................................................... 7
1.4 Connecting power................................................................................................................................ 8
1.4.1 VCC .............................................................................................................................................. 8
1.4.2 V_BCKP......................................................................................................................................... 8
1.4.3 VCC_RF......................................................................................................................................... 8
1.5 Interfaces.............................................................................................................................................. 8
1.5.1 UART............................................................................................................................................. 8
1.5.2 USB ............................................................................................................................................... 8
1.5.3 Display Data Channel (DDC) .......................................................................................................... 9
1.5.4 SPI................................................................................................................................................. 9
1.5.5 DDC interface for External DAC Control...................................................................................... 10
1.6 I/O and Control Pins............................................................................................................................ 10
1.6.1 RESET_N...................................................................................................................................... 10
1.6.2 D_SEL.......................................................................................................................................... 10
1.6.3 FREQ_PHASE_IN0 / EXINT0, FREQ_PHASE_IN1 / EXTINT1............................................................. 11
1.6.4 REF_FREQ_OUT ........................................................................................................................... 11
1.6.5 TIMEPULSE / TP2 ......................................................................................................................... 11
1.7 Device Configuration.......................................................................................................................... 11
2Design .........................................................................................................................12
2.1 Layout: Footprint and paste mask ....................................................................................................... 12
2.1.1 Placement ................................................................................................................................... 12
2.1.2 Antenna connection and ground plane design ............................................................................ 13
2.1.3 Antenna micro strip connection................................................................................................... 15
2.2 GNSS Antenna Connection................................................................................................................. 16
2.2.1Passive Antenna Connection ....................................................................................................... 16
2.2.2 Active antenna connection .......................................................................................................... 17
3Migration to u-blox M8 modules ..............................................................................18
3.1 Software migration............................................................................................................................. 18
3.2 Hardware migration LEA-6T -> LEA-M8F ............................................................................................ 18
Supply Voltage .................................................................................................................19
4Product handling ........................................................................................................20
4.1 Packaging, shipping, storage and moisture preconditioning ............................................................... 20
4.2 Soldering ............................................................................................................................................ 20

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4.3 EOS/ESD/EMI precautions ................................................................................................................... 23
4.4 Applications with cellular modules...................................................................................................... 26
Appendix ..........................................................................................................................28
Recommended parts...................................................................................................................................... 28
Manufacturer....................................................................................................................28
Order No. ..........................................................................................................................28
Comments.........................................................................................................................28
Related documents...........................................................................................................29
Revision history................................................................................................................29
Contact..............................................................................................................................30

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1Hardware description
1.1 Overview
The u-blox LEA-M8F module is a standalone GNSS time and frequency reference product featuring the high
performance u-blox M8 positioning engine. The device provides multi-GNSS synchronization for cost-sensitive
network edge equipment including Small Cell and Femto wireless base-stations. The LEA-M8F module is a fully
self-contained phase and frequency reference based on GNSS, but can also be used as part of a complete timing
sub-system including macro-sniff (network listen), Synchronous Ethernet and packet timing.
The LEA-M8F module includes a low-noise 30.72 MHz VCTCXO meeting the master reference requirements for
LTE Small Cells and providing 100 ppb autonomous hold-over. An external TCXO or OCXO can also be
measured and controlled for TD-LTE, LTE-Advanced and other applications requiring extended hold-over.
External sources of synchronization are supported through time-pulse and frequency inputs and a message
interface. This allows measurements from macro-sniff, Synchronous Ethernet or packet timing to be combined
with measurements from GNSS.
The industry standard LEA form factor in the leadless chip carrier (LCC) package makes the LEA-M8F easy to
integrate, while combining exceptional timing and frequency performance with highly flexible design and
connectivity options. SMT pads allow fully automated assembly with standard pick & place and reflow-soldering
equipment for cost-efficient, high-volume production enabling short time-to-market.
For product features see the LEA-M8F Data Sheet [1].
To determine which u-blox product best meets your needs, see the product selector tables on the u-blox
website www.u-blox.com.

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1.2 Architecture
Figure 1 shows a block schematic view of the module’s internal organization.
Figure 1: LEA-M8F Block Diagram
The device contains all the elements required to implement a multi-GNSS frequency and time synchronization
system. It comprises a u-blox M8030 GNSS receiver, RF LNA/SAW filter and disciplined VCTCXO. A FLASH
memory contains the FTS firmware and provides configuration storage.

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1.3 Pin description for LEA-M8F designs
Function PIN No I/O Description Remarks
Power VCC 6 I Supply Voltage Provide a clean and stable supply.
GND 7,
13-
15,
17
I Ground Assure a low impedance GND connection to all GND pins of
the module, preferably with a large ground.
V_BCKP 11 I connect to VCC. (Back-up mode not supported)
VDDUSB 24 I USB Power Supply To use the USB interface connect this pin to 3.0 – 3.6 V
derived from VBUS.
If no USB serial port used connect to GND.
Antenna RF_INPUT 16 I GPS/GLONASS/
BeiDou/signal input
from antenna
Use a controlled impedance transmission line of 50 Ωto
connect to RF_IN.
Don’t supply DC through this pin. Use V_ANT pin to supply
power.
VCC_RF 18 O Output Voltage RF
section
Can be used to power an external active antenna
Ω
). The max
power consumption of the Antenna must not exceed the
datasheet specification of the module.
Leave open if not used.
V_ANT 19 I Antenna Bias voltage Connect to GND (or leave open) if Passive Antenna is used. If
an active Antenna is used, add a 10 Ωresistor in front of
V_ANT input to the Antenna Bias Voltage or VCC_RF
Reserved 20 I Leave open
UART TxD1/MISO/
TX ready
3 O Serial Port 1 or SPI
Data i/p
Communication interface o/p function dependent on D_SEL. It
can also can be programmed as TX ready for DDC interface.
Leave open if not used.
RxD1/MOSI 4 I Serial Port 1 or SPI
Data o/p
Communication interface i/p dependent on D_SEL with
internal pull-up resistor to VCC. Leave open if not used. Don’t
use external pull up resistor.
USB USB_DM 25 I/O USB I/O line USB2.0 bidirectional communication pin. Leave open if
unused. For example implementations see section 1.5.2
USB_DP 26 I/O USB I/O line
System RESET_N 10 I Hardware Reset
(Active Low)
Leave open if not used.
TIMEPULSE/TP2/
SAFEBOOT_N
28 I/O Timepulse Signal Configurable Timepulse signal (one pulse per second by
default). Leave open if not used.
FREQ_PHASE_IN0/
EXTINT0
27 I TimePulse/Frequency General purpose frequency/phase measurement input 0,
Alternate function: External Interrupt 0
FREQ_PHASE_IN1/
EXTINT1
21 I TimePulse/Frequency General purpose frequency/phase measurement input 1
Alternate function: External Interrupt 1
REF_FREQ_OUT 9 I VCTCXO o/p Buffered output from the disciplined internal 30.72MHz
VCTCXO
SDA
/CS_N
1
I/O
DDC Data Pin
or SPI chip sel.
DDC Data. Leave open if not used.
or SPI chip select: dependent on DSEL
SCL
/SCLK
2 I/O DDC Clk Pin
or SPI clk
DDC Clock. Leave open if not used.
or SPI clock: dependent on DSEL
SAFEBOOT_N 12 I Test-point for service access. Leave open, do not drive low.
D_SEL 5 Selects the
interface protocol
Used to select UART+DDC or SPI
Open = UART+DDC; low = SPI on pins 1,2,3,4
SDA_DAC 22 I/O DDC Data pin For DAC control of external Freq Reference Only
SCL_DAC 23 O DDC Clk pin For DAC control of external Freq Reference Only
Table 1: LEA-M8F Pinout

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1.4 Connecting power
The u-blox LEA-M8F module has three power supply pins: VCC, V_BCKP and VDD_USB.
1.4.1 VCC
The VCC pin provides the main supply voltage. During operation, the current drawn by the module can vary by
some orders of magnitude. For this reason, it is important that the supply circuitry be able to support the peak
power for a short time. For specification see the LEA-M8F Data Sheet [1].
Use a proper GND concept with preferably low ESR decoupling capacitors at the module supply input.
Do not use any resistors or coils in the power line.
1.4.2 V_BCKP
This pin must be connected to the main module supply VCC.
1.4.3 VCC_RF
The VCC_RF pin provides a filtered source of DC to power an active antenna or external LNA. For more
information, see section 2.2.
1.5 Interfaces
The following interfaces are available for communication with a host for control and data handling.
1.5.1 UART
The LEA-M8F module includes a Universal Asynchronous Receiver Transmitter (UART) serial interface RxD/TxD
supporting configurable baud rates. See the LEA-M8F Data Sheet [1] for the supported baud rates.
The signal input and output levels are 0 V to VCC with inverted logic. An interface based on RS232 standard
levels (+/- 12 V) can be implemented using level shifters such as a Maxim MAX3232.
The interface does not support hardware handshake signals or synchronous operation.
Designs must allow access to the UART and the SAFEBOOT_N pin for future service, updates and
reconfiguration.
1.5.2 USB
A USB 2.0 (Full Speed, 12 Mb/s) compatible interface is available for communication as a development option.
The module is not designed to use the USB interface in an operational sense as the message latency cannot be
guaranteed.
The USB_DP pin has a pull-up resistor to signal a full-speed device to the USB host. The VDD_USB pin requires
connection to a 3 V (nom.) source to enable the USB interface. If the USB interface is not used, connect
VDD_USB to GND.
u-blox provides Microsoft® certified USB drivers for Windows XP, Windows Vista, Windows 7 and Windows 8
operating systems. These drivers are available for down-load at our website: www.u-blox.com
The USB port is for non-operational use e.g. for evaluation or firmware down-load

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1.5.2.1 USB external components
The USB interface requires some external components to comply with the USB 2.0 specification. These are
shown below in Figure 2 and listed in Table 2. To comply with USB specifications, VBUS must be connected
through an LDO (U1) to pin 24 (VDD_USB) to regulate the 5 V VBUS down to a nominal 3.3 V for the module.
The LEA-M8F module USB interface is intended to be used as a USB self-powered device deriving its power
supply from VCC. However, the module power supply (VCC) can be turned off independently of the host VBUS
supplying VDD_USB. With VDD_USB active, the USB host would receive a signal indicating that the device is
present and ready to communicate. This should be avoided by disabling the LDO (U1) using the enable signal
(EN) of the VCC-LDO enabled by e.g. VCC. Depending on the characteristics of the LDO (U1) it is recommended
to add a pull-down resistor (R11) at its output to ensure VDD_USB is not floating if the LDO (U1) is disabled or
the USB cable is disconnected i.e. VBUS is not supplied.
Module
VDD_USB
LDO
VDD_USB
R4
USB_DP
USB_DM
R5
C24 C23
D2
VBUS
DP
DM
GND
USB Device Connector
U1
EN R11
EN
Figure 2: USB Interface
Name Component Function Comments
U1 LDO Regulates VBUS (4.4 …5.25 V)
down to a voltage of 3.3 V.
Almost no current requirement (~1 mA) if the GNSS receiver is operated as a
USB self-powered device.
C23,
C24
Capacitors Required according to the specification of LDO U1
D2 Protection
diodes
Protect circuit from overvoltage
/ ESD when connecting.
Use low capacitance ESD protection such as ST Microelectronics USBLC6-2.
R4, R5 Serial
termination
resistors
Establish a full-speed driver
impedance of 28…44 Ω
A value of 27 Ωis recommended.
R11 Resistor 100 kΩis recommended for USB self-powered setup. For bus-powered setup,
R11 can be ignored.
Table 2: Summary of USB external components
1.5.3 Display Data Channel (DDC)
An I2C compatible Display Data Channel (DDC) interface is available for serial communication with an external
host CPU. The interface only supports slave mode operation (master mode is not supported). The DDC protocol
and electrical interface are fully compatible with the Fast-Mode of the I2C industry standard. The DDC pins SDA
and SCL have internal 10 kΩpull-up resistors.
For more information about the DDC implementation, see the u-blox M8 Receiver Description Including Protocol
Specification [2]. For bandwidth information, see the LEA-M8F Data Sheet [1]. For timing, parameters consult the
I2C-bus specification [8].
The u-blox M8 DDC interface supports serial communication with u-blox cellular modules. See the
specification of the applicable cellular module to confirm compatibility.
1.5.4 SPI
An SPI interface is available for communication to a host CPU, however its interface connections are shared with
the UART and DDC interface pins.The SPI interface is not available in the default configuration but can be

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enabled by connecting pin 5 (D_SEL) to ground - see 1.6.2 below. For speed and clock frequency specifications,
see the LEA-M8F Data Sheet [1].
1.5.5 DDC interface for External DAC Control
A dedicated DDC (I2C) interface (pins SDA_DAC, SCL_DAC) is provided for implementations in which the LEA-
M8F controls an external voltage controlled frequency reference via a DAC. This is set up via FTS specific
configuration messages. See the u-blox M8 Receiver Description Protocol Specification [2] and the u-blox M8F
Applications Guide [3] for more information. The DDC pins SDA_DAC and SCL_DAC have internal 10 kΩpull-
up resistors.
When the LEA-M8F is configured to discipline a voltage controlled oscillator via the dedicated DDC interface
(SDA_DAC, SCL_DAC) a choice must be made with respect to the DAC component. The recommended types
(TI or Microchip) offer 16 or 12 bit resolution respectively and should be chosen for the desired performance/cost
requirements. This section shows a suggested circuitry for implementing a 16 bit TI DAC analog filter
combination connected to a VCTCXO/VCOCXO. Note that 12 bit DAC may not provide sufficient resolution if
used over the full circuit voltage range and hence may compromise the controlled frequency performance.
Implementing a circuit using a smaller DAC voltage range and adding the output to a fixed low noise offset
voltage would be beneficial.
Figure 3: 16 bit DAC connection for VCOCXO control
1.6 I/O and Control Pins
1.6.1 RESET_N
RESET_N is an input-only pin with an internal pull-up resistor. The LEA-M8F performs an automatic reset
function on application of the power supply but this input may also be used to re-start the device during
operation if necessary. The pin must be held low for at least 10 ms to ensure RESET_N is detected. Leave
RESET_N open for normal operation. The RESET_N input complies with the power supply VCC voltage level and
can be actively driven high. Use this pin only to reset the module. Do not use RESET_N to turn the module on
and off since the reset state increases power consumption.
1.6.2 D_SEL
The D_SEL pin selects the available communication interfaces available at the module pins. This allows a choice
between UART+DDC or SPI control of the module, see Table 3 below. If D_SEL is left open both UART and DDC
are available. If pulled low, a single SPI interface is available. See the LEA-M8F Data Sheet [1].