Ublox NEO-D9C Use and care manual


NEO-D9C
u-blox D9 QZSS correction service receiver
Integration manual
Abstract
This document describes the features and specifications of the NEO-D9C
QZSS correction service receiver.
www.u-blox.com
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Document information
Title NEO-D9C
Subtitle u-blox D9 QZSS correction service receiver
Document type Integration manual
Document number UBX-21031631
Revision and date R02 16-Dec-2021
Disclosure restriction C1-Public
This document applies to the following products:
Type number FW version IN/PCN reference RN reference
NEO-D9C-00A-00 QZS 1.01 - UBX-21030680
NEO-D9C-00B-02 QZS 1.01 - UBX-21030680
u-blox or third parties may hold intellectual property rights in the products, names, logos and designs included in this
document. Copying, reproduction, modification or disclosure to third parties of this document or any part thereof is only
permitted with the express written permission of u-blox.
The information contained herein is provided "as is" and u-blox assumes no liability for its use. No warranty, either express
or implied, is given, including but not limited to, with respect to the accuracy, correctness, reliability and fitness for a
particular purpose of the information. This document may be revised by u-blox at any time without notice. For the most recent
documents, visit www.u-blox.com.
Copyright © 2021, u-blox AG.
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Contents
1 Integration manual overview............................................................................................. 5
2 System description...............................................................................................................6
2.1 Overview.................................................................................................................................................... 6
2.1.1 QZSS L6 augmentation service.................................................................................................. 6
2.2 Architecture..............................................................................................................................................8
2.2.1 Block diagram..................................................................................................................................8
3 Receiver functionality.......................................................................................................... 9
3.1 Receiver configuration........................................................................................................................... 9
3.1.1 Changing the receiver configuration..........................................................................................9
3.1.2 Default QZSS configuration.........................................................................................................9
3.1.3 Default interface settings............................................................................................................ 9
3.1.4 Basic receiver configuration...................................................................................................... 10
3.1.5 QZSS L6 satellite and message selection..............................................................................10
3.1.6 QZSS L6 data message output................................................................................................ 13
3.2 Communication interfaces................................................................................................................. 14
3.2.1 UART............................................................................................................................................... 15
3.2.2 I2C interface..................................................................................................................................16
3.2.3 SPI interface..................................................................................................................................19
3.2.4 USB interface................................................................................................................................20
3.3 Predefined PIOs.....................................................................................................................................21
3.3.1 D_SEL..............................................................................................................................................21
3.3.2 RESET_N........................................................................................................................................ 21
3.3.3 SAFEBOOT_N................................................................................................................................21
3.3.4 Extended TX timeout.................................................................................................................. 22
3.4 Security................................................................................................................................................... 22
3.4.1 Receiver status monitoring....................................................................................................... 22
3.5 Forcing a receiver reset....................................................................................................................... 22
3.6 Firmware upload....................................................................................................................................22
4 Design..................................................................................................................................... 24
4.1 Pin assignment......................................................................................................................................24
4.2 Antenna...................................................................................................................................................25
4.2.1 Antenna bias................................................................................................................................. 27
4.3 Power supply..........................................................................................................................................30
4.3.1 VCC: Main supply voltage.......................................................................................................... 30
4.3.2 NEO-D9C power supply.............................................................................................................. 30
4.4 NEO-D9C minimal design................................................................................................................... 30
4.5 EOS/ESD precautions.......................................................................................................................... 31
4.5.1 ESD protection measures.......................................................................................................... 31
4.5.2 EOS precautions...........................................................................................................................32
4.5.3 Safety precautions...................................................................................................................... 32
4.6 Electromagnetic interference on I/O lines.......................................................................................32
4.6.1 General notes on interference issues......................................................................................33
4.6.2 In-band interference mitigation................................................................................................33
4.6.3 Out-of-band interference........................................................................................................... 34
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4.7 Layout......................................................................................................................................................34
4.7.1 Placement...................................................................................................................................... 34
4.7.2 Thermal management................................................................................................................ 34
4.7.3 Package footprint, copper and paste mask........................................................................... 35
4.7.4 Layout guidance........................................................................................................................... 36
4.8 Design guidance....................................................................................................................................39
4.8.1 General considerations............................................................................................................... 39
4.8.2 RF front-end circuit options...................................................................................................... 39
4.8.3 Antenna/RF input........................................................................................................................ 40
4.8.4 Ground pads.................................................................................................................................. 41
4.8.5 Schematic design........................................................................................................................ 41
4.8.6 Layout design-in guideline......................................................................................................... 41
5 Product handling................................................................................................................. 42
5.1 ESD handling precautions.................................................................................................................. 42
5.2 Soldering.................................................................................................................................................42
5.3 Tapes....................................................................................................................................................... 45
5.4 Reels........................................................................................................................................................ 46
5.5 Moisture sensitivity levels.................................................................................................................. 46
Appendix.................................................................................................................................... 48
A Stacked patch antenna..........................................................................................................................48
B Glossary......................................................................................................................................................49
Related documents................................................................................................................ 51
Revision history.......................................................................................................................52

NEO-D9C-Integration manual
1 Integration manual overview
This document is an important source of information on all aspects of NEO-D9C QZSS correction
service receiver. The purpose of this document is to provide guidelines for a successful integration
of the receiver with the customer's end product.
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2 System description
2.1 Overview
The NEO-D9C receiver supports the QZSS L6 signals, QZSS Centimeter Level Augmentation
Service (CLAS) and experimental MADOCA service. The QZSS CLAS service provides high-accuracy
augmentation to GNSS receivers. The CLAS service is available over mainland Japan for free.
Combined with other products from u-blox, NEO-D9C builds a complete and stand-alone high
precision system providing users with access to free high-accuracy correction services and
ultimately centimeter-level GNSS accuracy.
2.1.1 QZSS L6 augmentation service
The QZSS L6 signal is available on satellites in a Quasi-Zenith Orbit over the Asia-Pacific region and
in geosynchronous orbit above Indonesia.
The QZSS L6 is a signal for augmentation corrections. It is transmitted at a frequency of 1278.75
MHz in the L6/E6 band. This signal provides two systems for corrections:
• CLAS: Centimetre Level Augmentation Service
• MADOCA: Multi-GNSS Advanced Demonstration Tool for Orbit and Clock Analysis
The CLAS service is targeted for less than 10 cm performance while MADOCA is a decimeter
correction service. Both these services are SSR corrections services that provide corrections that
are usable for a much larger area than what can be provided with the standard OSR corrections such
as VRS.
Figure 1: QZSS coverage area - image QZSS Japan
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Figure 2: QZSS satellite orbits - image QZSS Japan
The QZSS service transmits signals from the L5 band up to and including the L1 band.
The NEO-D9C requires the QZSS L2C signals as well as the QZSS L6 signal in order to
operate. It cannot provide the L6 message data without first acquiring the QZSS L2C signal.
The antenna providing the signal to the NEO-D9C must provide coverage of the L2C band and the
L6 band. Any RF circuitry on the PCB must be designed to consider this.
Figure 3: QZSS satellite - image QZSS Japan
The QZSS performance standard specification (PS-QZSS-001) and interface specification for QZSS
L6 (IS-QZSS-L6-001) is available from the QZSS http://qzss.go.jp/en/technical/ps-is-qzss/ps-is-
qzss.html.
The MADOCA L6E message specification can be found on the GPAS http://file.gpas.co.jp/
L6E_MADOCA_DataFormat_E.pdf.
The subframe data for the CLAS and MADOCA service is provided in a UBX message: UBX-RXM-
QZSSL6.
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2.2 Architecture
The NEO-D9C receiver provides all the necessary RF and baseband processing to enable multi-
constellation operation. The block diagram below shows the key functionality.
2.2.1 Block diagram
Figure 4: NEO-D9C block diagram
An active antenna is mandatory with the NEO-D9C.
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3 Receiver functionality
This section describes the NEO-D9C operational features and their configuration.
3.1 Receiver configuration
u-blox positioning receivers are fully configurable with UBX protocol messages. The configuration
used by the receiver during normal operation is called the "current configuration". The current
configuration can be changed during normal operation by sending UBX configuration messages. On
start-up the current configuration held in RAM is built from the default firmware settings plus any
settings held in flash memory.
A configuration setting stored in RAM remains effective until power-down or reset. Configuration
settings can be saved permanently in flash memory.
Configuration interface settings are held in a database consisting of separate configuration items.
An item is made up of a pair consisting of a key ID and a value. Related items are grouped together
and identified under a common group name: CFG-GROUP-*; a convention used in u-center and
within this document. Within u-center, a configuration group is identified as "Group name" and the
configuration item is identified as the "item name" under the "Generation 9 Configuration View" -
"Advanced Configuration" view.
The UBX messages available to change or poll the configurations are the UBX-CFG-VALSET, UBX-
CFG-VALGET, and UBX-CFG-VALDEL messages. For more information about these messages and
the configuration keys see the configuration interface section in the applicable interface description
[2].
3.1.1 Changing the receiver configuration
The configuration messages UBX-CFG-VALSET, UBX-CFG-VALGET and UBX-CFG-VALDEL will
result in a UBX-ACK-ACK or a UBX-ACK-NAK response.
3.1.2 Default QZSS configuration
The default QZSS configurations are:
• QZSS L2C
• QZSS L6
The QZSS L2C reception is always enabled as it is required and is transparent to user.
The QZSS L6 reception is configurable for satellite selection and L6D or L6E message
selection, or it can be left in an automatic mode. However both messages can be provided
simultaneously if required.
The configuration settings can be modified using UBX protocol configuration messages. For more
information, see the NEO-D9C Interface description [2].
QZSS L2C QZSS L6
Enabled Enabled
3.1.3 Default interface settings
Interface Settings
UART 9600 baud, 8 bits, no parity bit, 1 stop bit.
Output protocol: UBX. Only the following UBX message (if enabled) will be output if there is valid
data: UBX-RXM-QZSSL6.
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Interface Settings
Input protocols without need of additional configuration: UBX.
USB Output messages activated as in UART. Input protocols available as in UART.
I2C Output messages activated as in UART. Input protocols available as in UART.
SPI Output messages activated as in UART. Input protocols available as in UART.
Table 1: Default interface settings
The boot message is still output using $GNTXT messages. The messages are output when
the NEO-D9C is powered up.
Refer to the applicable interface description [2] for information about further settings.
3.1.4 Basic receiver configuration
This section summarizes the basic receiver configuration most commonly used.
3.1.4.1 Communication interface configuration
Several configuration items allow operation mode configuration of the various communications
interfaces. This includes parameters for the data framing, transfer rate and protocols used. See
Communication interfaces for details. The configuration items available for each interface are:
• UART1 interface: CFG-UART1-*, CFG-UART1INPROT-*, CFG-UART1OUTPROT-*
• UART2 interface: CFG-UART2-*, CFG-UART2INPROT-*, CFG-UART2OUTPROT-*
• SPI interface: CFG-SPI-*, CFG-SPIINPROT-*, CFG-SPIOUTPROT-*
• I2C interface: CFG-I2C-*, CFG-I2CINPROT-*, CFG-I2COUTPROT-*
• USB interface: CFG-USB-*, CFG-USBINPROT-*, CFG-USBOUTPROT-*
3.1.4.2 Message output configuration
The rate of UBX protocol output messages is configurable. If the rate configuration value is zero,
then the corresponding message will not be output. Values greater than zero indicate how often the
message is output.
For periodic output messages the rate relates to the event the message is related to. If the rate of
this message is set to one (1), it will be output for every epoch. If the rate is set to two (2), it will
be output every other epoch. The rates of the output messages are individually configurable per
communication interface. See the CFG-MSGOUT-* configuration group.
Some messages, such as UBX-MON-VER, are not periodic and will only be output as the answer to
a poll request.
The UBX-INF-* information messages are non-periodic output messages that do not have a
message rate configuration. Instead they can be enabled for each communication interface via the
CFG-INFMSG-* configuration group.
All message output is additionally subject to the protocol configuration of the
communication interfaces. Messages of a given protocol will not be output until the protocol
is enabled for output on the interface (see previous section).
3.1.5 QZSS L6 satellite and message selection
The D9C receivers support tracking up to 6 QZSS satellites in L2 band (L2CM/L2CL) and decoding
up to two L6 channels concurrently. As a result, a maximum of two QZSS L6 sat messages can be
provided. These messages can be from two different QZSS L6 satellites if needed.
There is no pilot signal on the L6 band, and the tracking parameters must be obtained from the
corresponding L2 signal. Therefore, the NEO-D9C needs to receive QZSS L2 signals and QZSS L6
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signals in order to operate. Ensure the receiving antenna used supports L2 and L6 signals. It will first
acquire the QZSS L2 signals before acquiring the QZSS L6 signals.
The L6 messages can be the L6D and the L6E message at the same time if required. The RXM-
QZSSL6 message has two channels, therefore only two possible L6 message streams can be
provided. If using two QZSS satellites to provide the L6 message data, only one message stream
from each can be the output in the RXM-QZSSL6 message.
Figure 5: Maximum number of QZSS sats that can be tracked
As shown below a single QZSS satellite will provide both the L6D and L6E messages.
Satellite QZSS 1 (Block 1) only transmits the L6D message. If manually selected or
automatically selected it will be possible only to decode an L6D channel message from this
satellite.
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Figure 6: QZSS L6 single satellite messages
Two QZSS satellites can be used as a source for either the L6D or L6E message. Only a maximum
of two satellites can be used to provide the L6 messages.
Figure 7: QZSS L6 double satellite messages
The required QZSS L6 satellite ID and message can be selected using the following configuration
keys:
• CFG-QZSS-L6_SVIDA
• CFG-QZSS-L6_SVIDB
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• CFG-QZSS-L6_MSGA
• CFG-QZSS-L6_MSGB
There are two message channels (A-B). Each of these channels can output QZSS L6 message L6D
or L6E.
By default the firmware has the SVIDA and SVIDB set to "0". The default selection for MSGA and
MSGB is set to L6D message for both channels. With this selection the firmware will acquire the two
strongest QZSS satellites and provide the L6D message on both channels.
If SVIDA is set to a SVID rather than the default of "0" it will acquire the SVID selected. SVIDB can
remain set to "0" and will acquire the QZSS satellite with the highest C/N0.
In the UBX-RXM-QZSSL6 output message the C/N0 reported will be for the L6 signal level and not
for the QZSS L2 signal level.
The NEO-D9C and ZED-F9x should be powered on at the same time to ensure the NEO-D9C receives
the messages at the correct time.
In order to ensure a fast start-up and re-acquisition time the NEO-D9C can be aided by the
ZED-F9x. This is done by inputting the following 3 UBX messages.
The three UBX messages that can be enabled on the ZED-F9x and sent into the NEO-D9C are:
• UBX-NAV-PVT
• UBX-NAV-TIMEGPS
• UBX-RXM-SFRBX
No other UBX/NMEA messages should be sent into the NEO-D9C.
If the ZED-F9x and the NEO-D9C are directly connected by UART, only the three indicated messages
should be enabled on the ZED-F9x output interface. No NMEA messages should be enabled.
The USB interfaces of the ZED-F9x and NEO-D9C can be used as host interface. If the host interface
is only UART1 for both units, the host application must re-direct the three required messages to the
NEO-D9C input.
3.1.6 QZSS L6 data message output
The L6 data is transmitted from the satellites in 250-symbol subframes with duration of 1000 ms.
The subframe begins with a 4-symbol fixed preamble pattern 0x1A, 0xCF, 0xFC, 0x1D, followed by
214 data symbols and 32 Reed-Solomon parity symbols. The message structure is the same for
both L6D and L6E signals.
Figure 8: QZSS L6 subframe
The contents of this L6 message are explained in the IS-QZSS-L6-001 specification for the QZSS
L6D/E service.
The NEO-D9C is simply a data link layer receiver for the CLAS/MADOCA correction data, and
other services transmitted on the QZSS L6 band. It does not parse, assemble or post-process the
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message content in any way. The only processing done on the raw subframe-level data is error
detection and correction, according to the receiver’s configuration.
There are three possible modes of operation:
1. No error detection or correction. The data is sent out as is, framed at the QZSS L6 250-byte
boundary.
2. Error detection only. The data is sent out as is, but the frame is accompanied by a meta-data
header indicating whether or not the message passed to the Reed-Solomon error detection.
3. Error detection and correction. The received complete subframes are passed to Reed-
Solomon error correction. If the data contains any errors, either preamble or payload,
error recovery is attempted. If the error correction results in a frame that passes the error
detection, the corrected frame is sent out accompanied with a meta-data header indicating
how many bytes were corrected. This includes the preamble bytes. Hence, the maximum
number of correctable errors is 20 (up to 4 errors in the preamble and up to 16 in the payload
in the Reed-Solomon). If the error correction fails, the received data is sent out as is (without
applying any correction attempts, including the preamble) and the frame is marked as
erroneous.
The NEO-D9C will output the raw QZSS L6 data messages in the UBX-RXM-QZSSL6 message. This
message can contain both the L6D and L6E service data if required.
3.2 Communication interfaces
u-blox receivers are equipped with a communication interface which is multi-protocol capable. The
interface ports can be used to transmit GNSS measurements, monitor status information and
configure the receiver.
A protocol (e.g. UBX, NMEA) can be assigned to several ports simultaneously, each configured with
individual settings (e.g. baud rate, message rates, etc.). More than one protocol (e.g. UBX protocol
and NMEA) can be assigned to a single port (multi-protocol capability), which is particularly useful
for debugging purposes.
The NEO-D9C provides UART1, UART2, SPI, I2C and USB interfaces for communication with a
host CPU. The interfaces are configured via the configuration methods described in the applicable
interface description [2].
The following table shows the port numbers reported in the UBX-MON-COMMS messages.
Port no. UBX-MON-COMMS portId Electrical interface
0 0x0000 I2C
1 0x0100 UART1
2 0x0200 UART2
3 0x0300 USB
4 0x0400 SPI
Table 2: Port number assignment
It is important to isolate interface pins when VCC is removed. They can be allowed to float
or be connected to a high impedance (Float or tri-state: Hi-Z state). Open collector circuits
powered by module VCC are also suitable. They must be powered by module VCC to ensure
correct pin state when module VCC is removed.
Example isolation circuit is shown below.
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Figure 9: NEO-D9C output isolation
Figure 10: NEO-D9C input isolation
3.2.1 UART
A Universal Asynchronous Receiver/Transmitter (UART) port consists of an RX and a TX line. Neither
handshaking signals nor hardware flow control signals are available. The UART interface protocol
and baud rate can be configured but there is no support for setting different baud rates for reception
and transmission.
The NEO-D9C includes two UART serial ports. UART1 can be used as a host interface for
configuration, monitoring and control.
UART2 may be used to provide correction data directly to a high precision GNSS receiver
from the u-blox F9 platform. To check whether a specific u-blox F9 product supports
correction data output by the NEO-D9C, refer to its Integration manual.
The UART RX interface will be disabled when more than 100 frame errors are detected
during a one-second period. This can happen if the wrong baud rate is used or the UART RX
pin is grounded. An error message appears when the UART RX interface is re-enabled at the
end of the one-second period.
Baud rate Data bits Parity Stop bits
9600 8 none 1
19200 8 none 1
38400 8 none 1
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Baud rate Data bits Parity Stop bits
57600 8 none 1
115200 8 none 1
230400 8 none 1
460800 8 none 1
921600 8 none 1
Table 3: Possible UART interface configurations
Users should allow a short time delay of typically 100 ms between sending a baud rate change
message and providing input data at the new rate. Otherwise some input characters may be ignored
or the port could be disabled until the interface is able to process the new baud rate.
Note that for protocols such as UBX, it does not make sense to change the default word length
values (data bits) since these properties are defined by the protocol and not by the electrical
interface.
If the amount of data configured is too much for a certain port's bandwidth (e.g. all UBX messages
output on a UART port with a baud rate of 9600), the buffer will fill up. Once the buffer space is
exceeded, new messages to be sent will be dropped. To prevent message loss, the baud rate and
communication speed or the number of enabled messages should be carefully selected so that the
expected number of bytes can be transmitted in less than one second.
3.2.2 I2C interface
An I2C interface is available for communication with an external host CPU or u-blox cellular modules.
The interface can be operated in slave mode only. The I2C protocol and electrical interface are fully
compatible with the I2C industry standard fast mode. Since the maximum SCL clock frequency
is 400 kHz, the maximum transfer rate is 400 kb/s. The SCL and SDA pins have internal pull-up
resistors which should be sufficient for most applications. However, depending on the speed of the
host and the load on the I2C lines additional external pull-up resistors may be necessary.
To use the I2C interface D_SEL pin must be left open.
In designs where the host uses the same I2C bus to communicate with more than one u-
blox receiver, the I2C slave address for each receiver must be configured to a different value.
Typically most u-blox receivers are configured to the same default I2C slave address value.
To poll or set the I2C slave address, use the CFG-I2C-ADDRESS configuration item (see the
applicable interface description [2]).
The CFG-I2C-ADDRESS configuration item is an 8-bit value containing the I2C slave address
in 7 most significant bits, and the read/write flag in the least significant bit.
3.2.2.1 I2C register layout
The I2C interface allows 256 registers to be addressed. As shown in Figure 11, only three of these
are currently implemented.
The data registers 0 to 252 at addresses 0x00 to 0xFC contain reserved information, the result from
their reading is currently undefined. The data registers 0 to 252 are 1 byte wide.
At addresses 0xFD and 0xFE it is possible to read the currently available number of bytes.
The register at address 0xFF allows the data stream to be read. If there is no data awaiting
transmission from the receiver, then this register delivers value 0xFF, which cannot be the first byte
of a valid message. If the message data is ready for transmission, the successive reads of register
0xFF will deliver the waiting message data.
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Do not use registers 0x00 to 0xFC. They are reserved for future use and they do not
currently provide any meaningful data.
Figure 11: I2C register layout
3.2.2.2 Read access types
There are two I2C read transfer forms:
• The "random access" form: includes a slave register address and allows any register to be read.
• The "current address" form: omits the register address.
Figure 12 shows the format of the first one, the "random access" form of the request. Following
the start condition from the master, the 7-bit device address and the RW bit (which is a logic low
for write access) are clocked onto the bus by the master transmitter. The receiver answers with an
acknowledge (logic low) to indicate that it recognizes the address.
Next, the 8-bit address of the register to be read must be written to the bus. Following the receiver's
acknowledgment, the master again triggers a start condition and writes the device address, but this
time the RW bit is a logic high to initiate the read access. Now, the master can read 1 to N bytes
from the receiver, generating a not-acknowledge and a stop condition after the last byte being read.
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Figure 12: I2C random read access
If the second form, "current address" is used, an address pointer in the receiver is used to determine
which register to read. This address pointer will increment after each read unless it is already
pointing at register 0xFF, the highest addressable register, in which case it remains unaltered.
The initial value of this address pointer at start-up is 0xFF, so by default all current address reads
will repeatedly read register 0xFF and receive the next byte of message data (or 0xFF if no message
data is waiting).
Figure 13: I2C current address read access
3.2.2.3 Write access
The receiver does not provide any write access except for writing UBX and NMEA messages to the
receiver, such as configuration or aiding data. Therefore, the register set mentioned in the section
Read access is not writeable.
Following the start condition from the master, the 7-bit device address and the RW bit (which is a
logic low for write access) are clocked onto the bus by the master transmitter. The receiver answers
with an acknowledge (logic low) to indicate that it is responsible for the given address.
The master can write 2 to N bytes to the receiver, generating a stop condition after the last byte
being written. The number of data bytes must be at least 2 to properly distinguish from the write
access to set the address counter in random read accesses.
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Figure 14: I2C write access
3.2.3 SPI interface
NEO-D9C has an SPI slave interface that can be selected by setting D_SEL = 0. The SPI slave
interface is shared with UART1 and I2C port, the physical pins are same. The SPI pins available are:
• SPI_MISO (TXD)
• SPI_MOSI (RXD)
• SPI_CS_N
• SPI_CLK
See more information about communication interface selection from the D_SEL section.
The SPI interface is designed to allow communication to a host CPU. The interface can be operated
in slave mode only.
3.2.3.1 Read access
As the register mode is not implemented for the SPI port, only the UBX/NMEA message stream is
provided. This stream is accessed using the back-to-back read and write access (see section Back-
to-back read and write access below). When no data is available to be written to the receiver, MOSI
should be held logic high, i.e. all bytes written to the receiver are set to 0xFF.
To prevent the receiver from being busy parsing incoming data, the parsing process is stopped after
50 subsequent bytes containing 0xFF. The parsing process is re-enabled with the first byte not equal
to 0xFF.
If the receiver has no more data to send, it sets MISO to logic high, i.e. all bytes transmitted decode
to 0xFF. An efficient parser in the host will ignore all 0xFF bytes which are not part of a message and
will resume data processing as soon as the first byte not equal to 0xFF is received.
3.2.3.2 Back-to-back read and write access
The receiver does not provide any write access except for writing UBX and NMEA messages to
the receiver, such as configuration or aiding data. For every byte written to the receiver, a byte will
simultaneously be read from the receiver. While the master writes to MOSI, at the same time it needs
to read from MISO, as any pending data will be output by the receiver with this access. The data
on MISO represents the results from a current address read, returning 0xFF when no more data is
available.
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Figure 15: SPI back-to-back read/write access
3.2.4 USB interface
A single USB port is provided for host communication purposes.
The USB 2.0 FS (Full speed, 12 Mbit/s) interface can be used for host communication. Due to the
hardware implementation, it may not be possible to certify the USB interface.
If the receiver executes code from internal ROM (i.e. when a valid flash firmware image is not
detected), the USB behavior can differ compared to executing a firmware image from flash memory.
USB host compatibility testing is thus recommended in this scenario.
The NEO-D9C receiver supports only self-powered mode operation in which the receiver is supplied
from its own power supply. The V_USB pin is used to detect the availability of the USB port, i.e.
whether the receiver is connected to a USB host.
USB suspend mode is not supported.
USB bus-powered mode is not supported.
It is important to connect V_USB to ground and leave data lines open when the USB
interface is not used in an application.
The voltage range for V_USB is specified from 3.0 V to 3.6 V, which differs slightly from the
specification for VCC.
The boot screen is retransmitted on the USB port after enumeration. However, messages
generated between boot-up of the receiver and USB enumeration are not visible on the USB
port.
There are additional hardware requirements if USB is used:
• V_USB (pin 7) requires 1 uF capacitor mounted adjacent to the pin to ensure correct V_USB
voltage detection
• The V_USB (Pin 7) voltage should be sourced from an LDO enabled by the module VCC and
supplied from the USB host.
• A pull-down resistor is required on the output of this V_USB LDO
• Pin 5 is USB_DM. Pin 6 is USB_DP.
• Apply USB_DM and USB_DP series resistors; typically 27 Ω
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